From mboxrd@z Thu Jan  1 00:00:00 1970
From: Simon Glass <sjg@chromium.org>
Date: Sat, 2 Nov 2019 15:04:41 -0600
Subject: [U-Boot] [PATCH v3 013/108] x86: spi: Add helper functions for
	Intel Fast SPI
In-Reply-To: <CAEUhbmW9GUfPyip36g0ke9H_W8882CmuP497Le9ijhnR_SF2nA@mail.gmail.com>
References: <20191021033322.217715-2-sjg@chromium.org>
 <20191021033322.217715-14-sjg@chromium.org>
 <CAEUhbmW9GUfPyip36g0ke9H_W8882CmuP497Le9ijhnR_SF2nA@mail.gmail.com>
Message-ID: <CAPnjgZ1+sCz2gPOHzMzfnvN8FmSzfM5j0Z9ryQxSKU1ut2+EbA@mail.gmail.com>
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Hi Bin,

On Fri, 1 Nov 2019 at 22:14, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Mon, Oct 21, 2019 at 11:33 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
> > top of 32-bit address space, so that it can be executed in place and read
> > simply by copying from memory. For an 8MB ROM the mapping starts at
> > 0xff800000.
> >
> > However some recent Intel CPUs do not use a simple 1:1 memory map. Instead
> > the map starts at a different address and not all of the SPI flash is
> > accessible through the map. This 'Fast SPI' feature requires that U-Boot
> > check the location of the map. It is also possible (optionally) to read
> > from the SPI flash using a driver.
> >
> > Add support for booting from Fast SPI. The memory-mapped version is used
> > by both TPL and SPL on apollolake.
> >
> > In respect of a SPI flash driver, the actual SPI driver is ich.c - this
> > just adds a few helper functions and definitions.
> >
> > This is used by Apollolake.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v3:
> > - Add support for of-platdata for TPL
> > - Add the missing header file
> > - Change Fast-SPI driver into a helper file used by ICH SPI
> > - Don't include write() and erase() in TPL
> > - Merge in patch "x86: Add support for booting from Fast SPI"
> > - Reorder file so that write() and erase() are together
> > - Use pci_get_devfn()
> >
> > Changes in v2: None
> >
> >  arch/x86/cpu/intel_common/Makefile   |  1 +
> >  arch/x86/cpu/intel_common/fast_spi.c | 73 ++++++++++++++++++++++++++++
> >  arch/x86/include/asm/fast_spi.h      | 68 ++++++++++++++++++++++++++
> >  arch/x86/include/asm/spl.h           |  1 +
> >  4 files changed, 143 insertions(+)
> >  create mode 100644 arch/x86/cpu/intel_common/fast_spi.c
> >  create mode 100644 arch/x86/include/asm/fast_spi.h
[..]

> > +/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
> > +struct fast_spi_regs {
> > +       u32 bfp;
> > +       u32 hsfsts_ctl;
> > +       u32 faddr;
> > +       u32 dlock;
> > +
> > +       u32 fdata[0x10];
> > +
> > +       u32 fracc;
> > +       u32 freg[12];
> > +       u32 fpr[5];
> > +       u32 gpr0;
> > +       u32 spare2;
> > +       u32 sts_ctl;
> > +       u16 preop;              /* a4 */
>
> I assume a4 is the offset of preop? Leaving it causes confusion and it
> can be dropped, I think.
>

Will do.

I'm rebasing on your applied patches and moving the code around to
address Andy's comments. I'll send a new version v4 by Monday.

Regards,
Simon