From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Glass Date: Fri, 18 Dec 2015 19:52:05 -0700 Subject: [U-Boot] [PATCH 04/10] x86: ivybridge: Add microcode blobs for all the steppings In-Reply-To: <1449831353-933-5-git-send-email-bmeng.cn@gmail.com> References: <1449831353-933-1-git-send-email-bmeng.cn@gmail.com> <1449831353-933-5-git-send-email-bmeng.cn@gmail.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 11 December 2015 at 03:55, Bin Meng wrote: > This adds microcode blobs created from Intel FSP package for the > Chief River platform. They are for all the Ivy Bridge steppings: > 306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the > 306a9 which is already in the U-Boot tree. > > Signed-off-by: Bin Meng > --- > > arch/x86/dts/microcode/m12306a2_00000008.dtsi | 554 +++++++++++++++++++++ > arch/x86/dts/microcode/m12306a4_00000007.dtsi | 618 +++++++++++++++++++++++ > arch/x86/dts/microcode/m12306a5_00000007.dtsi | 618 +++++++++++++++++++++++ > arch/x86/dts/microcode/m12306a8_00000010.dtsi | 682 ++++++++++++++++++++++++++ > 4 files changed, 2472 insertions(+) > create mode 100644 arch/x86/dts/microcode/m12306a2_00000008.dtsi > create mode 100644 arch/x86/dts/microcode/m12306a4_00000007.dtsi > create mode 100644 arch/x86/dts/microcode/m12306a5_00000007.dtsi > create mode 100644 arch/x86/dts/microcode/m12306a8_00000010.dtsi Acked-by: Simon Glass Tested on link (ivybridge non-FSP) Tested-by: Simon Glass