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diff for duplicates of <CAPnjgZ1Rv_U5Vod7gP5B8vTZo46b6cjEV4WrFwSWt_P=yj1VeA@mail.gmail.com>

diff --git a/a/1.txt b/N1/1.txt
index 98dcea8..b334374 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -22,10 +22,10 @@ On Thu, Jan 19, 2012 at 5:03 PM, Stephen Warren <swarren@nvidia.com> wrote:
 >> + - compatible : Should be "manufacture,device", "nand-flash"
 >> + - page-data-bytes : Number of bytes in the data area
 >> + - page-spare-bytes : * Number of bytes in spare area
->> +       spare area = skipped-spare-bytes + data-ecc-bytes + tag-bytes
->> +                     + tag-ecc-bytes
+>> + ? ? ? spare area = skipped-spare-bytes + data-ecc-bytes + tag-bytes
+>> + ? ? ? ? ? ? ? ? ? ? + tag-ecc-bytes
 >> + - skipped-spare-bytes : Number of bytes to skip at start of spare area
->> +     (these are typically used for bad block maintenance)
+>> + ? ? (these are typically used for bad block maintenance)
 >> + - data-ecc-bytes : Number of ECC bytes for data area
 >> + - tag-bytes :Number of tag bytes in spare area
 >> + - tag-ecc-bytes : Number ECC bytes to be generated for tag bytes
@@ -76,19 +76,19 @@ Yes.
 >> +Optional properties:
 >> +
 >> +wp-gpio : GPIO of write-protect line, three cells in the format:
->> +             phandle, parameter, flags
+>> + ? ? ? ? ? ? phandle, parameter, flags
 >> +width : bus width of the NAND device in bits
 >> +
 >> +For now here is something specific to the Nvidia controller, with naming
 >> +based on Nvidia's original (non-fdt) NAND driver:
 >> +
 >> + - nvidia,nand-timing : Timing parameters for the NAND. Each is in ns.
->> +     Order is: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH),
->> +     TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL
+>> + ? ? Order is: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH),
+>> + ? ? TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL
 >> +
->> +     MAX_TRP_TREA is:
->> +             non-EDO mode: Max(tRP, tREA) + 6ns
->> +             EDO mode: tRP timing
+>> + ? ? MAX_TRP_TREA is:
+>> + ? ? ? ? ? ? non-EDO mode: Max(tRP, tREA) + 6ns
+>> + ? ? ? ? ? ? EDO mode: tRP timing
 >
 > At first glance, it seems reasonable to have this in the NAND node; it's
 > certainly impossible to probe the timing parameters. Since NAND is so
@@ -110,20 +110,20 @@ sidetracked on some average of all the NAND datasheets.
 >
 >> +Example:
 >> +
->> +nand-controller@0x70008000 {
->> +     compatible = "nvidia,tegra20-nand";
->> +     wp-gpios = <&gpio 59 0>;                /* PH3 */
->> +     width = <8>;
->> +     nvidia,timing = <26 100 20 80 20 10 12 10 70>;
->> +     nand@0 {
->> +             compatible = "hynix,hy27uf4g2b", "nand-flash";
->> +             page-data-bytes = <2048>;
->> +             tag-ecc-bytes = <4>;
->> +             tag-bytes = <20>;
->> +             data-ecc-bytes = <36>;
->> +             skipped-spare-bytes = <4>;
->> +             page-spare-bytes = <64>;
->> +     };
+>> +nand-controller at 0x70008000 {
+>> + ? ? compatible = "nvidia,tegra20-nand";
+>> + ? ? wp-gpios = <&gpio 59 0>; ? ? ? ? ? ? ? ?/* PH3 */
+>> + ? ? width = <8>;
+>> + ? ? nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+>> + ? ? nand at 0 {
+>> + ? ? ? ? ? ? compatible = "hynix,hy27uf4g2b", "nand-flash";
+>> + ? ? ? ? ? ? page-data-bytes = <2048>;
+>> + ? ? ? ? ? ? tag-ecc-bytes = <4>;
+>> + ? ? ? ? ? ? tag-bytes = <20>;
+>> + ? ? ? ? ? ? data-ecc-bytes = <36>;
+>> + ? ? ? ? ? ? skipped-spare-bytes = <4>;
+>> + ? ? ? ? ? ? page-spare-bytes = <64>;
+>> + ? ? };
 >> +};
 >
 > --
diff --git a/a/content_digest b/N1/content_digest
index 8d948a7..6730cad 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -11,19 +11,13 @@
   "From\0Simon Glass <sjg\@chromium.org>\0"
 ]
 [
-  "Subject\0Re: [PATCH 3/6] tegra: fdt: Add NAND controller binding and definitions\0"
+  "Subject\0[U-Boot] [PATCH 3/6] tegra: fdt: Add NAND controller binding and definitions\0"
 ]
 [
   "Date\0Fri, 13 Apr 2012 10:44:28 -0700\0"
 ]
 [
-  "To\0Stephen Warren <swarren\@nvidia.com>\0"
-]
-[
-  "Cc\0Devicetree Discuss <devicetree-discuss\@lists.ozlabs.org>",
-  " U-Boot Mailing List <u-boot\@lists.denx.de>",
-  " Jerry Van Baren <vanbaren\@cideas.com>",
-  " Tom Warren <TWarren\@nvidia.com>\0"
+  "To\0u-boot\@lists.denx.de\0"
 ]
 [
   "\0000:1\0"
@@ -56,10 +50,10 @@
   ">> + - compatible : Should be \"manufacture,device\", \"nand-flash\"\n",
   ">> + - page-data-bytes : Number of bytes in the data area\n",
   ">> + - page-spare-bytes : * Number of bytes in spare area\n",
-  ">> + \302\240 \302\240 \302\240 spare area = skipped-spare-bytes + data-ecc-bytes + tag-bytes\n",
-  ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 + tag-ecc-bytes\n",
+  ">> + ? ? ? spare area = skipped-spare-bytes + data-ecc-bytes + tag-bytes\n",
+  ">> + ? ? ? ? ? ? ? ? ? ? + tag-ecc-bytes\n",
   ">> + - skipped-spare-bytes : Number of bytes to skip at start of spare area\n",
-  ">> + \302\240 \302\240 (these are typically used for bad block maintenance)\n",
+  ">> + ? ? (these are typically used for bad block maintenance)\n",
   ">> + - data-ecc-bytes : Number of ECC bytes for data area\n",
   ">> + - tag-bytes :Number of tag bytes in spare area\n",
   ">> + - tag-ecc-bytes : Number ECC bytes to be generated for tag bytes\n",
@@ -110,19 +104,19 @@
   ">> +Optional properties:\n",
   ">> +\n",
   ">> +wp-gpio : GPIO of write-protect line, three cells in the format:\n",
-  ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 phandle, parameter, flags\n",
+  ">> + ? ? ? ? ? ? phandle, parameter, flags\n",
   ">> +width : bus width of the NAND device in bits\n",
   ">> +\n",
   ">> +For now here is something specific to the Nvidia controller, with naming\n",
   ">> +based on Nvidia's original (non-fdt) NAND driver:\n",
   ">> +\n",
   ">> + - nvidia,nand-timing : Timing parameters for the NAND. Each is in ns.\n",
-  ">> + \302\240 \302\240 Order is: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH),\n",
-  ">> + \302\240 \302\240 TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL\n",
+  ">> + ? ? Order is: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH),\n",
+  ">> + ? ? TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL\n",
   ">> +\n",
-  ">> + \302\240 \302\240 MAX_TRP_TREA is:\n",
-  ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 non-EDO mode: Max(tRP, tREA) + 6ns\n",
-  ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 EDO mode: tRP timing\n",
+  ">> + ? ? MAX_TRP_TREA is:\n",
+  ">> + ? ? ? ? ? ? non-EDO mode: Max(tRP, tREA) + 6ns\n",
+  ">> + ? ? ? ? ? ? EDO mode: tRP timing\n",
   ">\n",
   "> At first glance, it seems reasonable to have this in the NAND node; it's\n",
   "> certainly impossible to probe the timing parameters. Since NAND is so\n",
@@ -144,20 +138,20 @@
   ">\n",
   ">> +Example:\n",
   ">> +\n",
-  ">> +nand-controller\@0x70008000 {\n",
-  ">> + \302\240 \302\240 compatible = \"nvidia,tegra20-nand\";\n",
-  ">> + \302\240 \302\240 wp-gpios = <&gpio 59 0>; \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240/* PH3 */\n",
-  ">> + \302\240 \302\240 width = <8>;\n",
-  ">> + \302\240 \302\240 nvidia,timing = <26 100 20 80 20 10 12 10 70>;\n",
-  ">> + \302\240 \302\240 nand\@0 {\n",
-  ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 compatible = \"hynix,hy27uf4g2b\", \"nand-flash\";\n",
-  ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 page-data-bytes = <2048>;\n",
-  ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 tag-ecc-bytes = <4>;\n",
-  ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 tag-bytes = <20>;\n",
-  ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 data-ecc-bytes = <36>;\n",
-  ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 skipped-spare-bytes = <4>;\n",
-  ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 page-spare-bytes = <64>;\n",
-  ">> + \302\240 \302\240 };\n",
+  ">> +nand-controller at 0x70008000 {\n",
+  ">> + ? ? compatible = \"nvidia,tegra20-nand\";\n",
+  ">> + ? ? wp-gpios = <&gpio 59 0>; ? ? ? ? ? ? ? ?/* PH3 */\n",
+  ">> + ? ? width = <8>;\n",
+  ">> + ? ? nvidia,timing = <26 100 20 80 20 10 12 10 70>;\n",
+  ">> + ? ? nand at 0 {\n",
+  ">> + ? ? ? ? ? ? compatible = \"hynix,hy27uf4g2b\", \"nand-flash\";\n",
+  ">> + ? ? ? ? ? ? page-data-bytes = <2048>;\n",
+  ">> + ? ? ? ? ? ? tag-ecc-bytes = <4>;\n",
+  ">> + ? ? ? ? ? ? tag-bytes = <20>;\n",
+  ">> + ? ? ? ? ? ? data-ecc-bytes = <36>;\n",
+  ">> + ? ? ? ? ? ? skipped-spare-bytes = <4>;\n",
+  ">> + ? ? ? ? ? ? page-spare-bytes = <64>;\n",
+  ">> + ? ? };\n",
   ">> +};\n",
   ">\n",
   "> --\n",
@@ -167,4 +161,4 @@
   "Simon"
 ]
 
-c01b90d37eaed14ab69e61f3ef2376ff583d8e7865333e8bd1b50b3c2dffd9c1
+9f2dad02fbf26ab5cd50b578eaeaf394af669391eafaa51abb149c508012fbcb
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