* [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188
@ 2016-07-15 22:17 Heiko Stuebner
2016-07-15 22:17 ` [U-Boot] [PATCH 1/9] cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming Heiko Stuebner
` (9 more replies)
0 siblings, 10 replies; 36+ messages in thread
From: Heiko Stuebner @ 2016-07-15 22:17 UTC (permalink / raw)
To: u-boot
I've made some nice progress on using mainline uboot on the rk3188
and would like to dump some first results.
Right now I can use uboot on the rk3188 with the Rockchip binary ddr init,
similar to what barebox does and can even netboot a kernel image using
a usb ethernet adapter [0] .
While working on this I found quite some cosmetic stuff that shouldn't
persist to make extending easier. So while I don't know what the policy
is for my standalone pinctrl and clock drivers (without the actual board)
at least the cosmetics + fix might get in at least.
[0] https://github.com/mmind/u-boot-rockchip/commits/rk3188-netboot
Heiko Stuebner (9):
cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming
cosmetic: rockchip: rk3036: pinctrl: fix config symbol naming
cosmetic: rockchip: sort socs according to numbers
cosmetic: rockchip: rk3288: rename rkclk_configure_cpu
rockchip: rk3288: fix FREF_MIN_HZ constant
rockchip: rk3188: Add header files for PMU and GRF
rockchip: rk3188: Add pinctrl driver
rockchip: rk3188: Bring in rk3066/rk3188 clock bindings
rockchip: rk3188: Add clock driver
arch/arm/include/asm/arch-rockchip/clock.h | 2 +-
arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 186 +++++++
arch/arm/include/asm/arch-rockchip/grf_rk3188.h | 589 +++++++++++++++++++++++
arch/arm/include/asm/arch-rockchip/pmu_rk3188.h | 36 ++
arch/arm/mach-rockchip/Kconfig | 20 +-
arch/arm/mach-rockchip/Makefile | 4 +-
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 2 +-
configs/chromebook_jerry_defconfig | 2 +-
configs/evb-rk3036_defconfig | 2 +-
configs/firefly-rk3288_defconfig | 2 +-
configs/kylin-rk3036_defconfig | 2 +-
configs/rock2_defconfig | 2 +-
configs/sandbox_defconfig | 4 +-
configs/sandbox_noblk_defconfig | 4 +-
drivers/clk/Makefile | 1 +
drivers/clk/clk_rk3188.c | 464 ++++++++++++++++++
drivers/clk/clk_rk3288.c | 4 +-
drivers/pinctrl/Kconfig | 23 +-
drivers/pinctrl/rockchip/Makefile | 5 +-
drivers/pinctrl/rockchip/pinctrl_rk3188.c | 614 ++++++++++++++++++++++++
include/dt-bindings/clock/rk3066a-cru.h | 40 ++
include/dt-bindings/clock/rk3188-cru-common.h | 256 ++++++++++
include/dt-bindings/clock/rk3188-cru.h | 56 +++
23 files changed, 2286 insertions(+), 34 deletions(-)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3188.h
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3188.h
create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3188.h
create mode 100644 drivers/clk/clk_rk3188.c
create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3188.c
create mode 100644 include/dt-bindings/clock/rk3066a-cru.h
create mode 100644 include/dt-bindings/clock/rk3188-cru-common.h
create mode 100644 include/dt-bindings/clock/rk3188-cru.h
--
2.8.0.rc3
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 1/9] cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming
2016-07-15 22:17 [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188 Heiko Stuebner
@ 2016-07-15 22:17 ` Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 2/9] cosmetic: rockchip: rk3036: " Heiko Stuebner
` (8 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Heiko Stuebner @ 2016-07-15 22:17 UTC (permalink / raw)
To: u-boot
The rk3288 pinctrl is very specific to this soc, so should
not hog the generic rockchip naming.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
configs/chromebook_jerry_defconfig | 2 +-
configs/firefly-rk3288_defconfig | 2 +-
configs/rock2_defconfig | 2 +-
configs/sandbox_defconfig | 2 +-
configs/sandbox_noblk_defconfig | 2 +-
drivers/pinctrl/Kconfig | 6 +++---
drivers/pinctrl/rockchip/Makefile | 2 +-
7 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index d5bc515..fd5314a 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -53,7 +53,7 @@ CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK808=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index bdafc71..4122000 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -46,7 +46,7 @@ CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_ACT8846=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 3e16b80..3b6d7d9 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -44,7 +44,7 @@ CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_ACT8846=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 6a1874a..a5bb759 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -119,7 +119,7 @@ CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
-CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
CONFIG_ROCKCHIP_3036_PINCTRL=y
CONFIG_PINCTRL_SANDBOX=y
CONFIG_DM_PMIC=y
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
index 60c7339..2928da4 100644
--- a/configs/sandbox_noblk_defconfig
+++ b/configs/sandbox_noblk_defconfig
@@ -112,7 +112,7 @@ CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
-CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
CONFIG_ROCKCHIP_3036_PINCTRL=y
CONFIG_PINCTRL_SANDBOX=y
CONFIG_DM_PMIC=y
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 1785e3b..85dddd3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -123,12 +123,12 @@ config QCA953X_PINCTRL
both the GPIO definitions and pin control functions for each
available multiplex function.
-config ROCKCHIP_PINCTRL
+config ROCKCHIP_RK3288_PINCTRL
bool "Rockchip pin control driver"
depends on DM
help
- Support pin multiplexing control on Rockchip SoCs. The driver is
- controlled by a device tree node which contains both the GPIO
+ Support pin multiplexing control on Rockchip rk3288 SoCs. The driver
+ is controlled by a device tree node which contains both the GPIO
definitions and pin control functions for each available multiplex
function.
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index 6fa7d00..6a84961 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -5,5 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_ROCKCHIP_PINCTRL) += pinctrl_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o
obj-$(CONFIG_ROCKCHIP_3036_PINCTRL) += pinctrl_rk3036.o
--
2.8.0.rc3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 2/9] cosmetic: rockchip: rk3036: pinctrl: fix config symbol naming
2016-07-15 22:17 [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188 Heiko Stuebner
2016-07-15 22:17 ` [U-Boot] [PATCH 1/9] cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming Heiko Stuebner
@ 2016-07-15 22:17 ` Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 3/9] cosmetic: rockchip: sort socs according to numbers Heiko Stuebner
` (7 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Heiko Stuebner @ 2016-07-15 22:17 UTC (permalink / raw)
To: u-boot
Rockchip socs are always named rkxxxx in all places, as also shown
by the naming of the rk3036 pinctrl file itself.
Therefore also name the config symbol according to this scheme.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
configs/evb-rk3036_defconfig | 2 +-
configs/kylin-rk3036_defconfig | 2 +-
configs/sandbox_defconfig | 2 +-
configs/sandbox_noblk_defconfig | 2 +-
drivers/pinctrl/Kconfig | 2 +-
drivers/pinctrl/rockchip/Makefile | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 9894fff..2d5e5e0 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -32,7 +32,7 @@ CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
-CONFIG_ROCKCHIP_3036_PINCTRL=y
+CONFIG_ROCKCHIP_RK3036_PINCTRL=y
CONFIG_RAM=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DEBUG_UART=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 0ff6c6b..51196aa 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -32,7 +32,7 @@ CONFIG_SYSRESET=y
CONFIG_DM_MMC=y
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
-CONFIG_ROCKCHIP_3036_PINCTRL=y
+CONFIG_ROCKCHIP_RK3036_PINCTRL=y
CONFIG_RAM=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index a5bb759..7ea9d31 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -120,7 +120,7 @@ CONFIG_PCI_SANDBOX=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_ROCKCHIP_RK3288_PINCTRL=y
-CONFIG_ROCKCHIP_3036_PINCTRL=y
+CONFIG_ROCKCHIP_RK3036_PINCTRL=y
CONFIG_PINCTRL_SANDBOX=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_ACT8846=y
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
index 2928da4..503845b 100644
--- a/configs/sandbox_noblk_defconfig
+++ b/configs/sandbox_noblk_defconfig
@@ -113,7 +113,7 @@ CONFIG_PCI_SANDBOX=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_ROCKCHIP_RK3288_PINCTRL=y
-CONFIG_ROCKCHIP_3036_PINCTRL=y
+CONFIG_ROCKCHIP_RK3036_PINCTRL=y
CONFIG_PINCTRL_SANDBOX=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_ACT8846=y
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 85dddd3..951a922 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -132,7 +132,7 @@ config ROCKCHIP_RK3288_PINCTRL
definitions and pin control functions for each available multiplex
function.
-config ROCKCHIP_3036_PINCTRL
+config ROCKCHIP_RK3036_PINCTRL
bool "Rockchip rk3036 pin control driver"
depends on DM
help
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index 6a84961..0b2e95e 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -6,4 +6,4 @@
#
obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o
-obj-$(CONFIG_ROCKCHIP_3036_PINCTRL) += pinctrl_rk3036.o
+obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o
--
2.8.0.rc3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 3/9] cosmetic: rockchip: sort socs according to numbers
2016-07-15 22:17 [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188 Heiko Stuebner
2016-07-15 22:17 ` [U-Boot] [PATCH 1/9] cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming Heiko Stuebner
2016-07-15 22:17 ` [U-Boot] [PATCH 2/9] cosmetic: rockchip: rk3036: " Heiko Stuebner
@ 2016-07-15 22:17 ` Heiko Stuebner
2016-07-16 15:47 ` Andreas Färber
2016-07-17 14:13 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 4/9] cosmetic: rockchip: rk3288: rename rkclk_configure_cpu Heiko Stuebner
` (6 subsequent siblings)
9 siblings, 2 replies; 36+ messages in thread
From: Heiko Stuebner @ 2016-07-15 22:17 UTC (permalink / raw)
To: u-boot
Having some sort of ordering proofed helpful in a lot of other places
already. So for a larger number of rockchip socs it might be helpful
as well instead of an ever increasing unsorted list.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/mach-rockchip/Kconfig | 20 ++++++++++----------
arch/arm/mach-rockchip/Makefile | 4 ++--
drivers/pinctrl/Kconfig | 16 ++++++++--------
drivers/pinctrl/rockchip/Makefile | 2 +-
4 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 86b77f8..a3faafe 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -1,5 +1,14 @@
if ARCH_ROCKCHIP
+config ROCKCHIP_RK3036
+ bool "Support Rockchip RK3036"
+ select CPU_V7
+ help
+ The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
+ including NEON and GPU, Mali-400 graphics, several DDR3 options
+ and video codec support. Peripherals include Gigabit Ethernet,
+ USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+
config ROCKCHIP_RK3288
bool "Support Rockchip RK3288"
select CPU_V7
@@ -10,15 +19,6 @@ config ROCKCHIP_RK3288
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs.
-config ROCKCHIP_RK3036
- bool "Support Rockchip RK3036"
- select CPU_V7
- help
- The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
- including NEON and GPU, Mali-400 graphics, several DDR3 options
- and video codec support. Peripherals include Gigabit Ethernet,
- USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
-
config ROCKCHIP_SPL_BACK_TO_BROM
bool "SPL returns to bootrom"
default y if ROCKCHIP_RK3036
@@ -27,6 +27,6 @@ config ROCKCHIP_SPL_BACK_TO_BROM
SPL will return to the boot rom, which will then load the U-Boot
binary to keep going on.
-source "arch/arm/mach-rockchip/rk3288/Kconfig"
source "arch/arm/mach-rockchip/rk3036/Kconfig"
+source "arch/arm/mach-rockchip/rk3288/Kconfig"
endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 6763af4..722b582 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -5,8 +5,8 @@
#
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
+obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
obj-$(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) += save_boot_param.o
else
obj-$(CONFIG_ROCKCHIP_RK3288) += board.o
@@ -14,5 +14,5 @@ endif
ifndef CONFIG_ARM64
obj-y += rk_timer.o
endif
-obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
+obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 951a922..2972dba 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -123,21 +123,21 @@ config QCA953X_PINCTRL
both the GPIO definitions and pin control functions for each
available multiplex function.
-config ROCKCHIP_RK3288_PINCTRL
- bool "Rockchip pin control driver"
+config ROCKCHIP_RK3036_PINCTRL
+ bool "Rockchip rk3036 pin control driver"
depends on DM
help
- Support pin multiplexing control on Rockchip rk3288 SoCs. The driver
- is controlled by a device tree node which contains both the GPIO
+ Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is
+ controlled by a device tree node which contains both the GPIO
definitions and pin control functions for each available multiplex
function.
-config ROCKCHIP_RK3036_PINCTRL
- bool "Rockchip rk3036 pin control driver"
+config ROCKCHIP_RK3288_PINCTRL
+ bool "Rockchip pin control driver"
depends on DM
help
- Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is
- controlled by a device tree node which contains both the GPIO
+ Support pin multiplexing control on Rockchip rk3288 SoCs. The driver
+ is controlled by a device tree node which contains both the GPIO
definitions and pin control functions for each available multiplex
function.
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index 0b2e95e..64e9587 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -5,5 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o
+obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o
--
2.8.0.rc3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 4/9] cosmetic: rockchip: rk3288: rename rkclk_configure_cpu
2016-07-15 22:17 [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188 Heiko Stuebner
` (2 preceding siblings ...)
2016-07-15 22:17 ` [U-Boot] [PATCH 3/9] cosmetic: rockchip: sort socs according to numbers Heiko Stuebner
@ 2016-07-15 22:17 ` Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 5/9] rockchip: rk3288: fix FREF_MIN_HZ constant Heiko Stuebner
` (5 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Heiko Stuebner @ 2016-07-15 22:17 UTC (permalink / raw)
To: u-boot
The function is very specific to the rk3288 in its arguments
referencing the rk3288 cru and grf and every other rockchip soc
has differing cru and grf registers. So make that function naming
explicit.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/include/asm/arch-rockchip/clock.h | 2 +-
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 2 +-
drivers/clk/clk_rk3288.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 317e512..4bebd62 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -65,6 +65,6 @@ void *rockchip_get_cru(void);
struct rk3288_cru;
struct rk3288_grf;
-void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
+void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
#endif
diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index b36b6af..fc0f2f3 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -784,7 +784,7 @@ static int veyron_init(struct dram_info *priv)
return ret;
udelay(100);/* Must wait for voltage to stabilize, 2mV/us */
- rkclk_configure_cpu(priv->cru, priv->grf);
+ rk3288_clk_configure_cpu(priv->cru, priv->grf);
return 0;
}
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 679f010..dece4bc 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -447,7 +447,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
}
#endif
-void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
+void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
{
/* pll enter slow-mode */
rk_clrsetreg(&cru->cru_mode_con,
--
2.8.0.rc3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 5/9] rockchip: rk3288: fix FREF_MIN_HZ constant
2016-07-15 22:17 [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188 Heiko Stuebner
` (3 preceding siblings ...)
2016-07-15 22:17 ` [U-Boot] [PATCH 4/9] cosmetic: rockchip: rk3288: rename rkclk_configure_cpu Heiko Stuebner
@ 2016-07-15 22:17 ` Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 6/9] rockchip: rk3188: Add header files for PMU and GRF Heiko Stuebner
` (4 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Heiko Stuebner @ 2016-07-15 22:17 UTC (permalink / raw)
To: u-boot
According to the TRM the minimum FREF frequency is 269kHz not MHz.
Adapt the constant accordingly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/clk/clk_rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index dece4bc..a41cf8b 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -47,7 +47,7 @@ enum {
OUTPUT_MAX_HZ = 2200U * 1000000,
OUTPUT_MIN_HZ = 27500000,
FREF_MAX_HZ = 2200U * 1000000,
- FREF_MIN_HZ = 269 * 1000000,
+ FREF_MIN_HZ = 269 * 1000,
};
enum {
--
2.8.0.rc3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 6/9] rockchip: rk3188: Add header files for PMU and GRF
2016-07-15 22:17 [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188 Heiko Stuebner
` (4 preceding siblings ...)
2016-07-15 22:17 ` [U-Boot] [PATCH 5/9] rockchip: rk3288: fix FREF_MIN_HZ constant Heiko Stuebner
@ 2016-07-15 22:17 ` Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 7/9] rockchip: rk3188: Add pinctrl driver Heiko Stuebner
` (3 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Heiko Stuebner @ 2016-07-15 22:17 UTC (permalink / raw)
To: u-boot
PMU is the power management unit and GRF is the general register file. Both
are heavily used in U-Boot. Add header files with register definitions.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/include/asm/arch-rockchip/grf_rk3188.h | 589 ++++++++++++++++++++++++
arch/arm/include/asm/arch-rockchip/pmu_rk3188.h | 36 ++
2 files changed, 625 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3188.h
create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3188.h
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h
new file mode 100644
index 0000000..1a4f944
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h
@@ -0,0 +1,589 @@
+/*
+ * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_GRF_RK3188_H
+#define _ASM_ARCH_GRF_RK3188_H
+
+struct rk3188_grf_gpio_lh {
+ u32 l;
+ u32 h;
+};
+
+struct rk3188_grf {
+ struct rk3188_grf_gpio_lh gpio_dir[4];
+ struct rk3188_grf_gpio_lh gpio_do[4];
+ struct rk3188_grf_gpio_lh gpio_en[4];
+
+ u32 reserved[2];
+ u32 gpio0c_iomux;
+ u32 gpio0d_iomux;
+
+ u32 gpio1a_iomux;
+ u32 gpio1b_iomux;
+ u32 gpio1c_iomux;
+ u32 gpio1d_iomux;
+
+ u32 gpio2a_iomux;
+ u32 gpio2b_iomux;
+ u32 gpio2c_iomux;
+ u32 gpio2d_iomux;
+
+ u32 gpio3a_iomux;
+ u32 gpio3b_iomux;
+ u32 gpio3c_iomux;
+ u32 gpio3d_iomux;
+
+ u32 soc_con0;
+ u32 soc_con1;
+ u32 soc_con2;
+ u32 soc_status0;
+
+ u32 busdmac_con[3];
+ u32 peridmac_con[4];
+
+ u32 cpu_con[6];
+ u32 reserved0[2];
+
+ u32 ddrc_con0;
+ u32 ddrc_stat;
+
+ u32 io_con[5];
+ u32 soc_status1;
+
+ u32 uoc0_con[4];
+ u32 uoc1_con[4];
+ u32 uoc2_con[2];
+ u32 reserved1;
+ u32 uoc3_con[2];
+ u32 hsic_stat;
+ u32 os_reg[8];
+
+ u32 gpio0_p[3];
+ u32 gpio1_p[3][4];
+
+ u32 flash_data_p;
+ u32 flash_cmd_p;
+};
+check_member(rk3188_grf, flash_cmd_p, 0x01a4);
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+ GPIO0D7_SHIFT = 14,
+ GPIO0D7_MASK = 1,
+ GPIO0D7_GPIO = 0,
+ GPIO0D7_SPI1_CSN0,
+
+ GPIO0D6_SHIFT = 12,
+ GPIO0D6_MASK = 1,
+ GPIO0D6_GPIO = 0,
+ GPIO0D6_SPI1_CLK,
+
+ GPIO0D5_SHIFT = 10,
+ GPIO0D5_MASK = 1,
+ GPIO0D5_GPIO = 0,
+ GPIO0D5_SPI1_TXD,
+
+ GPIO0D4_SHIFT = 8,
+ GPIO0D4_MASK = 1,
+ GPIO0D4_GPIO = 0,
+ GPIO0D4_SPI0_RXD,
+
+ GPIO0D3_SHIFT = 6,
+ GPIO0D3_MASK = 3,
+ GPIO0D3_GPIO = 0,
+ GPIO0D3_FLASH_CSN3,
+ GPIO0D3_EMMC_RSTN_OUT,
+
+ GPIO0D2_SHIFT = 4,
+ GPIO0D2_MASK = 3,
+ GPIO0D2_GPIO = 0,
+ GPIO0D2_FLASH_CSN2,
+ GPIO0D2_EMMC_CMD,
+
+ GPIO0D1_SHIFT = 2,
+ GPIO0D1_MASK = 1,
+ GPIO0D1_GPIO = 0,
+ GPIO0D1_FLASH_CSN1,
+
+ GPIO0D0_SHIFT = 0,
+ GPIO0D0_MASK = 3,
+ GPIO0D0_GPIO = 0,
+ GPIO0D0_FLASH_DQS,
+ GPIO0D0_EMMC_CLKOUT
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+ GPIO1A7_SHIFT = 14,
+ GPIO1A7_MASK = 3,
+ GPIO1A7_GPIO = 0,
+ GPIO1A7_UART1_RTS_N,
+ GPIO1A7_SPI0_CSN0,
+
+ GPIO1A6_SHIFT = 12,
+ GPIO1A6_MASK = 3,
+ GPIO1A6_GPIO = 0,
+ GPIO1A6_UART1_CTS_N,
+ GPIO1A6_SPI0_CLK,
+
+ GPIO1A5_SHIFT = 10,
+ GPIO1A5_MASK = 3,
+ GPIO1A5_GPIO = 0,
+ GPIO1A5_UART1_SOUT,
+ GPIO1A5_SPI0_TXD,
+
+ GPIO1A4_SHIFT = 8,
+ GPIO1A4_MASK = 3,
+ GPIO1A4_GPIO = 0,
+ GPIO1A4_UART1_SIN,
+ GPIO1A4_SPI0_RXD,
+
+ GPIO1A3_SHIFT = 6,
+ GPIO1A3_MASK = 1,
+ GPIO1A3_GPIO = 0,
+ GPIO1A3_UART0_RTS_N,
+
+ GPIO1A2_SHIFT = 4,
+ GPIO1A2_MASK = 1,
+ GPIO1A2_GPIO = 0,
+ GPIO1A2_UART0_CTS_N,
+
+ GPIO1A1_SHIFT = 2,
+ GPIO1A1_MASK = 1,
+ GPIO1A1_GPIO = 0,
+ GPIO1A1_UART0_SOUT,
+
+ GPIO1A0_SHIFT = 0,
+ GPIO1A0_MASK = 1,
+ GPIO1A0_GPIO = 0,
+ GPIO1A0_UART0_SIN,
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+ GPIO1B7_SHIFT = 14,
+ GPIO1B7_MASK = 1,
+ GPIO1B7_GPIO = 0,
+ GPIO1B7_SPI0_CSN1,
+
+ GPIO1B6_SHIFT = 12,
+ GPIO1B6_MASK = 3,
+ GPIO1B6_GPIO = 0,
+ GPIO1B6_SPDIF_TX,
+ GPIO1B6_SPI1_CSN1,
+
+ GPIO1B5_SHIFT = 10,
+ GPIO1B5_MASK = 3,
+ GPIO1B5_GPIO = 0,
+ GPIO1B5_UART3_RTS_N,
+ GPIO1B5_RESERVED,
+
+ GPIO1B4_SHIFT = 8,
+ GPIO1B4_MASK = 3,
+ GPIO1B4_GPIO = 0,
+ GPIO1B4_UART3_CTS_N,
+ GPIO1B4_GPS_RFCLK,
+
+ GPIO1B3_SHIFT = 6,
+ GPIO1B3_MASK = 3,
+ GPIO1B3_GPIO = 0,
+ GPIO1B3_UART3_SOUT,
+ GPIO1B3_GPS_SIG,
+
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 3,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_UART3_SIN,
+ GPIO1B2_GPS_MAG,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_UART2_SOUT,
+ GPIO1B1_JTAG_TDO,
+
+ GPIO1B0_SHIFT = 0,
+ GPIO1B0_MASK = 3,
+ GPIO1B0_GPIO = 0,
+ GPIO1B0_UART2_SIN,
+ GPIO1B0_JTAG_TDI,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+ GPIO1D7_SHIFT = 14,
+ GPIO1D7_MASK = 1,
+ GPIO1D7_GPIO = 0,
+ GPIO1D7_I2C4_SCL,
+
+ GPIO1D6_SHIFT = 12,
+ GPIO1D6_MASK = 1,
+ GPIO1D6_GPIO = 0,
+ GPIO1D6_I2C4_SDA,
+
+ GPIO1D5_SHIFT = 10,
+ GPIO1D5_MASK = 1,
+ GPIO1D5_GPIO = 0,
+ GPIO1D5_I2C2_SCL,
+
+ GPIO1D4_SHIFT = 8,
+ GPIO1D4_MASK = 1,
+ GPIO1D4_GPIO = 0,
+ GPIO1D4_I2C2_SDA,
+
+ GPIO1D3_SHIFT = 6,
+ GPIO1D3_MASK = 1,
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_I2C1_SCL,
+
+ GPIO1D2_SHIFT = 4,
+ GPIO1D2_MASK = 1,
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_I2C1_SDA,
+
+ GPIO1D1_SHIFT = 2,
+ GPIO1D1_MASK = 1,
+ GPIO1D1_GPIO = 0,
+ GPIO1D1_I2C0_SCL,
+
+ GPIO1D0_SHIFT = 0,
+ GPIO1D0_MASK = 1,
+ GPIO1D0_GPIO = 0,
+ GPIO1D0_I2C0_SDA,
+};
+
+/* GRF_GPIO3A_IOMUX */
+enum {
+ GPIO3A7_SHIFT = 14,
+ GPIO3A7_MASK = 1,
+ GPIO3A7_GPIO = 0,
+ GPIO3A7_SDMMC0_DATA3,
+
+ GPIO3A6_SHIFT = 12,
+ GPIO3A6_MASK = 1,
+ GPIO3A6_GPIO = 0,
+ GPIO3A6_SDMMC0_DATA2,
+
+ GPIO3A5_SHIFT = 10,
+ GPIO3A5_MASK = 1,
+ GPIO3A5_GPIO = 0,
+ GPIO3A5_SDMMC0_DATA1,
+
+ GPIO3A4_SHIFT = 8,
+ GPIO3A4_MASK = 1,
+ GPIO3A4_GPIO = 0,
+ GPIO3A4_SDMMC0_DATA0,
+
+ GPIO3A3_SHIFT = 6,
+ GPIO3A3_MASK = 1,
+ GPIO3A3_GPIO = 0,
+ GPIO3A3_SDMMC0_CMD,
+
+ GPIO3A2_SHIFT = 4,
+ GPIO3A2_MASK = 1,
+ GPIO3A2_GPIO = 0,
+ GPIO3A2_SDMMC0_CLKOUT,
+
+ GPIO3A1_SHIFT = 2,
+ GPIO3A1_MASK = 1,
+ GPIO3A1_GPIO = 0,
+ GPIO3A1_SDMMC0_PWREN,
+
+ GPIO3A0_SHIFT = 0,
+ GPIO3A0_MASK = 1,
+ GPIO3A0_GPIO = 0,
+ GPIO3A0_SDMMC0_RSTN,
+};
+
+/* GRF_GPIO3B_IOMUX */
+enum {
+ GPIO3B7_SHIFT = 14,
+ GPIO3B7_MASK = 3,
+ GPIO3B7_GPIO = 0,
+ GPIO3B7_CIF_DATA11,
+ GPIO3B7_I2C3_SCL,
+
+ GPIO3B6_SHIFT = 12,
+ GPIO3B6_MASK = 3,
+ GPIO3B6_GPIO = 0,
+ GPIO3B6_CIF_DATA10,
+ GPIO3B6_I2C3_SDA,
+
+ GPIO3B5_SHIFT = 10,
+ GPIO3B5_MASK = 3,
+ GPIO3B5_GPIO = 0,
+ GPIO3B5_CIF_DATA1,
+ GPIO3B5_HSADC_DATA9,
+
+ GPIO3B4_SHIFT = 8,
+ GPIO3B4_MASK = 3,
+ GPIO3B4_GPIO = 0,
+ GPIO3B4_CIF_DATA0,
+ GPIO3B4_HSADC_DATA8,
+
+ GPIO3B3_SHIFT = 6,
+ GPIO3B3_MASK = 1,
+ GPIO3B3_GPIO = 0,
+ GPIO3B3_CIF_CLKOUT,
+
+ GPIO3B2_SHIFT = 4,
+ GPIO3B2_MASK = 1,
+ GPIO3B2_GPIO = 0,
+ /* no muxes */
+
+ GPIO3B1_SHIFT = 2,
+ GPIO3B1_MASK = 1,
+ GPIO3B1_GPIO = 0,
+ GPIO3B1_SDMMC0_WRITE_PRT,
+
+ GPIO3B0_SHIFT = 0,
+ GPIO3B0_MASK = 1,
+ GPIO3B0_GPIO = 0,
+ GPIO3B0_SDMMC_DETECT_N,
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+ GPIO3C7_SHIFT = 14,
+ GPIO3C7_MASK = 3,
+ GPIO3C7_GPIO = 0,
+ GPIO3C7_SDMMC1_WRITE_PRT,
+ GPIO3C7_RMII_CRS_DVALID,
+ GPIO3C7_RESERVED,
+
+ GPIO3C6_SHIFT = 12,
+ GPIO3C6_MASK = 3,
+ GPIO3C6_GPIO = 0,
+ GPIO3C6_SDMMC1_DECTN,
+ GPIO3C6_RMII_RX_ERR,
+ GPIO3C6_RESERVED,
+
+ GPIO3C5_SHIFT = 10,
+ GPIO3C5_MASK = 3,
+ GPIO3C5_GPIO = 0,
+ GPIO3C5_SDMMC1_CLKOUT,
+ GPIO3C5_RMII_CLKOUT,
+ GPIO3C5_RMII_CLKIN,
+
+ GPIO3C4_SHIFT = 8,
+ GPIO3C4_MASK = 3,
+ GPIO3C4_GPIO = 0,
+ GPIO3C4_SDMMC1_DATA3,
+ GPIO3C4_RMII_RXD1,
+ GPIO3C4_RESERVED,
+
+ GPIO3C3_SHIFT = 6,
+ GPIO3C3_MASK = 3,
+ GPIO3C3_GPIO = 0,
+ GPIO3C3_SDMMC1_DATA2,
+ GPIO3C3_RMII_RXD0,
+ GPIO3C3_RESERVED,
+
+ GPIO3C2_SHIFT = 4,
+ GPIO3C2_MASK = 3,
+ GPIO3C2_GPIO = 0,
+ GPIO3C2_SDMMC1_DATA1,
+ GPIO3C2_RMII_TXD0,
+ GPIO3C2_RESERVED,
+
+ GPIO3C1_SHIFT = 2,
+ GPIO3C1_MASK = 3,
+ GPIO3C1_GPIO = 0,
+ GPIO3C1_SDMMC1_DATA0,
+ GPIO3C1_RMII_TXD1,
+ GPIO3C1_RESERVED,
+
+ GPIO3C0_SHIFT = 0,
+ GPIO3C0_MASK = 3,
+ GPIO3C0_GPIO = 0,
+ GPIO3C0_SDMMC1_CMD,
+ GPIO3C0_RMII_TX_EN,
+ GPIO3C0_RESERVED,
+};
+
+/* GRF_GPIO3D_IOMUX */
+enum {
+ GPIO3D6_SHIFT = 12,
+ GPIO3D6_MASK = 3,
+ GPIO3D6_GPIO = 0,
+ GPIO3D6_PWM_3,
+ GPIO3D6_JTAG_TMS,
+ GPIO3D6_HOST_DRV_VBUS,
+
+ GPIO3D5_SHIFT = 10,
+ GPIO3D5_MASK = 3,
+ GPIO3D5_GPIO = 0,
+ GPIO3D5_PWM_2,
+ GPIO3D5_JTAG_TCK,
+ GPIO3D5_OTG_DRV_VBUS,
+
+ GPIO3D4_SHIFT = 8,
+ GPIO3D4_MASK = 3,
+ GPIO3D4_GPIO = 0,
+ GPIO3D4_PWM_1,
+ GPIO3D4_JTAG_TRSTN,
+
+ GPIO3D3_SHIFT = 6,
+ GPIO3D3_MASK = 3,
+ GPIO3D3_GPIO = 0,
+ GPIO3D3_PWM_0,
+
+ GPIO3D2_SHIFT = 4,
+ GPIO3D2_MASK = 3,
+ GPIO3D2_GPIO = 0,
+ GPIO3D2_SDMMC1_INT_N,
+
+ GPIO3D1_SHIFT = 2,
+ GPIO3D1_MASK = 3,
+ GPIO3D1_GPIO = 0,
+ GPIO3D1_SDMMC1_BACKEND_PWR,
+ GPIO3D1_MII_MDCLK,
+
+ GPIO3D0_SHIFT = 0,
+ GPIO3D0_MASK = 3,
+ GPIO3D0_GPIO = 0,
+ GPIO3D0_SDMMC1_PWR_EN,
+ GPIO3D0_MII_MD,
+};
+
+/* GRF_SOC_CON0 */
+enum {
+ HSADC_CLK_DIR_SHIFT = 15,
+ HSADC_CLK_DIR_MASK = 1,
+
+ HSADC_SEL_SHIFT = 14,
+ HSADC_SEL_MASK = 1,
+
+ NOC_REMAP_SHIFT = 12,
+ NOC_REMAP_MASK = 1,
+
+ EMMC_FLASH_SEL_SHIFT = 11,
+ EMMC_FLASH_SEL_MASK = 1,
+
+ TZPC_REVISION_SHIFT = 7,
+ TZPC_REVISION_MASK = 0xf,
+
+ L2CACHE_ACC_SHIFT = 5,
+ L2CACHE_ACC_MASK = 3,
+
+ L2RD_WAIT_SHIFT = 3,
+ L2RD_WAIT_MASK = 3,
+
+ IMEMRD_WAIT_SHIFT = 1,
+ IMEMRD_WAIT_MASK = 3,
+};
+
+/* GRF_SOC_CON1 */
+enum {
+ RKI2C4_SEL_SHIFT = 15,
+ RKI2C4_SEL_MASK = 1,
+
+ RKI2C3_SEL_SHIFT = 14,
+ RKI2C3_SEL_MASK = 1,
+
+ RKI2C2_SEL_SHIFT = 13,
+ RKI2C2_SEL_MASK = 1,
+
+ RKI2C1_SEL_SHIFT = 12,
+ RKI2C1_SEL_MASK = 1,
+
+ RKI2C0_SEL_SHIFT = 11,
+ RKI2C0_SEL_MASK = 1,
+
+ VCODEC_SEL_SHIFT = 10,
+ VCODEC_SEL_MASK = 1,
+
+ PERI_EMEM_PAUSE_SHIFT = 9,
+ PERI_EMEM_PAUSE_MASK = 1,
+
+ PERI_USB_PAUSE_SHIFT = 8,
+ PERI_USB_PAUSE_MASK = 1,
+
+ SMC_MUX_MODE_0_SHIFT = 6,
+ SMC_MUX_MODE_0_MASK = 1,
+
+ SMC_SRAM_MW_0_SHIFT = 4,
+ SMC_SRAM_MW_0_MASK = 3,
+
+ SMC_REMAP_0_SHIFT = 3,
+ SMC_REMAP_0_MASK = 1,
+
+ SMC_A_GT_M0_SYNC_SHIFT = 2,
+ SMC_A_GT_M0_SYNC_MASK = 1,
+
+ EMAC_SPEED_SHIFT = 1,
+ EMAC_SPEEC_MASK = 1,
+
+ EMAC_MODE_SHIFT = 0,
+ EMAC_MODE_MASK = 1,
+};
+
+/* GRF_SOC_CON2 */
+enum {
+ SDIO_CLK_OUT_SR_SHIFT = 15,
+ SDIO_CLK_OUT_SR_MASK = 1,
+
+ MEM_EMA_L2C_SHIFT = 11,
+ MEM_EMA_L2C_MASK = 7,
+
+ MEM_EMA_A9_SHIFT = 8,
+ MEM_EMA_A9_MASK = 7,
+
+ MSCH4_MAINDDR3_SHIFT = 7,
+ MSCH4_MAINDDR3_MASK = 1,
+ MSCH4_MAINDDR3_DDR3 = 1,
+
+ EMAC_NEWRCV_EN_SHIFT = 6,
+ EMAC_NEWRCV_EN_MASK = 1,
+
+ SW_ADDR15_EN_SHIFT = 5,
+ SW_ADDR15_EN_MASK = 1,
+
+ SW_ADDR16_EN_SHIFT = 4,
+ SW_ADDR16_EN_MASK = 1,
+
+ SW_ADDR17_EN_SHIFT = 3,
+ SW_ADDR17_EN_MASK = 1,
+
+ BANK2_TO_RANK_EN_SHIFT = 2,
+ BANK2_TO_RANK_EN_MASK = 1,
+
+ RANK_TO_ROW15_EN_SHIFT = 1,
+ RANK_TO_ROW15_EN_MASK = 1,
+
+ UPCTL_C_ACTIVE_IN_SHIFT = 0,
+ UPCTL_C_ACTIVE_IN_MASK = 1,
+ UPCTL_C_ACTIVE_IN_MAY = 0,
+ UPCTL_C_ACTIVE_IN_WILL,
+};
+
+/* GRF_DDRC_CON0 */
+enum {
+ DDR_16BIT_EN_SHIFT = 15,
+ DDR_16BIT_EN_MASK = 1,
+
+ DTO_LB_SHIFT = 11,
+ DTO_LB_MASK = 3,
+
+ DTO_TE_SHIFT = 9,
+ DTO_TE_MASK = 3,
+
+ DTO_PDR_SHIFT = 7,
+ DTO_PDR_MASK = 3,
+
+ DTO_PDD_SHIFT = 5,
+ DTO_PDD_MASK = 3,
+
+ DTO_IOM_SHIFT = 3,
+ DTO_IOM_MASK = 3,
+
+ DTO_OE_SHIFT = 1,
+ DTO_OE_MASK = 3,
+
+ ATO_AE_SHIFT = 0,
+ ATO_AE_MASK = 1,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h
new file mode 100644
index 0000000..d82a678
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_PMU_RK3188_H
+#define _ASM_ARCH_PMU_RK3188_H
+
+struct rk3188_pmu {
+ u32 wakeup_cfg[2];
+ u32 pwrdn_con;
+ u32 pwrdn_st;
+
+ u32 int_con;
+ u32 int_st;
+ u32 misc_con;
+
+ u32 osc_cnt;
+ u32 pll_cnt;
+ u32 pmu_cnt;
+ u32 ddrio_pwron_cnt;
+ u32 wakeup_rst_clr_cnt;
+ u32 scu_pwrdwn_cnt;
+ u32 scu_pwrup_cnt;
+ u32 misc_con1;
+ u32 gpio0_con;
+
+ u32 sys_reg[4];
+ u32 reserved0[4];
+ u32 stop_int_dly;
+ u32 gpio0_p[2];
+};
+check_member(rk3188_pmu, gpio0_p[1], 0x0068);
+
+#endif
--
2.8.0.rc3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 7/9] rockchip: rk3188: Add pinctrl driver
2016-07-15 22:17 [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188 Heiko Stuebner
` (5 preceding siblings ...)
2016-07-15 22:17 ` [U-Boot] [PATCH 6/9] rockchip: rk3188: Add header files for PMU and GRF Heiko Stuebner
@ 2016-07-15 22:17 ` Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 8/9] rockchip: rk3188: Bring in rk3066/rk3188 clock bindings Heiko Stuebner
` (2 subsequent siblings)
9 siblings, 1 reply; 36+ messages in thread
From: Heiko Stuebner @ 2016-07-15 22:17 UTC (permalink / raw)
To: u-boot
Add a driver which supports pin multiplexing setup for the most commonly
used peripherals.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/pinctrl/Kconfig | 9 +
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl_rk3188.c | 614 ++++++++++++++++++++++++++++++
3 files changed, 624 insertions(+)
create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3188.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 2972dba..0d8ee19 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -141,6 +141,15 @@ config ROCKCHIP_RK3288_PINCTRL
definitions and pin control functions for each available multiplex
function.
+config ROCKCHIP_RK3188_PINCTRL
+ bool "Rockchip pin control driver"
+ depends on DM
+ help
+ Support pin multiplexing control on Rockchip rk3188 SoCs. The driver
+ is controlled by a device tree node which contains both the GPIO
+ definitions and pin control functions for each available multiplex
+ function.
+
config PINCTRL_SANDBOX
bool "Sandbox pinctrl driver"
depends on SANDBOX
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index 64e9587..7768628 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -6,4 +6,5 @@
#
obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o
+obj-$(CONFIG_ROCKCHIP_RK3188_PINCTRL) += pinctrl_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3188.c b/drivers/pinctrl/rockchip/pinctrl_rk3188.c
new file mode 100644
index 0000000..25c67ef
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3188.c
@@ -0,0 +1,613 @@
+/*
+ * Pinctrl driver for Rockchip RK3188 SoCs
+ * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3188.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pmu_rk3188.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk3188_pinctrl_priv {
+ struct rk3188_grf *grf;
+ struct rk3188_pmu *pmu;
+ int num_banks;
+};
+
+/**
+ * Encode variants of iomux registers into a type variable
+ */
+#define IOMUX_GPIO_ONLY BIT(0)
+
+/**
+ * @type: iomux variant using IOMUX_* constants
+ * @offset: if initialized to -1 it will be autocalculated, by specifying
+ * an initial offset value the relevant source offset can be reset
+ * to a new value for autocalculating the following iomux registers.
+ */
+struct rockchip_iomux {
+ u8 type;
+ s16 offset;
+};
+
+/**
+ * @reg: register offset of the gpio bank
+ * @nr_pins: number of pins in this bank
+ * @bank_num: number of the bank, to account for holes
+ * @name: name of the bank
+ * @iomux: array describing the 4 iomux sources of the bank
+ */
+struct rockchip_pin_bank {
+ u16 reg;
+ u8 nr_pins;
+ u8 bank_num;
+ char *name;
+ struct rockchip_iomux iomux[4];
+};
+
+#define PIN_BANK(id, pins, label) \
+ { \
+ .bank_num = id, \
+ .nr_pins = pins, \
+ .name = label, \
+ .iomux = { \
+ { .offset = -1 }, \
+ { .offset = -1 }, \
+ { .offset = -1 }, \
+ { .offset = -1 }, \
+ }, \
+ }
+
+#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
+ { \
+ .bank_num = id, \
+ .nr_pins = pins, \
+ .name = label, \
+ .iomux = { \
+ { .type = iom0, .offset = -1 }, \
+ { .type = iom1, .offset = -1 }, \
+ { .type = iom2, .offset = -1 }, \
+ { .type = iom3, .offset = -1 }, \
+ }, \
+ }
+
+#ifndef CONFIG_SPL_BUILD
+static struct rockchip_pin_bank rk3188_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
+ PIN_BANK(1, 32, "gpio1"),
+ PIN_BANK(2, 32, "gpio2"),
+ PIN_BANK(3, 32, "gpio3"),
+};
+#endif
+
+static void pinctrl_rk3188_pwm_config(struct rk3188_grf *grf, int pwm_id)
+{
+ switch (pwm_id) {
+ case PERIPH_ID_PWM0:
+ rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D3_MASK << GPIO3D3_SHIFT,
+ GPIO3D3_PWM_0 << GPIO3D3_SHIFT);
+ break;
+ case PERIPH_ID_PWM1:
+ rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D4_MASK << GPIO3D4_SHIFT,
+ GPIO3D4_PWM_1 << GPIO3D4_SHIFT);
+ break;
+ case PERIPH_ID_PWM2:
+ rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D5_MASK << GPIO3D5_SHIFT,
+ GPIO3D5_PWM_2 << GPIO3D5_SHIFT);
+ break;
+ case PERIPH_ID_PWM3:
+ rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D6_MASK << GPIO3D6_SHIFT,
+ GPIO3D6_PWM_3 << GPIO3D6_SHIFT);
+ break;
+ default:
+ debug("pwm id = %d iomux error!\n", pwm_id);
+ break;
+ }
+}
+
+static void pinctrl_rk3188_i2c_config(struct rk3188_grf *grf,
+ struct rk3188_pmu *pmu, int i2c_id)
+{
+ switch (i2c_id) {
+ case PERIPH_ID_I2C0:
+ rk_clrsetreg(&grf->gpio1d_iomux,
+ GPIO1D1_MASK << GPIO1D1_SHIFT |
+ GPIO1D0_MASK << GPIO1D0_SHIFT,
+ GPIO1D1_I2C0_SCL << GPIO1D1_SHIFT |
+ GPIO1D0_I2C0_SDA << GPIO1D0_SHIFT);
+ /* enable new i2c controller */
+ rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT,
+ 1 << RKI2C0_SEL_SHIFT);
+ break;
+ case PERIPH_ID_I2C1:
+ rk_clrsetreg(&grf->gpio1d_iomux,
+ GPIO1D3_MASK << GPIO1D3_SHIFT |
+ GPIO1D2_MASK << GPIO1D2_SHIFT,
+ GPIO1D3_I2C1_SCL << GPIO1D2_SHIFT |
+ GPIO1D2_I2C1_SDA << GPIO1D2_SHIFT);
+ rk_clrsetreg(&grf->soc_con1, 1 << RKI2C1_SEL_SHIFT,
+ 1 << RKI2C1_SEL_SHIFT);
+ break;
+ case PERIPH_ID_I2C2:
+ rk_clrsetreg(&grf->gpio1d_iomux,
+ GPIO1D5_MASK << GPIO1D5_SHIFT |
+ GPIO1D4_MASK << GPIO1D4_SHIFT,
+ GPIO1D5_I2C2_SCL << GPIO1D5_SHIFT |
+ GPIO1D4_I2C2_SDA << GPIO1D4_SHIFT);
+ rk_clrsetreg(&grf->soc_con1, 1 << RKI2C2_SEL_SHIFT,
+ 1 << RKI2C2_SEL_SHIFT);
+ break;
+ case PERIPH_ID_I2C3:
+ rk_clrsetreg(&grf->gpio3b_iomux,
+ GPIO3B7_MASK << GPIO3B7_SHIFT |
+ GPIO3B6_MASK << GPIO3B6_SHIFT,
+ GPIO3B7_I2C3_SCL << GPIO3B7_SHIFT |
+ GPIO3B6_I2C3_SDA << GPIO3B6_SHIFT);
+ rk_clrsetreg(&grf->soc_con1, 1 << RKI2C3_SEL_SHIFT,
+ 1 << RKI2C3_SEL_SHIFT);
+ break;
+ case PERIPH_ID_I2C4:
+ rk_clrsetreg(&grf->gpio1d_iomux,
+ GPIO1D7_MASK << GPIO1D7_SHIFT |
+ GPIO1D6_MASK << GPIO1D6_SHIFT,
+ GPIO1D7_I2C4_SCL << GPIO1D7_SHIFT |
+ GPIO1D6_I2C4_SDA << GPIO1D6_SHIFT);
+ rk_clrsetreg(&grf->soc_con1, 1 << RKI2C4_SEL_SHIFT,
+ 1 << RKI2C4_SEL_SHIFT);
+ break;
+ default:
+ debug("i2c id = %d iomux error!\n", i2c_id);
+ break;
+ }
+}
+
+static int pinctrl_rk3188_spi_config(struct rk3188_grf *grf,
+ enum periph_id spi_id, int cs)
+{
+ switch (spi_id) {
+ case PERIPH_ID_SPI0:
+ switch (cs) {
+ case 0:
+ rk_clrsetreg(&grf->gpio1a_iomux,
+ GPIO1A7_MASK << GPIO1A7_SHIFT,
+ GPIO1A7_SPI0_CSN0 << GPIO1A7_SHIFT);
+ break;
+ case 1:
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B7_MASK << GPIO1B7_SHIFT,
+ GPIO1B7_SPI0_CSN1 << GPIO1B7_SHIFT);
+ break;
+ default:
+ goto err;
+ }
+ rk_clrsetreg(&grf->gpio1a_iomux,
+ GPIO1A4_MASK << GPIO1A4_SHIFT |
+ GPIO1A5_MASK << GPIO1A5_SHIFT |
+ GPIO1A6_MASK << GPIO1A6_SHIFT,
+ GPIO1A4_SPI0_RXD << GPIO1A4_SHIFT |
+ GPIO1A5_SPI0_TXD << GPIO1A5_SHIFT |
+ GPIO1A6_SPI0_CLK << GPIO1A6_SHIFT);
+ break;
+ case PERIPH_ID_SPI1:
+ switch (cs) {
+ case 0:
+ rk_clrsetreg(&grf->gpio0d_iomux,
+ GPIO0D7_MASK << GPIO0D7_SHIFT,
+ GPIO0D7_SPI1_CSN0 << GPIO0D7_SHIFT);
+ break;
+ case 1:
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B6_MASK << GPIO1B6_SHIFT,
+ GPIO1B6_SPI1_CSN1 << GPIO1B6_SHIFT);
+ break;
+ default:
+ goto err;
+ }
+ rk_clrsetreg(&grf->gpio0d_iomux,
+ GPIO0D4_MASK << GPIO0D4_SHIFT |
+ GPIO0D5_MASK << GPIO0D5_SHIFT |
+ GPIO0D6_MASK << GPIO0D6_SHIFT,
+ GPIO0D4_SPI0_RXD << GPIO0D4_SHIFT |
+ GPIO0D5_SPI1_TXD << GPIO0D5_SHIFT |
+ GPIO0D6_SPI1_CLK << GPIO0D6_SHIFT);
+ break;
+ default:
+ goto err;
+ }
+
+ return 0;
+err:
+ debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
+ return -ENOENT;
+}
+
+static void pinctrl_rk3188_uart_config(struct rk3188_grf *grf, int uart_id)
+{
+ switch (uart_id) {
+ case PERIPH_ID_UART0:
+ rk_clrsetreg(&grf->gpio1a_iomux,
+ GPIO1A3_MASK << GPIO1A3_SHIFT |
+ GPIO1A2_MASK << GPIO1A2_SHIFT |
+ GPIO1A1_MASK << GPIO1A1_SHIFT |
+ GPIO1A0_MASK << GPIO1A0_SHIFT,
+ GPIO1A3_UART0_RTS_N << GPIO1A3_SHIFT |
+ GPIO1A2_UART0_CTS_N << GPIO1A2_SHIFT |
+ GPIO1A1_UART0_SOUT << GPIO1A1_SHIFT |
+ GPIO1A0_UART0_SIN << GPIO1A0_SHIFT);
+ break;
+ case PERIPH_ID_UART1:
+ rk_clrsetreg(&grf->gpio1a_iomux,
+ GPIO1A7_MASK << GPIO1A7_SHIFT |
+ GPIO1A6_MASK << GPIO1A6_SHIFT |
+ GPIO1A5_MASK << GPIO1A5_SHIFT |
+ GPIO1A4_MASK << GPIO1A4_SHIFT,
+ GPIO1A7_UART1_RTS_N << GPIO1A7_SHIFT |
+ GPIO1A6_UART1_CTS_N << GPIO1A6_SHIFT |
+ GPIO1A5_UART1_SOUT << GPIO1A5_SHIFT |
+ GPIO1A4_UART1_SIN << GPIO1A4_SHIFT);
+ break;
+ case PERIPH_ID_UART2:
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B1_MASK << GPIO1B1_SHIFT |
+ GPIO1B0_MASK << GPIO1B0_SHIFT,
+ GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
+ GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
+ break;
+ case PERIPH_ID_UART3:
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B5_MASK << GPIO1B5_SHIFT |
+ GPIO1B4_MASK << GPIO1B4_SHIFT |
+ GPIO1B3_MASK << GPIO1B3_SHIFT |
+ GPIO1B2_MASK << GPIO1B2_SHIFT,
+ GPIO1B5_UART3_RTS_N << GPIO1B5_SHIFT |
+ GPIO1B4_UART3_CTS_N << GPIO1B4_SHIFT |
+ GPIO1B3_UART3_SOUT << GPIO1B3_SHIFT |
+ GPIO1B2_UART3_SIN << GPIO1B2_SHIFT);
+ break;
+ default:
+ debug("uart id = %d iomux error!\n", uart_id);
+ break;
+ }
+}
+
+static void pinctrl_rk3188_sdmmc_config(struct rk3188_grf *grf, int mmc_id)
+{
+ switch (mmc_id) {
+ case PERIPH_ID_EMMC:
+ rk_clrsetreg(&grf->soc_con0, 1 << EMMC_FLASH_SEL_SHIFT,
+ 1 << EMMC_FLASH_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio0d_iomux,
+ GPIO0D2_MASK << GPIO0D2_SHIFT |
+ GPIO0D0_MASK << GPIO0D0_SHIFT,
+ GPIO0D2_EMMC_CMD << GPIO0D2_SHIFT |
+ GPIO0D0_EMMC_CLKOUT << GPIO0D0_SHIFT);
+ break;
+ case PERIPH_ID_SDCARD:
+ rk_clrsetreg(&grf->gpio3b_iomux,
+ GPIO3B0_MASK << GPIO3B0_SHIFT,
+ GPIO3B0_SDMMC_DETECT_N << GPIO3B0_SHIFT);
+ rk_clrsetreg(&grf->gpio3a_iomux,
+ GPIO3A7_MASK << GPIO3A7_SHIFT |
+ GPIO3A6_MASK << GPIO3A6_SHIFT |
+ GPIO3A5_MASK << GPIO3A5_SHIFT |
+ GPIO3A4_MASK << GPIO3A4_SHIFT |
+ GPIO3A3_MASK << GPIO3A3_SHIFT |
+ GPIO3A3_MASK << GPIO3A2_SHIFT,
+ GPIO3A7_SDMMC0_DATA3 << GPIO3A7_SHIFT |
+ GPIO3A6_SDMMC0_DATA2 << GPIO3A6_SHIFT |
+ GPIO3A5_SDMMC0_DATA1 << GPIO3A5_SHIFT |
+ GPIO3A4_SDMMC0_DATA0 << GPIO3A4_SHIFT |
+ GPIO3A3_SDMMC0_CMD << GPIO3A3_SHIFT |
+ GPIO3A2_SDMMC0_CLKOUT << GPIO3A2_SHIFT);
+ break;
+ default:
+ debug("mmc id = %d iomux error!\n", mmc_id);
+ break;
+ }
+}
+
+static int rk3188_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+ struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
+
+ debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+ switch (func) {
+ case PERIPH_ID_PWM0:
+ case PERIPH_ID_PWM1:
+ case PERIPH_ID_PWM2:
+ case PERIPH_ID_PWM3:
+ case PERIPH_ID_PWM4:
+ pinctrl_rk3188_pwm_config(priv->grf, func);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ pinctrl_rk3188_i2c_config(priv->grf, priv->pmu, func);
+ break;
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ case PERIPH_ID_SPI2:
+ pinctrl_rk3188_spi_config(priv->grf, func, flags);
+ break;
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ case PERIPH_ID_UART4:
+ pinctrl_rk3188_uart_config(priv->grf, func);
+ break;
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ pinctrl_rk3188_sdmmc_config(priv->grf, func);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rk3188_pinctrl_get_periph_id(struct udevice *dev,
+ struct udevice *periph)
+{
+ u32 cell[3];
+ int ret;
+
+ ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ "interrupts", cell, ARRAY_SIZE(cell));
+ if (ret < 0)
+ return -EINVAL;
+
+ switch (cell[1]) {
+ case 44:
+ return PERIPH_ID_SPI0;
+ case 45:
+ return PERIPH_ID_SPI1;
+ case 46:
+ return PERIPH_ID_SPI2;
+ case 60:
+ return PERIPH_ID_I2C0;
+ case 62: /* Note strange order */
+ return PERIPH_ID_I2C1;
+ case 61:
+ return PERIPH_ID_I2C2;
+ case 63:
+ return PERIPH_ID_I2C3;
+ case 64:
+ return PERIPH_ID_I2C4;
+ case 65:
+ return PERIPH_ID_I2C5;
+ }
+
+ return -ENOENT;
+}
+
+static int rk3188_pinctrl_set_state_simple(struct udevice *dev,
+ struct udevice *periph)
+{
+ int func;
+
+ func = rk3188_pinctrl_get_periph_id(dev, periph);
+ if (func < 0)
+ return func;
+ return rk3188_pinctrl_request(dev, func, 0);
+}
+
+#ifndef CONFIG_SPL_BUILD
+int rk3188_pinctrl_get_pin_info(struct rk3188_pinctrl_priv *priv,
+ int banknum, int ind, u32 **addrp, uint *shiftp,
+ uint *maskp)
+{
+ struct rockchip_pin_bank *bank = &rk3188_pin_banks[banknum];
+ uint muxnum;
+ u32 *addr;
+
+ for (muxnum = 0; muxnum < 4; muxnum++) {
+ struct rockchip_iomux *mux = &bank->iomux[muxnum];
+
+ if (ind >= 8) {
+ ind -= 8;
+ continue;
+ }
+
+ addr = &priv->grf->gpio0c_iomux - 2;
+ addr += mux->offset;
+ *shiftp = ind & 7;
+ *maskp = 3;
+ *shiftp *= 2;
+
+ debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
+ *maskp, *shiftp);
+ *addrp = addr;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int rk3188_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
+ int index)
+{
+ struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
+ uint shift;
+ uint mask;
+ u32 *addr;
+ int ret;
+
+ ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
+ &mask);
+ if (ret)
+ return ret;
+ return (readl(addr) & mask) >> shift;
+}
+
+static int rk3188_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
+ int muxval, int flags)
+{
+ struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
+ uint shift, ind = index;
+ uint mask;
+ u32 *addr;
+ int ret;
+
+ debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
+ ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
+ &mask);
+ if (ret)
+ return ret;
+ rk_clrsetreg(addr, mask << shift, muxval << shift);
+
+ /* Handle pullup/pulldown */
+ if (flags) {
+ uint val = 0;
+
+ if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
+ val = 1;
+ else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
+ val = 2;
+
+ ind = index >> 3;
+
+ if (banknum == 0 && index < 12) {
+ addr = &priv->pmu->gpio0_p[ind];
+ shift = (index & 7) * 2;
+ } else if (banknum == 0 && index >= 12) {
+ addr = &priv->grf->gpio0_p[ind - 1];
+ /*
+ * The bits in the grf-registers have an inverse
+ * ordering with the lowest pin being in bits 15:14
+ * and the highest pin in bits 1:0 .
+ */
+ shift = (7 - (index & 7)) * 2;
+ } else {
+ addr = &priv->grf->gpio1_p[banknum - 1][ind];
+ shift = (7 - (index & 7)) * 2;
+ }
+ debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
+ shift);
+ rk_clrsetreg(addr, 3 << shift, val << shift);
+ }
+
+ return 0;
+}
+
+static int rk3188_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+ const void *blob = gd->fdt_blob;
+ int pcfg_node, ret, flags, count, i;
+ u32 cell[60], *ptr;
+
+ debug("%s: %s %s\n", __func__, dev->name, config->name);
+ ret = fdtdec_get_int_array_count(blob, config->of_offset,
+ "rockchip,pins", cell,
+ ARRAY_SIZE(cell));
+ if (ret < 0) {
+ debug("%s: bad array %d\n", __func__, ret);
+ return -EINVAL;
+ }
+ count = ret;
+ for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
+ pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
+ if (pcfg_node < 0)
+ return -EINVAL;
+ flags = pinctrl_decode_pin_config(blob, pcfg_node);
+ if (flags < 0)
+ return flags;
+
+ ret = rk3188_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
+ flags);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+static struct pinctrl_ops rk3188_pinctrl_ops = {
+#ifndef CONFIG_SPL_BUILD
+ .set_state = rk3188_pinctrl_set_state,
+ .get_gpio_mux = rk3188_pinctrl_get_gpio_mux,
+#endif
+ .set_state_simple = rk3188_pinctrl_set_state_simple,
+ .request = rk3188_pinctrl_request,
+ .get_periph_id = rk3188_pinctrl_get_periph_id,
+};
+
+static int rk3188_pinctrl_bind(struct udevice *dev)
+{
+ /* scan child GPIO banks */
+ return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+}
+
+#ifndef CONFIG_SPL_BUILD
+static int rk3188_pinctrl_parse_tables(struct rk3188_pinctrl_priv *priv,
+ struct rockchip_pin_bank *banks,
+ int count)
+{
+ struct rockchip_pin_bank *bank;
+ uint reg, muxnum, banknum;
+
+ reg = 0;
+ for (banknum = 0; banknum < count; banknum++) {
+ bank = &banks[banknum];
+ bank->reg = reg;
+ debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
+ for (muxnum = 0; muxnum < 4; muxnum++) {
+ struct rockchip_iomux *mux = &bank->iomux[muxnum];
+
+ mux->offset = reg;
+ reg += 1;
+ }
+ }
+
+ return 0;
+}
+#endif
+
+static int rk3188_pinctrl_probe(struct udevice *dev)
+{
+ struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
+ int ret = 0;
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
+ debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
+#ifndef CONFIG_SPL_BUILD
+ ret = rk3188_pinctrl_parse_tables(priv, rk3188_pin_banks,
+ ARRAY_SIZE(rk3188_pin_banks));
+#endif
+
+ return ret;
+}
+
+static const struct udevice_id rk3188_pinctrl_ids[] = {
+ { .compatible = "rockchip,rk3188-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3188) = {
+ .name = "pinctrl_rk3188",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3188_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3188_pinctrl_priv),
+ .ops = &rk3188_pinctrl_ops,
+ .bind = rk3188_pinctrl_bind,
+ .probe = rk3188_pinctrl_probe,
+};
--
2.8.0.rc3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 8/9] rockchip: rk3188: Bring in rk3066/rk3188 clock bindings
2016-07-15 22:17 [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188 Heiko Stuebner
` (6 preceding siblings ...)
2016-07-15 22:17 ` [U-Boot] [PATCH 7/9] rockchip: rk3188: Add pinctrl driver Heiko Stuebner
@ 2016-07-15 22:17 ` Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 9/9] rockchip: rk3188: Add clock driver Heiko Stuebner
2016-07-17 14:14 ` [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188 Simon Glass
9 siblings, 1 reply; 36+ messages in thread
From: Heiko Stuebner @ 2016-07-15 22:17 UTC (permalink / raw)
To: u-boot
Bring in required device clock binding files from Linux.
The clock trees for rk3066 and rk3188 are largely similar, which makes
them share the common parts in a shared header. While we focus on rk3188
for now, bring in both headers already for completeness sake.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
include/dt-bindings/clock/rk3066a-cru.h | 40 ++++
include/dt-bindings/clock/rk3188-cru-common.h | 256 ++++++++++++++++++++++++++
include/dt-bindings/clock/rk3188-cru.h | 56 ++++++
3 files changed, 352 insertions(+)
create mode 100644 include/dt-bindings/clock/rk3066a-cru.h
create mode 100644 include/dt-bindings/clock/rk3188-cru-common.h
create mode 100644 include/dt-bindings/clock/rk3188-cru.h
diff --git a/include/dt-bindings/clock/rk3066a-cru.h b/include/dt-bindings/clock/rk3066a-cru.h
new file mode 100644
index 0000000..d3a9824
--- /dev/null
+++ b/include/dt-bindings/clock/rk3066a-cru.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H
+
+#include <dt-bindings/clock/rk3188-cru-common.h>
+
+/* soft-reset indices */
+#define SRST_SRST1 0
+#define SRST_SRST2 1
+
+#define SRST_L2MEM 18
+#define SRST_I2S0 23
+#define SRST_I2S1 24
+#define SRST_I2S2 25
+#define SRST_TIMER2 29
+
+#define SRST_GPIO4 36
+#define SRST_GPIO6 38
+
+#define SRST_TSADC 92
+
+#define SRST_HDMI 96
+#define SRST_HDMI_APB 97
+#define SRST_CIF1 111
+
+#endif
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h
new file mode 100644
index 0000000..4f53e70
--- /dev/null
+++ b/include/dt-bindings/clock/rk3188-cru-common.h
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
+
+/* core clocks from */
+#define PLL_APLL 1
+#define PLL_DPLL 2
+#define PLL_CPLL 3
+#define PLL_GPLL 4
+#define CORE_PERI 5
+#define CORE_L2C 6
+#define ARMCLK 7
+
+/* sclk gates (special clocks) */
+#define SCLK_UART0 64
+#define SCLK_UART1 65
+#define SCLK_UART2 66
+#define SCLK_UART3 67
+#define SCLK_MAC 68
+#define SCLK_SPI0 69
+#define SCLK_SPI1 70
+#define SCLK_SARADC 71
+#define SCLK_SDMMC 72
+#define SCLK_SDIO 73
+#define SCLK_EMMC 74
+#define SCLK_I2S0 75
+#define SCLK_I2S1 76
+#define SCLK_I2S2 77
+#define SCLK_SPDIF 78
+#define SCLK_CIF0 79
+#define SCLK_CIF1 80
+#define SCLK_OTGPHY0 81
+#define SCLK_OTGPHY1 82
+#define SCLK_HSADC 83
+#define SCLK_TIMER0 84
+#define SCLK_TIMER1 85
+#define SCLK_TIMER2 86
+#define SCLK_TIMER3 87
+#define SCLK_TIMER4 88
+#define SCLK_TIMER5 89
+#define SCLK_TIMER6 90
+#define SCLK_JTAG 91
+#define SCLK_SMC 92
+#define SCLK_TSADC 93
+
+#define DCLK_LCDC0 190
+#define DCLK_LCDC1 191
+
+/* aclk gates */
+#define ACLK_DMA1 192
+#define ACLK_DMA2 193
+#define ACLK_GPS 194
+#define ACLK_LCDC0 195
+#define ACLK_LCDC1 196
+#define ACLK_GPU 197
+#define ACLK_SMC 198
+#define ACLK_CIF 199
+#define ACLK_IPP 200
+#define ACLK_RGA 201
+#define ACLK_CIF0 202
+
+/* pclk gates */
+#define PCLK_GRF 320
+#define PCLK_PMU 321
+#define PCLK_TIMER0 322
+#define PCLK_TIMER1 323
+#define PCLK_TIMER2 324
+#define PCLK_TIMER3 325
+#define PCLK_PWM01 326
+#define PCLK_PWM23 327
+#define PCLK_SPI0 328
+#define PCLK_SPI1 329
+#define PCLK_SARADC 330
+#define PCLK_WDT 331
+#define PCLK_UART0 332
+#define PCLK_UART1 333
+#define PCLK_UART2 334
+#define PCLK_UART3 335
+#define PCLK_I2C0 336
+#define PCLK_I2C1 337
+#define PCLK_I2C2 338
+#define PCLK_I2C3 339
+#define PCLK_I2C4 340
+#define PCLK_GPIO0 341
+#define PCLK_GPIO1 342
+#define PCLK_GPIO2 343
+#define PCLK_GPIO3 344
+#define PCLK_GPIO4 345
+#define PCLK_GPIO6 346
+#define PCLK_EFUSE 347
+#define PCLK_TZPC 348
+#define PCLK_TSADC 349
+
+/* hclk gates */
+#define HCLK_SDMMC 448
+#define HCLK_SDIO 449
+#define HCLK_EMMC 450
+#define HCLK_OTG0 451
+#define HCLK_EMAC 452
+#define HCLK_SPDIF 453
+#define HCLK_I2S0 454
+#define HCLK_I2S1 455
+#define HCLK_I2S2 456
+#define HCLK_OTG1 457
+#define HCLK_HSIC 458
+#define HCLK_HSADC 459
+#define HCLK_PIDF 460
+#define HCLK_LCDC0 461
+#define HCLK_LCDC1 462
+#define HCLK_ROM 463
+#define HCLK_CIF0 464
+#define HCLK_IPP 465
+#define HCLK_RGA 466
+#define HCLK_NANDC0 467
+
+#define CLK_NR_CLKS (HCLK_NANDC0 + 1)
+
+/* soft-reset indices */
+#define SRST_MCORE 2
+#define SRST_CORE0 3
+#define SRST_CORE1 4
+#define SRST_MCORE_DBG 7
+#define SRST_CORE0_DBG 8
+#define SRST_CORE1_DBG 9
+#define SRST_CORE0_WDT 12
+#define SRST_CORE1_WDT 13
+#define SRST_STRC_SYS 14
+#define SRST_L2C 15
+
+#define SRST_CPU_AHB 17
+#define SRST_AHB2APB 19
+#define SRST_DMA1 20
+#define SRST_INTMEM 21
+#define SRST_ROM 22
+#define SRST_SPDIF 26
+#define SRST_TIMER0 27
+#define SRST_TIMER1 28
+#define SRST_EFUSE 30
+
+#define SRST_GPIO0 32
+#define SRST_GPIO1 33
+#define SRST_GPIO2 34
+#define SRST_GPIO3 35
+
+#define SRST_UART0 39
+#define SRST_UART1 40
+#define SRST_UART2 41
+#define SRST_UART3 42
+#define SRST_I2C0 43
+#define SRST_I2C1 44
+#define SRST_I2C2 45
+#define SRST_I2C3 46
+#define SRST_I2C4 47
+
+#define SRST_PWM0 48
+#define SRST_PWM1 49
+#define SRST_DAP_PO 50
+#define SRST_DAP 51
+#define SRST_DAP_SYS 52
+#define SRST_TPIU_ATB 53
+#define SRST_PMU_APB 54
+#define SRST_GRF 55
+#define SRST_PMU 56
+#define SRST_PERI_AXI 57
+#define SRST_PERI_AHB 58
+#define SRST_PERI_APB 59
+#define SRST_PERI_NIU 60
+#define SRST_CPU_PERI 61
+#define SRST_EMEM_PERI 62
+#define SRST_USB_PERI 63
+
+#define SRST_DMA2 64
+#define SRST_SMC 65
+#define SRST_MAC 66
+#define SRST_NANC0 68
+#define SRST_USBOTG0 69
+#define SRST_USBPHY0 70
+#define SRST_OTGC0 71
+#define SRST_USBOTG1 72
+#define SRST_USBPHY1 73
+#define SRST_OTGC1 74
+#define SRST_HSADC 76
+#define SRST_PIDFILTER 77
+#define SRST_DDR_MSCH 79
+
+#define SRST_TZPC 80
+#define SRST_SDMMC 81
+#define SRST_SDIO 82
+#define SRST_EMMC 83
+#define SRST_SPI0 84
+#define SRST_SPI1 85
+#define SRST_WDT 86
+#define SRST_SARADC 87
+#define SRST_DDRPHY 88
+#define SRST_DDRPHY_APB 89
+#define SRST_DDRCTL 90
+#define SRST_DDRCTL_APB 91
+#define SRST_DDRPUB 93
+
+#define SRST_VIO0_AXI 98
+#define SRST_VIO0_AHB 99
+#define SRST_LCDC0_AXI 100
+#define SRST_LCDC0_AHB 101
+#define SRST_LCDC0_DCLK 102
+#define SRST_LCDC1_AXI 103
+#define SRST_LCDC1_AHB 104
+#define SRST_LCDC1_DCLK 105
+#define SRST_IPP_AXI 106
+#define SRST_IPP_AHB 107
+#define SRST_RGA_AXI 108
+#define SRST_RGA_AHB 109
+#define SRST_CIF0 110
+
+#define SRST_VCODEC_AXI 112
+#define SRST_VCODEC_AHB 113
+#define SRST_VIO1_AXI 114
+#define SRST_VCODEC_CPU 115
+#define SRST_VCODEC_NIU 116
+#define SRST_GPU 120
+#define SRST_GPU_NIU 122
+#define SRST_TFUN_ATB 125
+#define SRST_TFUN_APB 126
+#define SRST_CTI4_APB 127
+
+#define SRST_TPIU_APB 128
+#define SRST_TRACE 129
+#define SRST_CORE_DBG 130
+#define SRST_DBG_APB 131
+#define SRST_CTI0 132
+#define SRST_CTI0_APB 133
+#define SRST_CTI1 134
+#define SRST_CTI1_APB 135
+#define SRST_PTM_CORE0 136
+#define SRST_PTM_CORE1 137
+#define SRST_PTM0 138
+#define SRST_PTM0_ATB 139
+#define SRST_PTM1 140
+#define SRST_PTM1_ATB 141
+#define SRST_CTM 142
+#define SRST_TS 143
+
+#endif
diff --git a/include/dt-bindings/clock/rk3188-cru.h b/include/dt-bindings/clock/rk3188-cru.h
new file mode 100644
index 0000000..9f2e631
--- /dev/null
+++ b/include/dt-bindings/clock/rk3188-cru.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
+
+#include <dt-bindings/clock/rk3188-cru-common.h>
+
+/* soft-reset indices */
+#define SRST_PTM_CORE2 0
+#define SRST_PTM_CORE3 1
+#define SRST_CORE2 5
+#define SRST_CORE3 6
+#define SRST_CORE2_DBG 10
+#define SRST_CORE3_DBG 11
+
+#define SRST_TIMER2 16
+#define SRST_TIMER4 23
+#define SRST_I2S0 24
+#define SRST_TIMER5 25
+#define SRST_TIMER3 29
+#define SRST_TIMER6 31
+
+#define SRST_PTM3 36
+#define SRST_PTM3_ATB 37
+
+#define SRST_GPS 67
+#define SRST_HSICPHY 75
+#define SRST_TIMER 78
+
+#define SRST_PTM2 92
+#define SRST_CORE2_WDT 94
+#define SRST_CORE3_WDT 95
+
+#define SRST_PTM2_ATB 111
+
+#define SRST_HSIC 117
+#define SRST_CTI2 118
+#define SRST_CTI2_APB 119
+#define SRST_GPU_BRIDGE 121
+#define SRST_CTI3 123
+#define SRST_CTI3_APB 124
+
+#endif
--
2.8.0.rc3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 9/9] rockchip: rk3188: Add clock driver
2016-07-15 22:17 [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188 Heiko Stuebner
` (7 preceding siblings ...)
2016-07-15 22:17 ` [U-Boot] [PATCH 8/9] rockchip: rk3188: Bring in rk3066/rk3188 clock bindings Heiko Stuebner
@ 2016-07-15 22:17 ` Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-17 14:14 ` [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188 Simon Glass
9 siblings, 1 reply; 36+ messages in thread
From: Heiko Stuebner @ 2016-07-15 22:17 UTC (permalink / raw)
To: u-boot
Add a driver for setting up and modifying the various PLLs and peripheral
clocks on the RK3188.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 186 ++++++++++
drivers/clk/Makefile | 1 +
drivers/clk/clk_rk3188.c | 464 ++++++++++++++++++++++++
3 files changed, 651 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3188.h
create mode 100644 drivers/clk/clk_rk3188.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h
new file mode 100644
index 0000000..1073613
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_CRU_RK3188_H
+#define _ASM_ARCH_CRU_RK3188_H
+
+#define OSC_HZ (24 * 1000 * 1000)
+
+#define APLL_HZ (1608 * 1000000)
+#define GPLL_HZ (594 * 1000000)
+#define CPLL_HZ (384 * 1000000)
+
+/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
+#define CPU_ACLK_HZ 297000000
+#define CPU_HCLK_HZ 148500000
+#define CPU_PCLK_HZ 74250000
+#define CPU_H2P_HZ 74250000
+
+#define PERI_ACLK_HZ 148500000
+#define PERI_HCLK_HZ 148500000
+#define PERI_PCLK_HZ 74250000
+
+struct rk3188_cru {
+ struct rk3188_pll {
+ u32 con0;
+ u32 con1;
+ u32 con2;
+ u32 con3;
+ } pll[4];
+ u32 cru_mode_con;
+ u32 cru_clksel_con[35];
+ u32 cru_clkgate_con[10];
+ u32 reserved1[2];
+ u32 cru_glb_srst_fst_value;
+ u32 cru_glb_srst_snd_value;
+ u32 reserved2[2];
+ u32 cru_softrst_con[9];
+ u32 cru_misc_con;
+ u32 reserved3[2];
+ u32 cru_glb_cnt_th;
+};
+check_member(rk3188_cru, cru_glb_cnt_th, 0x0140);
+
+/* CRU_CLKSEL0_CON */
+enum {
+ /* a9_core_div: core = core_src / (a9_core_div + 1) */
+ A9_CORE_DIV_SHIFT = 9,
+ A9_CORE_DIV_MASK = 0x1f,
+ CORE_PLL_SHIFT = 8,
+ CORE_PLL_MASK = 1,
+ CORE_PLL_SELECT_APLL = 0,
+ CORE_PLL_SELECT_GPLL,
+
+ /* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */
+ CORE_PERI_DIV_SHIFT = 6,
+ CORE_PERI_DIV_MASK = 3,
+
+ /* aclk_cpu pll selection */
+ CPU_ACLK_PLL_SHIFT = 5,
+ CPU_ACLK_PLL_MASK = 1,
+ CPU_ACLK_PLL_SELECT_APLL = 0,
+ CPU_ACLK_PLL_SELECT_GPLL,
+
+ /* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */
+ A9_CPU_DIV_SHIFT = 0,
+ A9_CPU_DIV_MASK = 0x1f,
+};
+
+/* CRU_CLKSEL1_CON */
+enum {
+ /* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */
+ AHB2APB_DIV_SHIFT = 14,
+ AHB2APB_DIV_MASK = 3,
+
+ /* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */
+ CPU_PCLK_DIV_SHIFT = 12,
+ CPU_PCLK_DIV_MASK = 3,
+
+ /* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */
+ CPU_HCLK_DIV_SHIFT = 8,
+ CPU_HCLK_DIV_MASK = 3,
+
+ /* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */
+ CORE_ACLK_DIV_SHIFT = 3,
+ CORE_ACLK_DIV_MASK = 7,
+};
+
+/* CRU_CLKSEL10_CON */
+enum {
+ PERI_SEL_PLL_MASK = 1,
+ PERI_SEL_PLL_SHIFT = 15,
+ PERI_SEL_CPLL = 0,
+ PERI_SEL_GPLL,
+
+ /* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */
+ PERI_PCLK_DIV_SHIFT = 12,
+ PERI_PCLK_DIV_MASK = 3,
+
+ /* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */
+ PERI_HCLK_DIV_SHIFT = 8,
+ PERI_HCLK_DIV_MASK = 3,
+
+ /* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */
+ PERI_ACLK_DIV_SHIFT = 0,
+ PERI_ACLK_DIV_MASK = 0x1f,
+};
+/* CRU_CLKSEL11_CON */
+enum {
+ HSICPHY_DIV_SHIFT = 8,
+ HSICPHY_DIV_MASK = 0x3f,
+
+ MMC0_DIV_SHIFT = 0,
+ MMC0_DIV_MASK = 0x3f,
+};
+
+/* CRU_CLKSEL12_CON */
+enum {
+ UART_PLL_SHIFT = 15,
+ UART_PLL_MASK = 1,
+ UART_PLL_SELECT_GENERAL = 0,
+ UART_PLL_SELECT_CODEC,
+
+ EMMC_DIV_SHIFT = 8,
+ EMMC_DIV_MASK = 0x3f,
+
+ SDIO_DIV_SHIFT = 0,
+ SDIO_DIV_MASK = 0x3f,
+};
+
+/* CRU_CLKSEL25_CON */
+enum {
+ SPI1_DIV_SHIFT = 8,
+ SPI1_DIV_MASK = 0x7f,
+
+ SPI0_DIV_SHIFT = 0,
+ SPI0_DIV_MASK = 0x7f,
+};
+
+/* CRU_MODE_CON */
+enum {
+ GPLL_MODE_SHIFT = 12,
+ GPLL_MODE_MASK = 3,
+ GPLL_MODE_SLOW = 0,
+ GPLL_MODE_NORMAL,
+ GPLL_MODE_DEEP,
+
+ CPLL_MODE_SHIFT = 8,
+ CPLL_MODE_MASK = 3,
+ CPLL_MODE_SLOW = 0,
+ CPLL_MODE_NORMAL,
+ CPLL_MODE_DEEP,
+
+ DPLL_MODE_SHIFT = 4,
+ DPLL_MODE_MASK = 3,
+ DPLL_MODE_SLOW = 0,
+ DPLL_MODE_NORMAL,
+ DPLL_MODE_DEEP,
+
+ APLL_MODE_SHIFT = 0,
+ APLL_MODE_MASK = 3,
+ APLL_MODE_SLOW = 0,
+ APLL_MODE_NORMAL,
+ APLL_MODE_DEEP,
+};
+
+/* CRU_APLL_CON0 */
+enum {
+ CLKR_SHIFT = 8,
+ CLKR_MASK = 0x3f,
+
+ CLKOD_SHIFT = 0,
+ CLKOD_MASK = 0x3f,
+};
+
+/* CRU_APLL_CON1 */
+enum {
+ CLKF_SHIFT = 0,
+ CLKF_MASK = 0x1fff,
+};
+
+#endif
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f7a8891..9455729 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_CLK) += clk-uclass.o clk_fixed_rate.o
obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
+obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
diff --git a/drivers/clk/clk_rk3188.c b/drivers/clk/clk_rk3188.c
new file mode 100644
index 0000000..4c28393
--- /dev/null
+++ b/drivers/clk/clk_rk3188.c
@@ -0,0 +1,465 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3188.h>
+#include <asm/arch/grf_rk3188.h>
+#include <asm/arch/hardware.h>
+#include <dt-bindings/clock/rk3188-cru.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk3188_clk_priv {
+ struct rk3188_grf *grf;
+ struct rk3188_cru *cru;
+ ulong rate;
+ bool has_bwadj;
+};
+
+struct pll_div {
+ u32 nr;
+ u32 nf;
+ u32 no;
+};
+
+enum {
+ VCO_MAX_HZ = 2200U * 1000000,
+ VCO_MIN_HZ = 440 * 1000000,
+ OUTPUT_MAX_HZ = 2200U * 1000000,
+ OUTPUT_MIN_HZ = 30 * 1000000,
+ FREF_MAX_HZ = 2200U * 1000000,
+ FREF_MIN_HZ = 30 * 1000,
+};
+
+enum {
+ /* PLL CON0 */
+ PLL_OD_MASK = 0x0f,
+
+ /* PLL CON1 */
+ PLL_NF_MASK = 0x1fff,
+
+ /* PLL CON2 */
+ PLL_BWADJ_MASK = 0x0fff,
+
+ /* PLL CON3 */
+ PLL_RESET_SHIFT = 5,
+
+ /* GRF_SOC_STATUS0 */
+ SOCSTS_DPLL_LOCK = 1 << 5,
+ SOCSTS_APLL_LOCK = 1 << 6,
+ SOCSTS_CPLL_LOCK = 1 << 7,
+ SOCSTS_GPLL_LOCK = 1 << 8,
+};
+
+#define RATE_TO_DIV(input_rate, output_rate) \
+ ((input_rate) / (output_rate) - 1);
+
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+#define PLL_DIVISORS(hz, _nr, _no) {\
+ .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
+ _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
+ (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
+ "divisors on line " __stringify(__LINE__));
+
+/* Keep divisors as low as possible to reduce jitter and power usage */
+static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
+static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
+static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
+
+void *rockchip_get_cru(void)
+{
+ struct rk3188_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@20000000", &dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
+
+static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id,
+ const struct pll_div *div, bool has_bwadj)
+{
+ int pll_id = rk_pll_id(clk_id);
+ struct rk3188_pll *pll = &cru->pll[pll_id];
+ /* All PLLs have same VCO and output frequency range restrictions. */
+ uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
+ uint output_hz = vco_hz / div->no;
+
+ debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
+ (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
+ assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
+ output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
+ (div->no == 1 || !(div->no % 2)));
+
+ /* enter reset */
+ rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
+
+ rk_clrsetreg(&pll->con0,
+ CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
+ ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
+ rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
+
+ if (has_bwadj)
+ rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
+
+ udelay(10);
+
+ /* return from reset */
+ rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
+
+ return 0;
+}
+
+static inline unsigned int log2(unsigned int value)
+{
+ return fls(value) - 1;
+}
+
+static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
+ bool has_bwadj)
+{
+ u32 aclk_div, hclk_div, pclk_div, h2p_div;
+
+ /* pll enter slow-mode */
+ rk_clrsetreg(&cru->cru_mode_con,
+ GPLL_MODE_MASK << GPLL_MODE_SHIFT |
+ CPLL_MODE_MASK << CPLL_MODE_SHIFT,
+ GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
+ CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
+
+ /* init pll */
+ rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
+ rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj);
+
+ /* waiting for pll lock */
+ while ((readl(&grf->soc_status0) &
+ (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
+ (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
+ udelay(1);
+
+ /*
+ * cpu clock pll source selection and
+ * reparent aclk_cpu_pre from apll to gpll
+ * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+ */
+ aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ);
+ assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+
+ rk_clrsetreg(&cru->cru_clksel_con[0],
+ CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT |
+ A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT,
+ CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT |
+ aclk_div << A9_CPU_DIV_SHIFT);
+
+ hclk_div = log2(CPU_ACLK_HZ / CPU_HCLK_HZ);
+ assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3);
+ pclk_div = log2(CPU_ACLK_HZ / CPU_PCLK_HZ);
+ assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4);
+ h2p_div = log2(CPU_HCLK_HZ / CPU_H2P_HZ);
+ assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3);
+
+ rk_clrsetreg(&cru->cru_clksel_con[1],
+ AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT |
+ CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT |
+ CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT,
+ h2p_div << AHB2APB_DIV_SHIFT |
+ pclk_div << CPU_PCLK_DIV_SHIFT |
+ hclk_div << CPU_HCLK_DIV_SHIFT);
+
+ /*
+ * peri clock pll source selection and
+ * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+ */
+ aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
+ assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+
+ hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
+ assert((1 << hclk_div) * PERI_HCLK_HZ ==
+ PERI_ACLK_HZ && (hclk_div < 0x4));
+
+ pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
+ assert((1 << pclk_div) * PERI_PCLK_HZ ==
+ PERI_ACLK_HZ && (pclk_div < 0x4));
+
+ rk_clrsetreg(&cru->cru_clksel_con[10],
+ PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
+ PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
+ PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
+ PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
+ pclk_div << PERI_PCLK_DIV_SHIFT |
+ hclk_div << PERI_HCLK_DIV_SHIFT |
+ aclk_div << PERI_ACLK_DIV_SHIFT);
+
+ /* PLL enter normal-mode */
+ rk_clrsetreg(&cru->cru_mode_con,
+ GPLL_MODE_MASK << GPLL_MODE_SHIFT |
+ CPLL_MODE_MASK << CPLL_MODE_SHIFT,
+ GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
+ CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
+}
+
+/* Get pll rate by id */
+static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru,
+ enum rk_clk_id clk_id)
+{
+ uint32_t nr, no, nf;
+ uint32_t con;
+ int pll_id = rk_pll_id(clk_id);
+ struct rk3188_pll *pll = &cru->pll[pll_id];
+ static u8 clk_shift[CLK_COUNT] = {
+ 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
+ GPLL_MODE_SHIFT
+ };
+ uint shift;
+
+ con = readl(&cru->cru_mode_con);
+ shift = clk_shift[clk_id];
+ switch ((con >> shift) & APLL_MODE_MASK) {
+ case APLL_MODE_SLOW:
+ return OSC_HZ;
+ case APLL_MODE_NORMAL:
+ /* normal mode */
+ con = readl(&pll->con0);
+ no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
+ nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
+ con = readl(&pll->con1);
+ nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
+
+ return (24 * nf / (nr * no)) * 1000000;
+ case APLL_MODE_DEEP:
+ default:
+ return 32768;
+ }
+}
+
+static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
+ int periph)
+{
+ uint div;
+ u32 con;
+
+ switch (periph) {
+ case HCLK_EMMC:
+ con = readl(&cru->cru_clksel_con[12]);
+ div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
+ break;
+ case HCLK_SDMMC:
+ con = readl(&cru->cru_clksel_con[11]);
+ div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
+ break;
+ case HCLK_SDIO:
+ con = readl(&cru->cru_clksel_con[12]);
+ div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return DIV_TO_RATE(gclk_rate, div);
+}
+
+static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
+ int periph, uint freq)
+{
+ int src_clk_div;
+
+ debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
+ src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+ assert(src_clk_div <= 0x3f);
+
+ switch (periph) {
+ case HCLK_EMMC:
+ rk_clrsetreg(&cru->cru_clksel_con[12],
+ EMMC_DIV_MASK << EMMC_DIV_SHIFT,
+ src_clk_div << EMMC_DIV_SHIFT);
+ break;
+ case HCLK_SDMMC:
+ rk_clrsetreg(&cru->cru_clksel_con[11],
+ MMC0_DIV_MASK << MMC0_DIV_SHIFT,
+ src_clk_div << MMC0_DIV_SHIFT);
+ break;
+ case HCLK_SDIO:
+ rk_clrsetreg(&cru->cru_clksel_con[12],
+ SDIO_DIV_MASK << SDIO_DIV_SHIFT,
+ src_clk_div << SDIO_DIV_SHIFT);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return rockchip_mmc_get_clk(cru, gclk_rate, periph);
+}
+
+static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
+ int periph)
+{
+ uint div;
+ u32 con;
+
+ switch (periph) {
+ case SCLK_SPI0:
+ con = readl(&cru->cru_clksel_con[25]);
+ div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
+ break;
+ case SCLK_SPI1:
+ con = readl(&cru->cru_clksel_con[25]);
+ div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return DIV_TO_RATE(gclk_rate, div);
+}
+
+static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
+ int periph, uint freq)
+{
+ int src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+
+ switch (periph) {
+ case SCLK_SPI0:
+ assert(src_clk_div <= SPI0_DIV_MASK);
+ rk_clrsetreg(&cru->cru_clksel_con[25],
+ SPI0_DIV_MASK << SPI0_DIV_SHIFT,
+ src_clk_div << SPI0_DIV_SHIFT);
+ break;
+ case SCLK_SPI1:
+ assert(src_clk_div <= SPI1_DIV_MASK);
+ rk_clrsetreg(&cru->cru_clksel_con[25],
+ SPI1_DIV_MASK << SPI1_DIV_SHIFT,
+ src_clk_div << SPI1_DIV_SHIFT);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return rockchip_spi_get_clk(cru, gclk_rate, periph);
+}
+
+static ulong rk3188_clk_get_rate(struct clk *clk)
+{
+ struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong new_rate, gclk_rate;
+
+ gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
+ switch (clk->id) {
+ case 1 ... 4:
+ new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
+ break;
+ case HCLK_EMMC:
+ case HCLK_SDMMC:
+ case HCLK_SDIO:
+ new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
+ clk->id);
+ break;
+ case SCLK_SPI0:
+ case SCLK_SPI1:
+ new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ,
+ clk->id);
+ break;
+ case PCLK_I2C0:
+ case PCLK_I2C1:
+ case PCLK_I2C2:
+ case PCLK_I2C3:
+ case PCLK_I2C4:
+ return gclk_rate;
+ default:
+ return -ENOENT;
+ }
+
+ return new_rate;
+}
+
+static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3188_cru *cru = priv->cru;
+ ulong new_rate;
+
+ switch (clk->id) {
+ case HCLK_EMMC:
+ case HCLK_SDMMC:
+ case HCLK_SDIO:
+ new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
+ clk->id, rate);
+ break;
+ case SCLK_SPI0:
+ case SCLK_SPI1:
+ new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ,
+ clk->id, rate);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return new_rate;
+}
+
+static struct clk_ops rk3188_clk_ops = {
+ .get_rate = rk3188_clk_get_rate,
+ .set_rate = rk3188_clk_set_rate,
+};
+
+static int rk3188_clk_probe(struct udevice *dev)
+{
+ struct rk3188_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = (struct rk3188_cru *)dev_get_addr(dev);
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ priv->has_bwadj = of_device_is_compatible(dev, "rockchip,rk3188a-cru")
+ ? 1 : 0;
+
+ /* we don't have a spl yet, so call rkclk_init at the regular time */
+ rkclk_init(priv->cru, priv->grf, priv->has_bwadj);
+
+ return 0;
+}
+
+static int rk3188_clk_bind(struct udevice *dev)
+{
+ int ret;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(gd->dm_root, "rk3188_sysreset", "reset", &dev);
+ if (ret)
+ debug("Warning: No rk3188 reset driver: ret=%d\n", ret);
+
+ return 0;
+}
+
+static const struct udevice_id rk3188_clk_ids[] = {
+ { .compatible = "rockchip,rk3188-cru" },
+ { .compatible = "rockchip,rk3188a-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(clk_rk3188) = {
+ .name = "clk_rk3188",
+ .id = UCLASS_CLK,
+ .of_match = rk3188_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3188_clk_priv),
+ .ops = &rk3188_clk_ops,
+ .bind = rk3188_clk_bind,
+ .probe = rk3188_clk_probe,
+};
--
2.8.0.rc3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 3/9] cosmetic: rockchip: sort socs according to numbers
2016-07-15 22:17 ` [U-Boot] [PATCH 3/9] cosmetic: rockchip: sort socs according to numbers Heiko Stuebner
@ 2016-07-16 15:47 ` Andreas Färber
2016-07-17 14:13 ` Simon Glass
1 sibling, 0 replies; 36+ messages in thread
From: Andreas Färber @ 2016-07-16 15:47 UTC (permalink / raw)
To: u-boot
Am 16.07.2016 um 00:17 schrieb Heiko Stuebner:
> Having some sort of ordering proofed helpful in a lot of other places
"proved"
> already. So for a larger number of rockchip socs it might be helpful
> as well instead of an ever increasing unsorted list.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/arm/mach-rockchip/Kconfig | 20 ++++++++++----------
> arch/arm/mach-rockchip/Makefile | 4 ++--
> drivers/pinctrl/Kconfig | 16 ++++++++--------
> drivers/pinctrl/rockchip/Makefile | 2 +-
> 4 files changed, 21 insertions(+), 21 deletions(-)
Makes perfect sense to me,
Reviewed-by: Andreas F?rber <afaerber@suse.de>
Thanks,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Felix Imend?rffer, Jane Smithard, Graham Norton
HRB 21284 (AG N?rnberg)
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 1/9] cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming
2016-07-15 22:17 ` [U-Boot] [PATCH 1/9] cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming Heiko Stuebner
@ 2016-07-17 14:13 ` Simon Glass
2016-07-18 12:16 ` Simon Glass
0 siblings, 1 reply; 36+ messages in thread
From: Simon Glass @ 2016-07-17 14:13 UTC (permalink / raw)
To: u-boot
On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
> The rk3288 pinctrl is very specific to this soc, so should
> not hog the generic rockchip naming.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> configs/chromebook_jerry_defconfig | 2 +-
> configs/firefly-rk3288_defconfig | 2 +-
> configs/rock2_defconfig | 2 +-
> configs/sandbox_defconfig | 2 +-
> configs/sandbox_noblk_defconfig | 2 +-
> drivers/pinctrl/Kconfig | 6 +++---
> drivers/pinctrl/rockchip/Makefile | 2 +-
> 7 files changed, 9 insertions(+), 9 deletions(-)
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 2/9] cosmetic: rockchip: rk3036: pinctrl: fix config symbol naming
2016-07-15 22:17 ` [U-Boot] [PATCH 2/9] cosmetic: rockchip: rk3036: " Heiko Stuebner
@ 2016-07-17 14:13 ` Simon Glass
2016-07-18 12:16 ` Simon Glass
0 siblings, 1 reply; 36+ messages in thread
From: Simon Glass @ 2016-07-17 14:13 UTC (permalink / raw)
To: u-boot
On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
> Rockchip socs are always named rkxxxx in all places, as also shown
> by the naming of the rk3036 pinctrl file itself.
> Therefore also name the config symbol according to this scheme.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> configs/evb-rk3036_defconfig | 2 +-
> configs/kylin-rk3036_defconfig | 2 +-
> configs/sandbox_defconfig | 2 +-
> configs/sandbox_noblk_defconfig | 2 +-
> drivers/pinctrl/Kconfig | 2 +-
> drivers/pinctrl/rockchip/Makefile | 2 +-
> 6 files changed, 6 insertions(+), 6 deletions(-)
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 3/9] cosmetic: rockchip: sort socs according to numbers
2016-07-15 22:17 ` [U-Boot] [PATCH 3/9] cosmetic: rockchip: sort socs according to numbers Heiko Stuebner
2016-07-16 15:47 ` Andreas Färber
@ 2016-07-17 14:13 ` Simon Glass
2016-07-18 12:16 ` Simon Glass
1 sibling, 1 reply; 36+ messages in thread
From: Simon Glass @ 2016-07-17 14:13 UTC (permalink / raw)
To: u-boot
On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
> Having some sort of ordering proofed helpful in a lot of other places
> already. So for a larger number of rockchip socs it might be helpful
> as well instead of an ever increasing unsorted list.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/arm/mach-rockchip/Kconfig | 20 ++++++++++----------
> arch/arm/mach-rockchip/Makefile | 4 ++--
> drivers/pinctrl/Kconfig | 16 ++++++++--------
> drivers/pinctrl/rockchip/Makefile | 2 +-
> 4 files changed, 21 insertions(+), 21 deletions(-)
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 4/9] cosmetic: rockchip: rk3288: rename rkclk_configure_cpu
2016-07-15 22:17 ` [U-Boot] [PATCH 4/9] cosmetic: rockchip: rk3288: rename rkclk_configure_cpu Heiko Stuebner
@ 2016-07-17 14:13 ` Simon Glass
2016-07-18 12:16 ` Simon Glass
0 siblings, 1 reply; 36+ messages in thread
From: Simon Glass @ 2016-07-17 14:13 UTC (permalink / raw)
To: u-boot
On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
> The function is very specific to the rk3288 in its arguments
> referencing the rk3288 cru and grf and every other rockchip soc
> has differing cru and grf registers. So make that function naming
> explicit.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/arm/include/asm/arch-rockchip/clock.h | 2 +-
> arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 2 +-
> drivers/clk/clk_rk3288.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 5/9] rockchip: rk3288: fix FREF_MIN_HZ constant
2016-07-15 22:17 ` [U-Boot] [PATCH 5/9] rockchip: rk3288: fix FREF_MIN_HZ constant Heiko Stuebner
@ 2016-07-17 14:13 ` Simon Glass
2016-07-18 12:16 ` Simon Glass
0 siblings, 1 reply; 36+ messages in thread
From: Simon Glass @ 2016-07-17 14:13 UTC (permalink / raw)
To: u-boot
On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
> According to the TRM the minimum FREF frequency is 269kHz not MHz.
> Adapt the constant accordingly.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> drivers/clk/clk_rk3288.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 6/9] rockchip: rk3188: Add header files for PMU and GRF
2016-07-15 22:17 ` [U-Boot] [PATCH 6/9] rockchip: rk3188: Add header files for PMU and GRF Heiko Stuebner
@ 2016-07-17 14:13 ` Simon Glass
0 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2016-07-17 14:13 UTC (permalink / raw)
To: u-boot
Hi Heiko,
On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
> PMU is the power management unit and GRF is the general register file. Both
> are heavily used in U-Boot. Add header files with register definitions.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/arm/include/asm/arch-rockchip/grf_rk3188.h | 589 ++++++++++++++++++++++++
> arch/arm/include/asm/arch-rockchip/pmu_rk3188.h | 36 ++
> 2 files changed, 625 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3188.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3188.h
Acked-by: Simon Glass <sjg@chromium.org>
It's unfortunate that I got the mask value wrong. It should be:
SW_ADDR16_EN_SHIFT = 4,
SW_ADDR16_EN_MASK = 1 << SW_ADDR16_EN_SHIFT,
since that makes the C code simpler in the common case. It also makes
it an actual mask.
- Simon
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 7/9] rockchip: rk3188: Add pinctrl driver
2016-07-15 22:17 ` [U-Boot] [PATCH 7/9] rockchip: rk3188: Add pinctrl driver Heiko Stuebner
@ 2016-07-17 14:13 ` Simon Glass
2016-07-17 15:47 ` Heiko Stübner
0 siblings, 1 reply; 36+ messages in thread
From: Simon Glass @ 2016-07-17 14:13 UTC (permalink / raw)
To: u-boot
Hi Heiko,
On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
> Add a driver which supports pin multiplexing setup for the most commonly
> used peripherals.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> drivers/pinctrl/Kconfig | 9 +
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl_rk3188.c | 614 ++++++++++++++++++++++++++++++
> 3 files changed, 624 insertions(+)
> create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3188.c
Acked-by: Simon Glass <sjg@chromium.org>
But is it possible to use some common code with the rk3288 driver?
Things like rk3288_pinctrl_set_pins()?
- Simon
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 8/9] rockchip: rk3188: Bring in rk3066/rk3188 clock bindings
2016-07-15 22:17 ` [U-Boot] [PATCH 8/9] rockchip: rk3188: Bring in rk3066/rk3188 clock bindings Heiko Stuebner
@ 2016-07-17 14:13 ` Simon Glass
0 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2016-07-17 14:13 UTC (permalink / raw)
To: u-boot
Hi Heiko,
On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
> Bring in required device clock binding files from Linux.
> The clock trees for rk3066 and rk3188 are largely similar, which makes
> them share the common parts in a shared header. While we focus on rk3188
> for now, bring in both headers already for completeness sake.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> include/dt-bindings/clock/rk3066a-cru.h | 40 ++++
> include/dt-bindings/clock/rk3188-cru-common.h | 256 ++++++++++++++++++++++++++
> include/dt-bindings/clock/rk3188-cru.h | 56 ++++++
> 3 files changed, 352 insertions(+)
> create mode 100644 include/dt-bindings/clock/rk3066a-cru.h
> create mode 100644 include/dt-bindings/clock/rk3188-cru-common.h
> create mode 100644 include/dt-bindings/clock/rk3188-cru.h
>
> diff --git a/include/dt-bindings/clock/rk3066a-cru.h b/include/dt-bindings/clock/rk3066a-cru.h
> new file mode 100644
> index 0000000..d3a9824
> --- /dev/null
> +++ b/include/dt-bindings/clock/rk3066a-cru.h
> @@ -0,0 +1,40 @@
> +/*
> + * Copyright (c) 2014 MundoReader S.L.
> + * Author: Heiko Stuebner <heiko@sntech.de>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
Can you please use SPDX?
Regards,
Simon
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 9/9] rockchip: rk3188: Add clock driver
2016-07-15 22:17 ` [U-Boot] [PATCH 9/9] rockchip: rk3188: Add clock driver Heiko Stuebner
@ 2016-07-17 14:13 ` Simon Glass
2016-07-17 15:33 ` Heiko Stübner
0 siblings, 1 reply; 36+ messages in thread
From: Simon Glass @ 2016-07-17 14:13 UTC (permalink / raw)
To: u-boot
Hi Heiko,
On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
> Add a driver for setting up and modifying the various PLLs and peripheral
> clocks on the RK3188.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 186 ++++++++++
> drivers/clk/Makefile | 1 +
> drivers/clk/clk_rk3188.c | 464 ++++++++++++++++++++++++
> 3 files changed, 651 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3188.h
> create mode 100644 drivers/clk/clk_rk3188.c
Could you add a patch to move these files into a drivers/clk/rockchip directory?
> new file mode 100644
> index 0000000..4c28393
> --- /dev/null
> +++ b/drivers/clk/clk_rk3188.c
> @@ -0,0 +1,465 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3188.h>
> +#include <asm/arch/grf_rk3188.h>
> +#include <asm/arch/hardware.h>
> +#include <dt-bindings/clock/rk3188-cru.h>
> +#include <dm/device-internal.h>
> +#include <dm/lists.h>
> +#include <dm/uclass-internal.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct rk3188_clk_priv {
> + struct rk3188_grf *grf;
> + struct rk3188_cru *cru;
> + ulong rate;
> + bool has_bwadj;
> +};
> +
> +struct pll_div {
> + u32 nr;
> + u32 nf;
> + u32 no;
> +};
> +
> +enum {
> + VCO_MAX_HZ = 2200U * 1000000,
> + VCO_MIN_HZ = 440 * 1000000,
> + OUTPUT_MAX_HZ = 2200U * 1000000,
> + OUTPUT_MIN_HZ = 30 * 1000000,
> + FREF_MAX_HZ = 2200U * 1000000,
> + FREF_MIN_HZ = 30 * 1000,
> +};
> +
> +enum {
> + /* PLL CON0 */
> + PLL_OD_MASK = 0x0f,
> +
> + /* PLL CON1 */
> + PLL_NF_MASK = 0x1fff,
> +
> + /* PLL CON2 */
> + PLL_BWADJ_MASK = 0x0fff,
> +
> + /* PLL CON3 */
> + PLL_RESET_SHIFT = 5,
> +
> + /* GRF_SOC_STATUS0 */
> + SOCSTS_DPLL_LOCK = 1 << 5,
> + SOCSTS_APLL_LOCK = 1 << 6,
> + SOCSTS_CPLL_LOCK = 1 << 7,
> + SOCSTS_GPLL_LOCK = 1 << 8,
> +};
> +
> +#define RATE_TO_DIV(input_rate, output_rate) \
> + ((input_rate) / (output_rate) - 1);
> +
> +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
> +
> +#define PLL_DIVISORS(hz, _nr, _no) {\
> + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
> + _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
> + (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
> + "divisors on line " __stringify(__LINE__));
> +
> +/* Keep divisors as low as possible to reduce jitter and power usage */
> +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
> +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
> +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
> +
> +void *rockchip_get_cru(void)
> +{
> + struct rk3188_clk_priv *priv;
> + struct udevice *dev;
> + int ret;
> +
> + ret = uclass_get_device_by_name(UCLASS_CLK,
> + "clock-controller at 20000000", &dev);
This seems odd. Could you use uclass_get_device(UCLASS_CLK, 0, .&dev) ?
> + if (ret)
> + return ERR_PTR(ret);
> +
> + priv = dev_get_priv(dev);
> +
> + return priv->cru;
> +}
> +
> +static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id,
> + const struct pll_div *div, bool has_bwadj)
> +{
> + int pll_id = rk_pll_id(clk_id);
> + struct rk3188_pll *pll = &cru->pll[pll_id];
> + /* All PLLs have same VCO and output frequency range restrictions. */
> + uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
> + uint output_hz = vco_hz / div->no;
> +
> + debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
> + (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
> + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
> + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
> + (div->no == 1 || !(div->no % 2)));
> +
> + /* enter reset */
> + rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
> +
> + rk_clrsetreg(&pll->con0,
> + CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
> + ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
> + rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
> +
> + if (has_bwadj)
> + rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
> +
> + udelay(10);
> +
> + /* return from reset */
> + rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
> +
> + return 0;
> +}
> +
> +static inline unsigned int log2(unsigned int value)
Hmm this should go in a common file. Perhaps bitfield.h or common.h?
> +{
> + return fls(value) - 1;
> +}
> +
> +static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
> + bool has_bwadj)
> +{
> + u32 aclk_div, hclk_div, pclk_div, h2p_div;
> +
> + /* pll enter slow-mode */
> + rk_clrsetreg(&cru->cru_mode_con,
> + GPLL_MODE_MASK << GPLL_MODE_SHIFT |
> + CPLL_MODE_MASK << CPLL_MODE_SHIFT,
> + GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
> + CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
> +
> + /* init pll */
> + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
> + rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj);
> +
> + /* waiting for pll lock */
> + while ((readl(&grf->soc_status0) &
> + (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
> + (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
> + udelay(1);
> +
> + /*
> + * cpu clock pll source selection and
> + * reparent aclk_cpu_pre from apll to gpll
> + * set up dependent divisors for PCLK/HCLK and ACLK clocks.
> + */
> + aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ);
> + assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
> +
> + rk_clrsetreg(&cru->cru_clksel_con[0],
> + CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT |
> + A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT,
> + CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT |
> + aclk_div << A9_CPU_DIV_SHIFT);
> +
> + hclk_div = log2(CPU_ACLK_HZ / CPU_HCLK_HZ);
> + assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3);
> + pclk_div = log2(CPU_ACLK_HZ / CPU_PCLK_HZ);
> + assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4);
> + h2p_div = log2(CPU_HCLK_HZ / CPU_H2P_HZ);
> + assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3);
> +
> + rk_clrsetreg(&cru->cru_clksel_con[1],
> + AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT |
> + CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT |
> + CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT,
> + h2p_div << AHB2APB_DIV_SHIFT |
> + pclk_div << CPU_PCLK_DIV_SHIFT |
> + hclk_div << CPU_HCLK_DIV_SHIFT);
> +
> + /*
> + * peri clock pll source selection and
> + * set up dependent divisors for PCLK/HCLK and ACLK clocks.
> + */
> + aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
> + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
> +
> + hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
> + assert((1 << hclk_div) * PERI_HCLK_HZ ==
> + PERI_ACLK_HZ && (hclk_div < 0x4));
> +
> + pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
> + assert((1 << pclk_div) * PERI_PCLK_HZ ==
> + PERI_ACLK_HZ && (pclk_div < 0x4));
> +
> + rk_clrsetreg(&cru->cru_clksel_con[10],
> + PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
> + PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
> + PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
> + PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
> + pclk_div << PERI_PCLK_DIV_SHIFT |
> + hclk_div << PERI_HCLK_DIV_SHIFT |
> + aclk_div << PERI_ACLK_DIV_SHIFT);
> +
> + /* PLL enter normal-mode */
> + rk_clrsetreg(&cru->cru_mode_con,
> + GPLL_MODE_MASK << GPLL_MODE_SHIFT |
> + CPLL_MODE_MASK << CPLL_MODE_SHIFT,
> + GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
> + CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
> +}
> +
> +/* Get pll rate by id */
> +static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru,
> + enum rk_clk_id clk_id)
> +{
> + uint32_t nr, no, nf;
> + uint32_t con;
> + int pll_id = rk_pll_id(clk_id);
> + struct rk3188_pll *pll = &cru->pll[pll_id];
> + static u8 clk_shift[CLK_COUNT] = {
> + 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
> + GPLL_MODE_SHIFT
> + };
> + uint shift;
> +
> + con = readl(&cru->cru_mode_con);
> + shift = clk_shift[clk_id];
> + switch ((con >> shift) & APLL_MODE_MASK) {
> + case APLL_MODE_SLOW:
> + return OSC_HZ;
> + case APLL_MODE_NORMAL:
> + /* normal mode */
> + con = readl(&pll->con0);
> + no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
> + nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
> + con = readl(&pll->con1);
> + nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
> +
> + return (24 * nf / (nr * no)) * 1000000;
> + case APLL_MODE_DEEP:
> + default:
> + return 32768;
> + }
> +}
> +
> +static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
> + int periph)
> +{
> + uint div;
> + u32 con;
> +
> + switch (periph) {
> + case HCLK_EMMC:
> + con = readl(&cru->cru_clksel_con[12]);
> + div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
> + break;
> + case HCLK_SDMMC:
> + con = readl(&cru->cru_clksel_con[11]);
> + div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
> + break;
> + case HCLK_SDIO:
> + con = readl(&cru->cru_clksel_con[12]);
> + div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return DIV_TO_RATE(gclk_rate, div);
> +}
> +
> +static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
> + int periph, uint freq)
> +{
> + int src_clk_div;
> +
> + debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
> + src_clk_div = RATE_TO_DIV(gclk_rate, freq);
> + assert(src_clk_div <= 0x3f);
> +
> + switch (periph) {
> + case HCLK_EMMC:
> + rk_clrsetreg(&cru->cru_clksel_con[12],
> + EMMC_DIV_MASK << EMMC_DIV_SHIFT,
> + src_clk_div << EMMC_DIV_SHIFT);
> + break;
> + case HCLK_SDMMC:
> + rk_clrsetreg(&cru->cru_clksel_con[11],
> + MMC0_DIV_MASK << MMC0_DIV_SHIFT,
> + src_clk_div << MMC0_DIV_SHIFT);
> + break;
> + case HCLK_SDIO:
> + rk_clrsetreg(&cru->cru_clksel_con[12],
> + SDIO_DIV_MASK << SDIO_DIV_SHIFT,
> + src_clk_div << SDIO_DIV_SHIFT);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return rockchip_mmc_get_clk(cru, gclk_rate, periph);
> +}
> +
> +static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
> + int periph)
> +{
> + uint div;
> + u32 con;
> +
> + switch (periph) {
> + case SCLK_SPI0:
> + con = readl(&cru->cru_clksel_con[25]);
> + div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
> + break;
> + case SCLK_SPI1:
> + con = readl(&cru->cru_clksel_con[25]);
> + div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return DIV_TO_RATE(gclk_rate, div);
> +}
> +
> +static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
> + int periph, uint freq)
> +{
> + int src_clk_div = RATE_TO_DIV(gclk_rate, freq);
> +
> + switch (periph) {
> + case SCLK_SPI0:
> + assert(src_clk_div <= SPI0_DIV_MASK);
> + rk_clrsetreg(&cru->cru_clksel_con[25],
> + SPI0_DIV_MASK << SPI0_DIV_SHIFT,
> + src_clk_div << SPI0_DIV_SHIFT);
> + break;
> + case SCLK_SPI1:
> + assert(src_clk_div <= SPI1_DIV_MASK);
> + rk_clrsetreg(&cru->cru_clksel_con[25],
> + SPI1_DIV_MASK << SPI1_DIV_SHIFT,
> + src_clk_div << SPI1_DIV_SHIFT);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return rockchip_spi_get_clk(cru, gclk_rate, periph);
> +}
> +
> +static ulong rk3188_clk_get_rate(struct clk *clk)
> +{
> + struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
> + ulong new_rate, gclk_rate;
> +
> + gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
> + switch (clk->id) {
> + case 1 ... 4:
> + new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
> + break;
> + case HCLK_EMMC:
> + case HCLK_SDMMC:
> + case HCLK_SDIO:
> + new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
> + clk->id);
> + break;
> + case SCLK_SPI0:
> + case SCLK_SPI1:
> + new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ,
> + clk->id);
> + break;
> + case PCLK_I2C0:
> + case PCLK_I2C1:
> + case PCLK_I2C2:
> + case PCLK_I2C3:
> + case PCLK_I2C4:
> + return gclk_rate;
> + default:
> + return -ENOENT;
> + }
> +
> + return new_rate;
> +}
> +
> +static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
> +{
> + struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
> + struct rk3188_cru *cru = priv->cru;
> + ulong new_rate;
> +
> + switch (clk->id) {
> + case HCLK_EMMC:
> + case HCLK_SDMMC:
> + case HCLK_SDIO:
> + new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
> + clk->id, rate);
> + break;
> + case SCLK_SPI0:
> + case SCLK_SPI1:
> + new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ,
> + clk->id, rate);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return new_rate;
> +}
> +
> +static struct clk_ops rk3188_clk_ops = {
> + .get_rate = rk3188_clk_get_rate,
> + .set_rate = rk3188_clk_set_rate,
> +};
> +
> +static int rk3188_clk_probe(struct udevice *dev)
> +{
> + struct rk3188_clk_priv *priv = dev_get_priv(dev);
> +
> + priv->cru = (struct rk3188_cru *)dev_get_addr(dev);
> + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> + priv->has_bwadj = of_device_is_compatible(dev, "rockchip,rk3188a-cru")
> + ? 1 : 0;
You should add a .data member to your udevice_id array below using a
two-member enum, and check dev_get_driver_data() here.
> +
> + /* we don't have a spl yet, so call rkclk_init at the regular time */
> + rkclk_init(priv->cru, priv->grf, priv->has_bwadj);
> +
> + return 0;
> +}
> +
> +static int rk3188_clk_bind(struct udevice *dev)
> +{
> + int ret;
> +
> + /* The reset driver does not have a device node, so bind it here */
> + ret = device_bind_driver(gd->dm_root, "rk3188_sysreset", "reset", &dev);
> + if (ret)
> + debug("Warning: No rk3188 reset driver: ret=%d\n", ret);
> +
> + return 0;
> +}
> +
> +static const struct udevice_id rk3188_clk_ids[] = {
> + { .compatible = "rockchip,rk3188-cru" },
> + { .compatible = "rockchip,rk3188a-cru" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(clk_rk3188) = {
> + .name = "clk_rk3188",
> + .id = UCLASS_CLK,
> + .of_match = rk3188_clk_ids,
> + .priv_auto_alloc_size = sizeof(struct rk3188_clk_priv),
> + .ops = &rk3188_clk_ops,
> + .bind = rk3188_clk_bind,
> + .probe = rk3188_clk_probe,
> +};
> --
> 2.8.0.rc3
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188
2016-07-15 22:17 [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188 Heiko Stuebner
` (8 preceding siblings ...)
2016-07-15 22:17 ` [U-Boot] [PATCH 9/9] rockchip: rk3188: Add clock driver Heiko Stuebner
@ 2016-07-17 14:14 ` Simon Glass
2016-07-17 15:20 ` Heiko Stübner
9 siblings, 1 reply; 36+ messages in thread
From: Simon Glass @ 2016-07-17 14:14 UTC (permalink / raw)
To: u-boot
Hi Heiko,
On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
> I've made some nice progress on using mainline uboot on the rk3188
> and would like to dump some first results.
>
> Right now I can use uboot on the rk3188 with the Rockchip binary ddr init,
> similar to what barebox does and can even netboot a kernel image using
> a usb ethernet adapter [0] .
>
> While working on this I found quite some cosmetic stuff that shouldn't
> persist to make extending easier. So while I don't know what the policy
> is for my standalone pinctrl and clock drivers (without the actual board)
> at least the cosmetics + fix might get in at least.
Nice work!
It would be best to add the drivers with the board - otherwise they
are just dead code. How far away is it?
Regards,
Simon
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188
2016-07-17 14:14 ` [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188 Simon Glass
@ 2016-07-17 15:20 ` Heiko Stübner
2016-07-17 15:27 ` Simon Glass
0 siblings, 1 reply; 36+ messages in thread
From: Heiko Stübner @ 2016-07-17 15:20 UTC (permalink / raw)
To: u-boot
Am Sonntag, 17. Juli 2016, 08:14:06 schrieb Simon Glass:
> Hi Heiko,
>
> On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
> > I've made some nice progress on using mainline uboot on the rk3188
> > and would like to dump some first results.
> >
> > Right now I can use uboot on the rk3188 with the Rockchip binary ddr init,
> > similar to what barebox does and can even netboot a kernel image using
> > a usb ethernet adapter [0] .
> >
> > While working on this I found quite some cosmetic stuff that shouldn't
> > persist to make extending easier. So while I don't know what the policy
> > is for my standalone pinctrl and clock drivers (without the actual board)
> > at least the cosmetics + fix might get in at least.
>
> Nice work!
>
> It would be best to add the drivers with the board - otherwise they
> are just dead code. How far away is it?
The big issue is the SPL. Right now I'm using Rockchip's ddr-init as spl-
replacement, and I'd say this second part is nearly ready - only minor
cleanups.
The memory-setup is supposed to be very much similar to the rk3288 (same
dw_upctl and ddr-phy), but it looks like the very first steps are somewhat
different and I haven't been able to make the spl output anything on the
serial console yet ... which could stem from some difference in what the soc
expects or just some dumb mistake on my part :-)
Heiko
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188
2016-07-17 15:20 ` Heiko Stübner
@ 2016-07-17 15:27 ` Simon Glass
2016-07-18 12:16 ` Simon Glass
0 siblings, 1 reply; 36+ messages in thread
From: Simon Glass @ 2016-07-17 15:27 UTC (permalink / raw)
To: u-boot
Hi Heiko,
On 17 July 2016 at 09:20, Heiko St?bner <heiko@sntech.de> wrote:
> Am Sonntag, 17. Juli 2016, 08:14:06 schrieb Simon Glass:
>> Hi Heiko,
>>
>> On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
>> > I've made some nice progress on using mainline uboot on the rk3188
>> > and would like to dump some first results.
>> >
>> > Right now I can use uboot on the rk3188 with the Rockchip binary ddr init,
>> > similar to what barebox does and can even netboot a kernel image using
>> > a usb ethernet adapter [0] .
>> >
>> > While working on this I found quite some cosmetic stuff that shouldn't
>> > persist to make extending easier. So while I don't know what the policy
>> > is for my standalone pinctrl and clock drivers (without the actual board)
>> > at least the cosmetics + fix might get in at least.
>>
>> Nice work!
>>
>> It would be best to add the drivers with the board - otherwise they
>> are just dead code. How far away is it?
>
> The big issue is the SPL. Right now I'm using Rockchip's ddr-init as spl-
> replacement, and I'd say this second part is nearly ready - only minor
> cleanups.
>
> The memory-setup is supposed to be very much similar to the rk3288 (same
> dw_upctl and ddr-phy), but it looks like the very first steps are somewhat
> different and I haven't been able to make the spl output anything on the
> serial console yet ... which could stem from some difference in what the soc
> expects or just some dumb mistake on my part :-)
That's always tricky.
You may already know this, but the EARLY_UART setting is used on
rk3288 to display a character as soon as SPL starts. You might be able
to do something similar. The main issue I had was getting the pinmux
setting right.
As a test, you can start with booting SPL from the ddr-init binary I
suspect. I have not tried it but it should work. Then the pinmux
should already be set up (since ddr-init outputs to serial).
Regards,
Simon
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 9/9] rockchip: rk3188: Add clock driver
2016-07-17 14:13 ` Simon Glass
@ 2016-07-17 15:33 ` Heiko Stübner
2016-07-17 15:48 ` Simon Glass
0 siblings, 1 reply; 36+ messages in thread
From: Heiko Stübner @ 2016-07-17 15:33 UTC (permalink / raw)
To: u-boot
Am Sonntag, 17. Juli 2016, 08:13:58 schrieb Simon Glass:
> Hi Heiko,
>
> On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
> > Add a driver for setting up and modifying the various PLLs and peripheral
> > clocks on the RK3188.
> >
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > ---
> >
> > arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 186 ++++++++++
> > drivers/clk/Makefile | 1 +
> > drivers/clk/clk_rk3188.c | 464
> > ++++++++++++++++++++++++ 3 files changed, 651 insertions(+)
> > create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3188.h
> > create mode 100644 drivers/clk/clk_rk3188.c
>
> Could you add a patch to move these files into a drivers/clk/rockchip
> directory?
ok
> > new file mode 100644
> > index 0000000..4c28393
> > --- /dev/null
> > +++ b/drivers/clk/clk_rk3188.c
> > @@ -0,0 +1,465 @@
> > +/*
> > + * (C) Copyright 2015 Google, Inc
> > + * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
> > + *
> > + * SPDX-License-Identifier: GPL-2.0
> > + */
> > +
> > +#include <common.h>
> > +#include <clk-uclass.h>
> > +#include <dm.h>
> > +#include <errno.h>
> > +#include <syscon.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/clock.h>
> > +#include <asm/arch/cru_rk3188.h>
> > +#include <asm/arch/grf_rk3188.h>
> > +#include <asm/arch/hardware.h>
> > +#include <dt-bindings/clock/rk3188-cru.h>
> > +#include <dm/device-internal.h>
> > +#include <dm/lists.h>
> > +#include <dm/uclass-internal.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +struct rk3188_clk_priv {
> > + struct rk3188_grf *grf;
> > + struct rk3188_cru *cru;
> > + ulong rate;
> > + bool has_bwadj;
> > +};
> > +
> > +struct pll_div {
> > + u32 nr;
> > + u32 nf;
> > + u32 no;
> > +};
> > +
> > +enum {
> > + VCO_MAX_HZ = 2200U * 1000000,
> > + VCO_MIN_HZ = 440 * 1000000,
> > + OUTPUT_MAX_HZ = 2200U * 1000000,
> > + OUTPUT_MIN_HZ = 30 * 1000000,
> > + FREF_MAX_HZ = 2200U * 1000000,
> > + FREF_MIN_HZ = 30 * 1000,
> > +};
> > +
> > +enum {
> > + /* PLL CON0 */
> > + PLL_OD_MASK = 0x0f,
> > +
> > + /* PLL CON1 */
> > + PLL_NF_MASK = 0x1fff,
> > +
> > + /* PLL CON2 */
> > + PLL_BWADJ_MASK = 0x0fff,
> > +
> > + /* PLL CON3 */
> > + PLL_RESET_SHIFT = 5,
> > +
> > + /* GRF_SOC_STATUS0 */
> > + SOCSTS_DPLL_LOCK = 1 << 5,
> > + SOCSTS_APLL_LOCK = 1 << 6,
> > + SOCSTS_CPLL_LOCK = 1 << 7,
> > + SOCSTS_GPLL_LOCK = 1 << 8,
> > +};
> > +
> > +#define RATE_TO_DIV(input_rate, output_rate) \
> > + ((input_rate) / (output_rate) - 1);
> > +
> > +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
> > +
> > +#define PLL_DIVISORS(hz, _nr, _no) {\
> > + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
> > + _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
> > + (_nr * _no) == hz, #hz "Hz cannot be hit with PLL
> > "\
> > + "divisors on line " __stringify(__LINE__));
> > +
> > +/* Keep divisors as low as possible to reduce jitter and power usage */
> > +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
> > +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
> > +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
> > +
> > +void *rockchip_get_cru(void)
> > +{
> > + struct rk3188_clk_priv *priv;
> > + struct udevice *dev;
> > + int ret;
> > +
> > + ret = uclass_get_device_by_name(UCLASS_CLK,
> > + "clock-controller at 20000000",
> > &dev);
>
> This seems odd. Could you use uclass_get_device(UCLASS_CLK, 0, .&dev) ?
Index 0 actually gets me the 24MHz oscillator fixed clock :-), which is why I
switched to the by-name variant to not depend on some dts or uclass ordering.
I'm wondering how that works on the other socs.
>
> > + if (ret)
> > + return ERR_PTR(ret);
> > +
> > + priv = dev_get_priv(dev);
> > +
> > + return priv->cru;
> > +}
> > +
> > +static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id,
> > + const struct pll_div *div, bool has_bwadj)
> > +{
> > + int pll_id = rk_pll_id(clk_id);
> > + struct rk3188_pll *pll = &cru->pll[pll_id];
> > + /* All PLLs have same VCO and output frequency range restrictions.
> > */ + uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
> > + uint output_hz = vco_hz / div->no;
> > +
> > + debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
> > + (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
> > + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
> > + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
> > + (div->no == 1 || !(div->no % 2)));
> > +
> > + /* enter reset */
> > + rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
> > +
> > + rk_clrsetreg(&pll->con0,
> > + CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
> > + ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
> > + rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
> > +
> > + if (has_bwadj)
> > + rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) -
> > 1); +
> > + udelay(10);
> > +
> > + /* return from reset */
> > + rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
> > +
> > + return 0;
> > +}
> > +
> > +static inline unsigned int log2(unsigned int value)
>
> Hmm this should go in a common file. Perhaps bitfield.h or common.h?
it looks like uboot is already carrying ilog2() in include/linux/log2.h ?
[...]
> > +static int rk3188_clk_probe(struct udevice *dev)
> > +{
> > + struct rk3188_clk_priv *priv = dev_get_priv(dev);
> > +
> > + priv->cru = (struct rk3188_cru *)dev_get_addr(dev);
> > + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> > + priv->has_bwadj = of_device_is_compatible(dev,
> > "rockchip,rk3188a-cru") + ? 1 : 0;
>
> You should add a .data member to your udevice_id array below using a
> two-member enum, and check dev_get_driver_data() here.
ah, nice to know. I was wondering if and how uboot was handling .data stuff
but my short skimming through the sources didn't reveal that. Will change.
Heiko
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 7/9] rockchip: rk3188: Add pinctrl driver
2016-07-17 14:13 ` Simon Glass
@ 2016-07-17 15:47 ` Heiko Stübner
2016-07-17 15:49 ` Simon Glass
0 siblings, 1 reply; 36+ messages in thread
From: Heiko Stübner @ 2016-07-17 15:47 UTC (permalink / raw)
To: u-boot
Hi Simon,
Am Sonntag, 17. Juli 2016, 08:13:51 schrieb Simon Glass:
> On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
> > Add a driver which supports pin multiplexing setup for the most commonly
> > used peripherals.
> >
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > ---
> >
> > drivers/pinctrl/Kconfig | 9 +
> > drivers/pinctrl/rockchip/Makefile | 1 +
> > drivers/pinctrl/rockchip/pinctrl_rk3188.c | 614
> > ++++++++++++++++++++++++++++++ 3 files changed, 624 insertions(+)
> > create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3188.c
>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> But is it possible to use some common code with the rk3288 driver?
> Things like rk3288_pinctrl_set_pins()?
I don't really think that will fly.
The iomux area always sees a lot of creativity when the GRF gets designed.
For example on the rk3288 you have gpio0 iomux + pull + etc in the pmu and all
other banks in the grf. On the rk3188 the iomux is contained completely in the
grf but the pull setting of the first _12_ pins are living in the pmu - and
even their ordering is inverted - see the whole if(flags) part in the rk3188
pinctrl driver.
The rk3399 introduces even more funny things. So I don't see where we would
save without adding all the indirection the linux driver currently has.
Heiko
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 9/9] rockchip: rk3188: Add clock driver
2016-07-17 15:33 ` Heiko Stübner
@ 2016-07-17 15:48 ` Simon Glass
2016-07-18 13:31 ` Simon Glass
0 siblings, 1 reply; 36+ messages in thread
From: Simon Glass @ 2016-07-17 15:48 UTC (permalink / raw)
To: u-boot
Hi Heiko,
On 17 July 2016 at 09:33, Heiko St?bner <heiko@sntech.de> wrote:
> Am Sonntag, 17. Juli 2016, 08:13:58 schrieb Simon Glass:
>> Hi Heiko,
>>
>> On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
>> > Add a driver for setting up and modifying the various PLLs and peripheral
>> > clocks on the RK3188.
>> >
>> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>> > ---
>> >
>> > arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 186 ++++++++++
>> > drivers/clk/Makefile | 1 +
>> > drivers/clk/clk_rk3188.c | 464
>> > ++++++++++++++++++++++++ 3 files changed, 651 insertions(+)
>> > create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3188.h
>> > create mode 100644 drivers/clk/clk_rk3188.c
>>
>> Could you add a patch to move these files into a drivers/clk/rockchip
>> directory?
>
> ok
>
>> > new file mode 100644
>> > index 0000000..4c28393
>> > --- /dev/null
>> > +++ b/drivers/clk/clk_rk3188.c
>> > @@ -0,0 +1,465 @@
>> > +/*
>> > + * (C) Copyright 2015 Google, Inc
>> > + * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
>> > + *
>> > + * SPDX-License-Identifier: GPL-2.0
>> > + */
>> > +
>> > +#include <common.h>
>> > +#include <clk-uclass.h>
>> > +#include <dm.h>
>> > +#include <errno.h>
>> > +#include <syscon.h>
>> > +#include <asm/io.h>
>> > +#include <asm/arch/clock.h>
>> > +#include <asm/arch/cru_rk3188.h>
>> > +#include <asm/arch/grf_rk3188.h>
>> > +#include <asm/arch/hardware.h>
>> > +#include <dt-bindings/clock/rk3188-cru.h>
>> > +#include <dm/device-internal.h>
>> > +#include <dm/lists.h>
>> > +#include <dm/uclass-internal.h>
>> > +
>> > +DECLARE_GLOBAL_DATA_PTR;
>> > +
>> > +struct rk3188_clk_priv {
>> > + struct rk3188_grf *grf;
>> > + struct rk3188_cru *cru;
>> > + ulong rate;
>> > + bool has_bwadj;
>> > +};
>> > +
>> > +struct pll_div {
>> > + u32 nr;
>> > + u32 nf;
>> > + u32 no;
>> > +};
>> > +
>> > +enum {
>> > + VCO_MAX_HZ = 2200U * 1000000,
>> > + VCO_MIN_HZ = 440 * 1000000,
>> > + OUTPUT_MAX_HZ = 2200U * 1000000,
>> > + OUTPUT_MIN_HZ = 30 * 1000000,
>> > + FREF_MAX_HZ = 2200U * 1000000,
>> > + FREF_MIN_HZ = 30 * 1000,
>> > +};
>> > +
>> > +enum {
>> > + /* PLL CON0 */
>> > + PLL_OD_MASK = 0x0f,
>> > +
>> > + /* PLL CON1 */
>> > + PLL_NF_MASK = 0x1fff,
>> > +
>> > + /* PLL CON2 */
>> > + PLL_BWADJ_MASK = 0x0fff,
>> > +
>> > + /* PLL CON3 */
>> > + PLL_RESET_SHIFT = 5,
>> > +
>> > + /* GRF_SOC_STATUS0 */
>> > + SOCSTS_DPLL_LOCK = 1 << 5,
>> > + SOCSTS_APLL_LOCK = 1 << 6,
>> > + SOCSTS_CPLL_LOCK = 1 << 7,
>> > + SOCSTS_GPLL_LOCK = 1 << 8,
>> > +};
>> > +
>> > +#define RATE_TO_DIV(input_rate, output_rate) \
>> > + ((input_rate) / (output_rate) - 1);
>> > +
>> > +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
>> > +
>> > +#define PLL_DIVISORS(hz, _nr, _no) {\
>> > + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
>> > + _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
>> > + (_nr * _no) == hz, #hz "Hz cannot be hit with PLL
>> > "\
>> > + "divisors on line " __stringify(__LINE__));
>> > +
>> > +/* Keep divisors as low as possible to reduce jitter and power usage */
>> > +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
>> > +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
>> > +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
>> > +
>> > +void *rockchip_get_cru(void)
>> > +{
>> > + struct rk3188_clk_priv *priv;
>> > + struct udevice *dev;
>> > + int ret;
>> > +
>> > + ret = uclass_get_device_by_name(UCLASS_CLK,
>> > + "clock-controller at 20000000",
>> > &dev);
>>
>> This seems odd. Could you use uclass_get_device(UCLASS_CLK, 0, .&dev) ?
>
> Index 0 actually gets me the 24MHz oscillator fixed clock :-), which is why I
> switched to the by-name variant to not depend on some dts or uclass ordering.
> I'm wondering how that works on the other socs.
I suspect this might have become broken by Stephen's clock changes. I
had a bit of a look at this but have not resolved it yet. For example
on firefly, HDMI does not work now.
There is this:
enum rk_clk_id {
CLK_OSC,
CLK_ARM,
CLK_DDR,
CLK_CODEC,
CLK_GENERAL,
CLK_NEW,
CLK_COUNT,
};
and it used to check against the platform data (see rkclk_get_clk() in
v2016.05). I'll have a think about it.
>
>>
>> > + if (ret)
>> > + return ERR_PTR(ret);
>> > +
>> > + priv = dev_get_priv(dev);
>> > +
>> > + return priv->cru;
>> > +}
>> > +
>> > +static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id,
>> > + const struct pll_div *div, bool has_bwadj)
>> > +{
>> > + int pll_id = rk_pll_id(clk_id);
>> > + struct rk3188_pll *pll = &cru->pll[pll_id];
>> > + /* All PLLs have same VCO and output frequency range restrictions.
>> > */ + uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
>> > + uint output_hz = vco_hz / div->no;
>> > +
>> > + debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
>> > + (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
>> > + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
>> > + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
>> > + (div->no == 1 || !(div->no % 2)));
>> > +
>> > + /* enter reset */
>> > + rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
>> > +
>> > + rk_clrsetreg(&pll->con0,
>> > + CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
>> > + ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
>> > + rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
>> > +
>> > + if (has_bwadj)
>> > + rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) -
>> > 1); +
>> > + udelay(10);
>> > +
>> > + /* return from reset */
>> > + rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
>> > +
>> > + return 0;
>> > +}
>> > +
>> > +static inline unsigned int log2(unsigned int value)
>>
>> Hmm this should go in a common file. Perhaps bitfield.h or common.h?
>
> it looks like uboot is already carrying ilog2() in include/linux/log2.h ?
Yes.
>
> [...]
>
>> > +static int rk3188_clk_probe(struct udevice *dev)
>> > +{
>> > + struct rk3188_clk_priv *priv = dev_get_priv(dev);
>> > +
>> > + priv->cru = (struct rk3188_cru *)dev_get_addr(dev);
>> > + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
>> > + priv->has_bwadj = of_device_is_compatible(dev,
>> > "rockchip,rk3188a-cru") + ? 1 : 0;
>>
>> You should add a .data member to your udevice_id array below using a
>> two-member enum, and check dev_get_driver_data() here.
>
> ah, nice to know. I was wondering if and how uboot was handling .data stuff
> but my short skimming through the sources didn't reveal that. Will change.
I'm AFK for a few hours now.
Regards,
Simon
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 7/9] rockchip: rk3188: Add pinctrl driver
2016-07-17 15:47 ` Heiko Stübner
@ 2016-07-17 15:49 ` Simon Glass
0 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2016-07-17 15:49 UTC (permalink / raw)
To: u-boot
Hi Heiko,
On 17 July 2016 at 09:47, Heiko St?bner <heiko@sntech.de> wrote:
> Hi Simon,
>
> Am Sonntag, 17. Juli 2016, 08:13:51 schrieb Simon Glass:
>> On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
>> > Add a driver which supports pin multiplexing setup for the most commonly
>> > used peripherals.
>> >
>> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>> > ---
>> >
>> > drivers/pinctrl/Kconfig | 9 +
>> > drivers/pinctrl/rockchip/Makefile | 1 +
>> > drivers/pinctrl/rockchip/pinctrl_rk3188.c | 614
>> > ++++++++++++++++++++++++++++++ 3 files changed, 624 insertions(+)
>> > create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3188.c
>>
>> Acked-by: Simon Glass <sjg@chromium.org>
>>
>> But is it possible to use some common code with the rk3288 driver?
>> Things like rk3288_pinctrl_set_pins()?
>
> I don't really think that will fly.
>
> The iomux area always sees a lot of creativity when the GRF gets designed.
>
> For example on the rk3288 you have gpio0 iomux + pull + etc in the pmu and all
> other banks in the grf. On the rk3188 the iomux is contained completely in the
> grf but the pull setting of the first _12_ pins are living in the pmu - and
> even their ordering is inverted - see the whole if(flags) part in the rk3188
> pinctrl driver.
>
> The rk3399 introduces even more funny things. So I don't see where we would
> save without adding all the indirection the linux driver currently has.
That's fine, thanks for the info.
Regards,
Simon
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 1/9] cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming
2016-07-17 14:13 ` Simon Glass
@ 2016-07-18 12:16 ` Simon Glass
0 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2016-07-18 12:16 UTC (permalink / raw)
To: u-boot
On 17 July 2016 at 08:13, Simon Glass <sjg@chromium.org> wrote:
> On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
>> The rk3288 pinctrl is very specific to this soc, so should
>> not hog the generic rockchip naming.
>>
>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>> ---
>> configs/chromebook_jerry_defconfig | 2 +-
>> configs/firefly-rk3288_defconfig | 2 +-
>> configs/rock2_defconfig | 2 +-
>> configs/sandbox_defconfig | 2 +-
>> configs/sandbox_noblk_defconfig | 2 +-
>> drivers/pinctrl/Kconfig | 6 +++---
>> drivers/pinctrl/rockchip/Makefile | 2 +-
>> 7 files changed, 9 insertions(+), 9 deletions(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 2/9] cosmetic: rockchip: rk3036: pinctrl: fix config symbol naming
2016-07-17 14:13 ` Simon Glass
@ 2016-07-18 12:16 ` Simon Glass
0 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2016-07-18 12:16 UTC (permalink / raw)
To: u-boot
On 17 July 2016 at 08:13, Simon Glass <sjg@chromium.org> wrote:
> On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
>> Rockchip socs are always named rkxxxx in all places, as also shown
>> by the naming of the rk3036 pinctrl file itself.
>> Therefore also name the config symbol according to this scheme.
>>
>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>> ---
>> configs/evb-rk3036_defconfig | 2 +-
>> configs/kylin-rk3036_defconfig | 2 +-
>> configs/sandbox_defconfig | 2 +-
>> configs/sandbox_noblk_defconfig | 2 +-
>> drivers/pinctrl/Kconfig | 2 +-
>> drivers/pinctrl/rockchip/Makefile | 2 +-
>> 6 files changed, 6 insertions(+), 6 deletions(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 3/9] cosmetic: rockchip: sort socs according to numbers
2016-07-17 14:13 ` Simon Glass
@ 2016-07-18 12:16 ` Simon Glass
0 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2016-07-18 12:16 UTC (permalink / raw)
To: u-boot
On 17 July 2016 at 08:13, Simon Glass <sjg@chromium.org> wrote:
> On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
>> Having some sort of ordering proofed helpful in a lot of other places
>> already. So for a larger number of rockchip socs it might be helpful
>> as well instead of an ever increasing unsorted list.
>>
>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>> ---
>> arch/arm/mach-rockchip/Kconfig | 20 ++++++++++----------
>> arch/arm/mach-rockchip/Makefile | 4 ++--
>> drivers/pinctrl/Kconfig | 16 ++++++++--------
>> drivers/pinctrl/rockchip/Makefile | 2 +-
>> 4 files changed, 21 insertions(+), 21 deletions(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 4/9] cosmetic: rockchip: rk3288: rename rkclk_configure_cpu
2016-07-17 14:13 ` Simon Glass
@ 2016-07-18 12:16 ` Simon Glass
0 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2016-07-18 12:16 UTC (permalink / raw)
To: u-boot
On 17 July 2016 at 08:13, Simon Glass <sjg@chromium.org> wrote:
> On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
>> The function is very specific to the rk3288 in its arguments
>> referencing the rk3288 cru and grf and every other rockchip soc
>> has differing cru and grf registers. So make that function naming
>> explicit.
>>
>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>> ---
>> arch/arm/include/asm/arch-rockchip/clock.h | 2 +-
>> arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 2 +-
>> drivers/clk/clk_rk3288.c | 2 +-
>> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188
2016-07-17 15:27 ` Simon Glass
@ 2016-07-18 12:16 ` Simon Glass
2016-07-18 13:42 ` Heiko Stübner
0 siblings, 1 reply; 36+ messages in thread
From: Simon Glass @ 2016-07-18 12:16 UTC (permalink / raw)
To: u-boot
Hi Heiko,
On 17 July 2016 at 09:27, Simon Glass <sjg@chromium.org> wrote:
> Hi Heiko,
>
> On 17 July 2016 at 09:20, Heiko St?bner <heiko@sntech.de> wrote:
>> Am Sonntag, 17. Juli 2016, 08:14:06 schrieb Simon Glass:
>>> Hi Heiko,
>>>
>>> On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
>>> > I've made some nice progress on using mainline uboot on the rk3188
>>> > and would like to dump some first results.
>>> >
>>> > Right now I can use uboot on the rk3188 with the Rockchip binary ddr init,
>>> > similar to what barebox does and can even netboot a kernel image using
>>> > a usb ethernet adapter [0] .
>>> >
>>> > While working on this I found quite some cosmetic stuff that shouldn't
>>> > persist to make extending easier. So while I don't know what the policy
>>> > is for my standalone pinctrl and clock drivers (without the actual board)
>>> > at least the cosmetics + fix might get in at least.
>>>
>>> Nice work!
>>>
>>> It would be best to add the drivers with the board - otherwise they
>>> are just dead code. How far away is it?
>>
>> The big issue is the SPL. Right now I'm using Rockchip's ddr-init as spl-
>> replacement, and I'd say this second part is nearly ready - only minor
>> cleanups.
>>
>> The memory-setup is supposed to be very much similar to the rk3288 (same
>> dw_upctl and ddr-phy), but it looks like the very first steps are somewhat
>> different and I haven't been able to make the spl output anything on the
>> serial console yet ... which could stem from some difference in what the soc
>> expects or just some dumb mistake on my part :-)
>
> That's always tricky.
>
> You may already know this, but the EARLY_UART setting is used on
> rk3288 to display a character as soon as SPL starts. You might be able
> to do something similar. The main issue I had was getting the pinmux
> setting right.
>
> As a test, you can start with booting SPL from the ddr-init binary I
> suspect. I have not tried it but it should work. Then the pinmux
> should already be set up (since ddr-init outputs to serial).
I'm going to apply the earlier patches in your series. Once you have a
working board we can apply the rest (to avoid adding dead code).
Regards,
Simon
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 5/9] rockchip: rk3288: fix FREF_MIN_HZ constant
2016-07-17 14:13 ` Simon Glass
@ 2016-07-18 12:16 ` Simon Glass
0 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2016-07-18 12:16 UTC (permalink / raw)
To: u-boot
On 17 July 2016 at 08:13, Simon Glass <sjg@chromium.org> wrote:
> On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
>> According to the TRM the minimum FREF frequency is 269kHz not MHz.
>> Adapt the constant accordingly.
>>
>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>> ---
>> drivers/clk/clk_rk3288.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 9/9] rockchip: rk3188: Add clock driver
2016-07-17 15:48 ` Simon Glass
@ 2016-07-18 13:31 ` Simon Glass
0 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2016-07-18 13:31 UTC (permalink / raw)
To: u-boot
Hi Heiko,
On 17 July 2016 at 09:48, Simon Glass <sjg@chromium.org> wrote:
> Hi Heiko,
>
> On 17 July 2016 at 09:33, Heiko St?bner <heiko@sntech.de> wrote:
>> Am Sonntag, 17. Juli 2016, 08:13:58 schrieb Simon Glass:
>>> Hi Heiko,
>>>
>>> On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
>>> > Add a driver for setting up and modifying the various PLLs and peripheral
>>> > clocks on the RK3188.
>>> >
>>> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>>> > ---
>>> >
>>> > arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 186 ++++++++++
>>> > drivers/clk/Makefile | 1 +
>>> > drivers/clk/clk_rk3188.c | 464
>>> > ++++++++++++++++++++++++ 3 files changed, 651 insertions(+)
>>> > create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3188.h
>>> > create mode 100644 drivers/clk/clk_rk3188.c
>>>
>>> Could you add a patch to move these files into a drivers/clk/rockchip
>>> directory?
>>
>> ok
>>
>>> > new file mode 100644
>>> > index 0000000..4c28393
>>> > --- /dev/null
>>> > +++ b/drivers/clk/clk_rk3188.c
>>> > @@ -0,0 +1,465 @@
>>> > +/*
>>> > + * (C) Copyright 2015 Google, Inc
>>> > + * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
>>> > + *
>>> > + * SPDX-License-Identifier: GPL-2.0
>>> > + */
>>> > +
>>> > +#include <common.h>
>>> > +#include <clk-uclass.h>
>>> > +#include <dm.h>
>>> > +#include <errno.h>
>>> > +#include <syscon.h>
>>> > +#include <asm/io.h>
>>> > +#include <asm/arch/clock.h>
>>> > +#include <asm/arch/cru_rk3188.h>
>>> > +#include <asm/arch/grf_rk3188.h>
>>> > +#include <asm/arch/hardware.h>
>>> > +#include <dt-bindings/clock/rk3188-cru.h>
>>> > +#include <dm/device-internal.h>
>>> > +#include <dm/lists.h>
>>> > +#include <dm/uclass-internal.h>
>>> > +
>>> > +DECLARE_GLOBAL_DATA_PTR;
>>> > +
>>> > +struct rk3188_clk_priv {
>>> > + struct rk3188_grf *grf;
>>> > + struct rk3188_cru *cru;
>>> > + ulong rate;
>>> > + bool has_bwadj;
>>> > +};
>>> > +
>>> > +struct pll_div {
>>> > + u32 nr;
>>> > + u32 nf;
>>> > + u32 no;
>>> > +};
>>> > +
>>> > +enum {
>>> > + VCO_MAX_HZ = 2200U * 1000000,
>>> > + VCO_MIN_HZ = 440 * 1000000,
>>> > + OUTPUT_MAX_HZ = 2200U * 1000000,
>>> > + OUTPUT_MIN_HZ = 30 * 1000000,
>>> > + FREF_MAX_HZ = 2200U * 1000000,
>>> > + FREF_MIN_HZ = 30 * 1000,
>>> > +};
>>> > +
>>> > +enum {
>>> > + /* PLL CON0 */
>>> > + PLL_OD_MASK = 0x0f,
>>> > +
>>> > + /* PLL CON1 */
>>> > + PLL_NF_MASK = 0x1fff,
>>> > +
>>> > + /* PLL CON2 */
>>> > + PLL_BWADJ_MASK = 0x0fff,
>>> > +
>>> > + /* PLL CON3 */
>>> > + PLL_RESET_SHIFT = 5,
>>> > +
>>> > + /* GRF_SOC_STATUS0 */
>>> > + SOCSTS_DPLL_LOCK = 1 << 5,
>>> > + SOCSTS_APLL_LOCK = 1 << 6,
>>> > + SOCSTS_CPLL_LOCK = 1 << 7,
>>> > + SOCSTS_GPLL_LOCK = 1 << 8,
>>> > +};
>>> > +
>>> > +#define RATE_TO_DIV(input_rate, output_rate) \
>>> > + ((input_rate) / (output_rate) - 1);
>>> > +
>>> > +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
>>> > +
>>> > +#define PLL_DIVISORS(hz, _nr, _no) {\
>>> > + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
>>> > + _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
>>> > + (_nr * _no) == hz, #hz "Hz cannot be hit with PLL
>>> > "\
>>> > + "divisors on line " __stringify(__LINE__));
>>> > +
>>> > +/* Keep divisors as low as possible to reduce jitter and power usage */
>>> > +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
>>> > +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
>>> > +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
>>> > +
>>> > +void *rockchip_get_cru(void)
>>> > +{
>>> > + struct rk3188_clk_priv *priv;
>>> > + struct udevice *dev;
>>> > + int ret;
>>> > +
>>> > + ret = uclass_get_device_by_name(UCLASS_CLK,
>>> > + "clock-controller at 20000000",
>>> > &dev);
>>>
>>> This seems odd. Could you use uclass_get_device(UCLASS_CLK, 0, .&dev) ?
>>
>> Index 0 actually gets me the 24MHz oscillator fixed clock :-), which is why I
>> switched to the by-name variant to not depend on some dts or uclass ordering.
>> I'm wondering how that works on the other socs.
>
> I suspect this might have become broken by Stephen's clock changes. I
> had a bit of a look at this but have not resolved it yet. For example
> on firefly, HDMI does not work now.
>
> There is this:
>
> enum rk_clk_id {
> CLK_OSC,
> CLK_ARM,
> CLK_DDR,
> CLK_CODEC,
> CLK_GENERAL,
> CLK_NEW,
>
> CLK_COUNT,
> };
>
> and it used to check against the platform data (see rkclk_get_clk() in
> v2016.05). I'll have a think about it.
>
>>
I found a problem here...please see:
http://patchwork.ozlabs.org/patch/649283/
Regards,
Simon
[...]
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188
2016-07-18 12:16 ` Simon Glass
@ 2016-07-18 13:42 ` Heiko Stübner
2016-07-20 14:19 ` Simon Glass
0 siblings, 1 reply; 36+ messages in thread
From: Heiko Stübner @ 2016-07-18 13:42 UTC (permalink / raw)
To: u-boot
Hi Simon,
Am Montag, 18. Juli 2016, 06:16:33 schrieb Simon Glass:
> On 17 July 2016 at 09:27, Simon Glass <sjg@chromium.org> wrote:
> > On 17 July 2016 at 09:20, Heiko St?bner <heiko@sntech.de> wrote:
> >> Am Sonntag, 17. Juli 2016, 08:14:06 schrieb Simon Glass:
> >>> Hi Heiko,
> >>>
> >>> On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
> >>> > I've made some nice progress on using mainline uboot on the rk3188
> >>> > and would like to dump some first results.
> >>> >
> >>> > Right now I can use uboot on the rk3188 with the Rockchip binary ddr
> >>> > init,
> >>> > similar to what barebox does and can even netboot a kernel image using
> >>> > a usb ethernet adapter [0] .
> >>> >
> >>> > While working on this I found quite some cosmetic stuff that shouldn't
> >>> > persist to make extending easier. So while I don't know what the
> >>> > policy
> >>> > is for my standalone pinctrl and clock drivers (without the actual
> >>> > board)
> >>> > at least the cosmetics + fix might get in at least.
> >>>
> >>> Nice work!
> >>>
> >>> It would be best to add the drivers with the board - otherwise they
> >>> are just dead code. How far away is it?
> >>
> >> The big issue is the SPL. Right now I'm using Rockchip's ddr-init as spl-
> >> replacement, and I'd say this second part is nearly ready - only minor
> >> cleanups.
> >>
> >> The memory-setup is supposed to be very much similar to the rk3288 (same
> >> dw_upctl and ddr-phy), but it looks like the very first steps are
> >> somewhat
> >> different and I haven't been able to make the spl output anything on the
> >> serial console yet ... which could stem from some difference in what the
> >> soc expects or just some dumb mistake on my part :-)
> >
> > That's always tricky.
> >
> > You may already know this, but the EARLY_UART setting is used on
> > rk3288 to display a character as soon as SPL starts. You might be able
> > to do something similar. The main issue I had was getting the pinmux
> > setting right.
> >
> > As a test, you can start with booting SPL from the ddr-init binary I
> > suspect. I have not tried it but it should work. Then the pinmux
> > should already be set up (since ddr-init outputs to serial).
yep, changing the SPL_TEXT_BASE to the ram address and using the spl as 2nd
stage brings me the expected
earlyuart running
message.
I've also dumped the sram contents after a sucessful boot using the rk ddr-
init + uboot and can see that the ddr-init is sitting at the 0x800 offset in
sram - including the rk31 header, so I'm pretty sure the sram-based
SPL_TEXT_BASE should be 0x10080804 - yet no lifesign.
Judging by how the rk3036 declares its SPL_STACK, I guess 0x10087fff should
also be right.
> I'm going to apply the earlier patches in your series. Once you have a
> working board we can apply the rest (to avoid adding dead code).
great ... everything I don't need to carry over helps ;-) .
Going forward, I see both the rk3368 and rk3399 support initially not
providing a spl but sitting on top of the binary ddr init + ATF.
Is that also something doable for my rk3188 or do you _require_ the spl there?
I.e. bringing the support without spl forward should be fairly easy, so doing
that first sounds nice, before worrying about the strange things the SPL needs.
Heiko
^ permalink raw reply [flat|nested] 36+ messages in thread
* [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188
2016-07-18 13:42 ` Heiko Stübner
@ 2016-07-20 14:19 ` Simon Glass
0 siblings, 0 replies; 36+ messages in thread
From: Simon Glass @ 2016-07-20 14:19 UTC (permalink / raw)
To: u-boot
Hi Heiko,
On 18 July 2016 at 07:42, Heiko St?bner <heiko@sntech.de> wrote:
> Hi Simon,
>
> Am Montag, 18. Juli 2016, 06:16:33 schrieb Simon Glass:
>> On 17 July 2016 at 09:27, Simon Glass <sjg@chromium.org> wrote:
>> > On 17 July 2016 at 09:20, Heiko St?bner <heiko@sntech.de> wrote:
>> >> Am Sonntag, 17. Juli 2016, 08:14:06 schrieb Simon Glass:
>> >>> Hi Heiko,
>> >>>
>> >>> On 15 July 2016 at 16:17, Heiko Stuebner <heiko@sntech.de> wrote:
>> >>> > I've made some nice progress on using mainline uboot on the rk3188
>> >>> > and would like to dump some first results.
>> >>> >
>> >>> > Right now I can use uboot on the rk3188 with the Rockchip binary ddr
>> >>> > init,
>> >>> > similar to what barebox does and can even netboot a kernel image using
>> >>> > a usb ethernet adapter [0] .
>> >>> >
>> >>> > While working on this I found quite some cosmetic stuff that shouldn't
>> >>> > persist to make extending easier. So while I don't know what the
>> >>> > policy
>> >>> > is for my standalone pinctrl and clock drivers (without the actual
>> >>> > board)
>> >>> > at least the cosmetics + fix might get in at least.
>> >>>
>> >>> Nice work!
>> >>>
>> >>> It would be best to add the drivers with the board - otherwise they
>> >>> are just dead code. How far away is it?
>> >>
>> >> The big issue is the SPL. Right now I'm using Rockchip's ddr-init as spl-
>> >> replacement, and I'd say this second part is nearly ready - only minor
>> >> cleanups.
>> >>
>> >> The memory-setup is supposed to be very much similar to the rk3288 (same
>> >> dw_upctl and ddr-phy), but it looks like the very first steps are
>> >> somewhat
>> >> different and I haven't been able to make the spl output anything on the
>> >> serial console yet ... which could stem from some difference in what the
>> >> soc expects or just some dumb mistake on my part :-)
>> >
>> > That's always tricky.
>> >
>> > You may already know this, but the EARLY_UART setting is used on
>> > rk3288 to display a character as soon as SPL starts. You might be able
>> > to do something similar. The main issue I had was getting the pinmux
>> > setting right.
>> >
>> > As a test, you can start with booting SPL from the ddr-init binary I
>> > suspect. I have not tried it but it should work. Then the pinmux
>> > should already be set up (since ddr-init outputs to serial).
>
> yep, changing the SPL_TEXT_BASE to the ram address and using the spl as 2nd
> stage brings me the expected
> earlyuart running
> message.
>
> I've also dumped the sram contents after a sucessful boot using the rk ddr-
> init + uboot and can see that the ddr-init is sitting at the 0x800 offset in
> sram - including the rk31 header, so I'm pretty sure the sram-based
> SPL_TEXT_BASE should be 0x10080804 - yet no lifesign.
>
> Judging by how the rk3036 declares its SPL_STACK, I guess 0x10087fff should
> also be right.
>
>> I'm going to apply the earlier patches in your series. Once you have a
>> working board we can apply the rest (to avoid adding dead code).
>
> great ... everything I don't need to carry over helps ;-) .
>
>
> Going forward, I see both the rk3368 and rk3399 support initially not
> providing a spl but sitting on top of the binary ddr init + ATF.
> Is that also something doable for my rk3188 or do you _require_ the spl there?
>
> I.e. bringing the support without spl forward should be fairly easy, so doing
> that first sounds nice, before worrying about the strange things the SPL needs.
That it because we don't have a good story for how to integrate ATF
with SPL at present (on ARMv8). I would much prefer to avoid this on
rk3188. Can you perhaps ask the Rockchip people on the list for help?
Regards,
Simon
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2016-07-20 14:19 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-07-15 22:17 [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188 Heiko Stuebner
2016-07-15 22:17 ` [U-Boot] [PATCH 1/9] cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-18 12:16 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 2/9] cosmetic: rockchip: rk3036: " Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-18 12:16 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 3/9] cosmetic: rockchip: sort socs according to numbers Heiko Stuebner
2016-07-16 15:47 ` Andreas Färber
2016-07-17 14:13 ` Simon Glass
2016-07-18 12:16 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 4/9] cosmetic: rockchip: rk3288: rename rkclk_configure_cpu Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-18 12:16 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 5/9] rockchip: rk3288: fix FREF_MIN_HZ constant Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-18 12:16 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 6/9] rockchip: rk3188: Add header files for PMU and GRF Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 7/9] rockchip: rk3188: Add pinctrl driver Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-17 15:47 ` Heiko Stübner
2016-07-17 15:49 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 8/9] rockchip: rk3188: Bring in rk3066/rk3188 clock bindings Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-15 22:17 ` [U-Boot] [PATCH 9/9] rockchip: rk3188: Add clock driver Heiko Stuebner
2016-07-17 14:13 ` Simon Glass
2016-07-17 15:33 ` Heiko Stübner
2016-07-17 15:48 ` Simon Glass
2016-07-18 13:31 ` Simon Glass
2016-07-17 14:14 ` [U-Boot] [PATCH 0/9] rockchip: cosmetics, a fix and first steps on the rk3188 Simon Glass
2016-07-17 15:20 ` Heiko Stübner
2016-07-17 15:27 ` Simon Glass
2016-07-18 12:16 ` Simon Glass
2016-07-18 13:42 ` Heiko Stübner
2016-07-20 14:19 ` Simon Glass
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