From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 595ECC433F5 for ; Thu, 29 Sep 2022 23:56:32 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5499184CE4; Fri, 30 Sep 2022 01:56:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="gx5Kxs7K"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id C270A84CD7; Fri, 30 Sep 2022 01:56:07 +0200 (CEST) Received: from mail-oo1-xc33.google.com (mail-oo1-xc33.google.com [IPv6:2607:f8b0:4864:20::c33]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A53B084CCB for ; Fri, 30 Sep 2022 01:56:04 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@google.com Received: by mail-oo1-xc33.google.com with SMTP id c13-20020a4ac30d000000b0047663e3e16bso1193534ooq.6 for ; Thu, 29 Sep 2022 16:56:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=vP8YfkxtKOxW3yA9G0JXT6p/QD3nNRLeVIZnznGM9/Q=; b=gx5Kxs7KmcCH3ueEY760t4ljFEyY6Y1EY8PZIVkheha/xxOCCJmL0FsEq09u5INRLd wYvYzbkdV/zZ4zAHzRS1NhH5AsgJgsfh+8TG/vSOeEm6SOgPyKjYLJ347vdRLQ8zwVGp 9XhM9Q+CpCNqVqJBO+azWJYbNvtmuoYgSVlh4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=vP8YfkxtKOxW3yA9G0JXT6p/QD3nNRLeVIZnznGM9/Q=; b=VPovmusyqEmhxjOEyQvuvrKCnbS1ltOIxnFXqLdlwdFat7HQSzapM8QCAlXkAaeRvK 8UGMBytqBUgPL+X29zBOQBEFwwRWHxvYGJkP12uwk418MJ1VyLxmXfXD6a+ncbtfNL0k TDxfi8TE4xwT8bBPiOC3FhWFPTIWHvud1fWGe2ZmVwzn2QjyPQ1Ueo8QY7GsEs/slw2v 6+gy9JnGaH8Gq4q27YtVk///BKpwQUM4Y48pSZcdke/4XjIIuQ7eDHhNOaSdjq9yMFIZ 4bsc3n8ndhJ0wu+emnu+LcE2o5DNFuW+aEKx42lc69mMvQoo1xToCcC2fJNppFhQohNr URPw== X-Gm-Message-State: ACrzQf14zajiZGIJSo86y0S9UTZNuxlp45qzejmoGrmfQ+Ll1GeJr23U dpWkSSSvATfwh45eAHDF1LPXswH/NOMHaMOhZtVDlx0Cx2s= X-Google-Smtp-Source: AMsMyM5tkpnSBXbYZjtmHmHJKJntr21wquqIltItPt+Hk6+G62o/ZWlRRKdKk9ggflR63fCcKqA2pnIrv6QLlBD8x70= X-Received: by 2002:a05:6830:20d3:b0:655:cd22:b47c with SMTP id z19-20020a05683020d300b00655cd22b47cmr2427250otq.351.1664495763011; Thu, 29 Sep 2022 16:56:03 -0700 (PDT) MIME-Version: 1.0 References: <20220929095639.355675-1-mchitale@ventanamicro.com> <20220929095639.355675-3-mchitale@ventanamicro.com> In-Reply-To: <20220929095639.355675-3-mchitale@ventanamicro.com> From: Simon Glass Date: Thu, 29 Sep 2022 17:55:51 -0600 Message-ID: Subject: Re: [RFC PATCH v1 2/3] nvme: pci: Enable for SPL To: Mayuresh Chitale Cc: Bin Meng , U-Boot Mailing List , Heinrich Schuchardt , Rick Chen , Leo Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hi Mayuresh, On Thu, 29 Sept 2022 at 03:57, Mayuresh Chitale wrote: > > Build PCI NVMe driver when enabled for SPI and enable dm-pre-reloc for > the driver. Also enable PCI_PNP for SPL which is required to auto > configure the PCIe devices. > > Signed-off-by: Mayuresh Chitale > --- > drivers/Makefile | 2 +- > drivers/nvme/Makefile | 2 +- > drivers/nvme/nvme_pci.c | 1 + > drivers/pci/Kconfig | 7 +++++++ > drivers/pci/pci-uclass.c | 3 ++- > 5 files changed, 12 insertions(+), 3 deletions(-) > > diff --git a/drivers/Makefile b/drivers/Makefile > index eba9940231..581ae9f819 100644 > --- a/drivers/Makefile > +++ b/drivers/Makefile > @@ -34,6 +34,7 @@ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/ > obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/ > obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/ > obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ > +obj-$(CONFIG_$(SPL_)NVME) += nvme/ > obj-$(CONFIG_XEN) += xen/ > obj-$(CONFIG_$(SPL_)FPGA) += fpga/ > > @@ -86,7 +87,6 @@ obj-y += crypto/ > obj-$(CONFIG_FASTBOOT) += fastboot/ > obj-y += misc/ > obj-$(CONFIG_MMC) += mmc/ > -obj-$(CONFIG_NVME) += nvme/ > obj-$(CONFIG_PCI_ENDPOINT) += pci_endpoint/ > obj-y += dfu/ > obj-$(CONFIG_PCH) += pch/ > diff --git a/drivers/nvme/Makefile b/drivers/nvme/Makefile > index fa7b619446..fd3e68a91d 100644 > --- a/drivers/nvme/Makefile > +++ b/drivers/nvme/Makefile > @@ -4,4 +4,4 @@ > > obj-y += nvme-uclass.o nvme.o nvme_show.o > obj-$(CONFIG_NVME_APPLE) += nvme_apple.o > -obj-$(CONFIG_NVME_PCI) += nvme_pci.o > +obj-$(CONFIG_$(SPL_)NVME_PCI) += nvme_pci.o > diff --git a/drivers/nvme/nvme_pci.c b/drivers/nvme/nvme_pci.c > index 36bf9c5ffb..16d8b9fff7 100644 > --- a/drivers/nvme/nvme_pci.c > +++ b/drivers/nvme/nvme_pci.c > @@ -39,6 +39,7 @@ U_BOOT_DRIVER(nvme) = { > .bind = nvme_bind, > .probe = nvme_probe, > .priv_auto = sizeof(struct nvme_dev), > + .flags = DM_FLAG_PRE_RELOC, Why is this here? It is only applicable on some boards. Instead, add the appropriate tag (e.g. u-boot,dm-spl) to the device node. > }; > > struct pci_device_id nvme_supported[] = { > diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig > index 22f4995453..2d4c9f0781 100644 > --- a/drivers/pci/Kconfig > +++ b/drivers/pci/Kconfig > @@ -40,6 +40,13 @@ config PCI_PNP > help > Enable PCI memory and I/O space resource allocation and assignment. > > +config SPL_PCI_PNP > + bool "Enable Plug & Play support for PCI" > + default n > + help > + Enable PCI memory and I/O space resource allocation and assignment. > + This is required to auto configure the enumerated devices. > + > config PCI_REGION_MULTI_ENTRY > bool "Enable Multiple entries of region type MEMORY in ranges for PCI" > help > diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c > index 16a6a699f9..62d2409a6d 100644 > --- a/drivers/pci/pci-uclass.c > +++ b/drivers/pci/pci-uclass.c > @@ -1140,7 +1140,8 @@ static int pci_uclass_post_probe(struct udevice *bus) > if (ret) > return log_msg_ret("bind", ret); > > - if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() && > + if ((CONFIG_IS_ENABLED(PCI_PNP) || CONFIG_IS_ENABLED(SPL_PCI_PNP)) && > + ll_boot_init() && > (!hose->skip_auto_config_until_reloc || > (gd->flags & GD_FLG_RELOC))) { > ret = pci_auto_config_devices(bus); > -- > 2.25.1 > Regards, Simon