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* [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support
@ 2015-12-11 10:55 Bin Meng
  2015-12-11 10:55 ` [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP Bin Meng
                   ` (9 more replies)
  0 siblings, 10 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
  To: u-boot

This series adds Intel FSP support to IvyBridge processor and
Panther Point chipset (aka Chief River platform), and is validated
on Intel Cougar Canyon 2 board.

This only adds basic features like serial, keyboard, RTC, timer,
SPI, GPIO, PCI, SATA, USB. Other features will be enabled in future
patch set.


Bin Meng (10):
  fdtdec: Add compatible string for Intel IvyBridge FSP
  x86: ivybridge: Add FSP support
  tools: microcode-tool: Support parsing header file with a license
    block
  x86: ivybridge: Add microcode blobs for all the steppings
  superio: Add SMSC SIO1007 driver
  x86: ivybridge: Do not require HAVE_INTEL_ME
  x86: fsp: Make sure HOB list is not overwritten by U-Boot
  x86: fsp: Always use hex numbers in the hob command output
  x86: ivybridge: Add macros for LPC decode ranges
  x86: Add Intel Cougar Canyon 2 board

 arch/x86/cpu/ivybridge/Kconfig                     |   9 +-
 arch/x86/cpu/ivybridge/Makefile                    |   4 +
 arch/x86/cpu/ivybridge/fsp_configs.c               |  45 ++
 arch/x86/cpu/ivybridge/ivybridge.c                 |  22 +
 arch/x86/dts/Makefile                              |   1 +
 arch/x86/dts/cougarcanyon2.dts                     |  96 +++
 arch/x86/dts/microcode/m12306a2_00000008.dtsi      | 554 +++++++++++++++++
 arch/x86/dts/microcode/m12306a4_00000007.dtsi      | 618 +++++++++++++++++++
 arch/x86/dts/microcode/m12306a5_00000007.dtsi      | 618 +++++++++++++++++++
 arch/x86/dts/microcode/m12306a8_00000010.dtsi      | 682 +++++++++++++++++++++
 .../include/asm/arch-ivybridge/fsp/fsp_configs.h   |  40 ++
 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h  |  12 +
 arch/x86/include/asm/arch-ivybridge/pch.h          |  10 +
 arch/x86/lib/fsp/cmd_fsp.c                         |   4 +-
 arch/x86/lib/fsp/fsp_support.c                     |  27 +
 board/google/chromebook_link/Kconfig               |   1 +
 board/google/chromebox_panther/Kconfig             |   1 +
 board/intel/Kconfig                                |   9 +
 board/intel/cougarcanyon2/Kconfig                  |  25 +
 board/intel/cougarcanyon2/MAINTAINERS              |   6 +
 board/intel/cougarcanyon2/Makefile                 |   7 +
 board/intel/cougarcanyon2/cougarcanyon2.c          |  48 ++
 board/intel/cougarcanyon2/start.S                  |   9 +
 configs/cougarcanyon2_defconfig                    |  21 +
 drivers/misc/Makefile                              |   1 +
 drivers/misc/smsc_sio1007.c                        | 126 ++++
 include/configs/cougarcanyon2.h                    |  34 +
 include/fdtdec.h                                   |   1 +
 include/smsc_sio1007.h                             | 115 ++++
 lib/fdtdec.c                                       |   1 +
 tools/microcode-tool.py                            |  14 +
 31 files changed, 3158 insertions(+), 3 deletions(-)
 create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
 create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
 create mode 100644 arch/x86/dts/cougarcanyon2.dts
 create mode 100644 arch/x86/dts/microcode/m12306a2_00000008.dtsi
 create mode 100644 arch/x86/dts/microcode/m12306a4_00000007.dtsi
 create mode 100644 arch/x86/dts/microcode/m12306a5_00000007.dtsi
 create mode 100644 arch/x86/dts/microcode/m12306a8_00000010.dtsi
 create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
 create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
 create mode 100644 board/intel/cougarcanyon2/Kconfig
 create mode 100644 board/intel/cougarcanyon2/MAINTAINERS
 create mode 100644 board/intel/cougarcanyon2/Makefile
 create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c
 create mode 100644 board/intel/cougarcanyon2/start.S
 create mode 100644 configs/cougarcanyon2_defconfig
 create mode 100644 drivers/misc/smsc_sio1007.c
 create mode 100644 include/configs/cougarcanyon2.h
 create mode 100644 include/smsc_sio1007.h

-- 
1.8.2.1

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP
  2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
  2015-12-19  2:51   ` Simon Glass
  2015-12-11 10:55 ` [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support Bin Meng
                   ` (8 subsequent siblings)
  9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
  To: u-boot

Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 include/fdtdec.h | 1 +
 lib/fdtdec.c     | 1 +
 2 files changed, 2 insertions(+)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 7fe657d..c515a3c 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -169,6 +169,7 @@ enum fdt_compat_id {
 	COMPAT_ALTERA_SOCFPGA_DWMMC,	/* SoCFPGA DWMMC controller */
 	COMPAT_INTEL_BAYTRAIL_FSP,	/* Intel Bay Trail FSP */
 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-down params */
+	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge FSP */
 
 	COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 82d0090..002594d 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
 	COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
 	COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
+	COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
1.8.2.1

^ permalink raw reply related	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support
  2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
  2015-12-11 10:55 ` [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
  2015-12-19  2:52   ` Simon Glass
  2015-12-11 10:55 ` [U-Boot] [PATCH 03/10] tools: microcode-tool: Support parsing header file with a license block Bin Meng
                   ` (7 subsequent siblings)
  9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
  To: u-boot

IvyBridge FSP package is built with a base address at 0xfff80000,
and does not use UPD data region. This adds basic FSP support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/ivybridge/Kconfig                     |  8 ++++
 arch/x86/cpu/ivybridge/Makefile                    |  4 ++
 arch/x86/cpu/ivybridge/fsp_configs.c               | 45 ++++++++++++++++++++++
 arch/x86/cpu/ivybridge/ivybridge.c                 | 22 +++++++++++
 .../include/asm/arch-ivybridge/fsp/fsp_configs.h   | 40 +++++++++++++++++++
 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h  | 12 ++++++
 6 files changed, 131 insertions(+)
 create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
 create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
 create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
 create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h

diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index 56abd8f..36b74c2 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -72,4 +72,12 @@ config ENABLE_VMX
 	  will be unable to support virtualisation, or it will run very
 	  slowly.
 
+config FSP_ADDR
+	hex
+	default 0xfff80000
+
+config FSP_USE_UPD
+	bool
+	default n
+
 endif
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 0c7efae..d74635e 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -4,6 +4,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+ifdef CONFIG_HAVE_FSP
+obj-y += fsp_configs.o ivybridge.o
+else
 obj-y += bd82x6x.o
 obj-y += car.o
 obj-y += cpu.o
@@ -22,3 +25,4 @@ obj-y += sata.o
 obj-y += sdram.o
 obj-y += usb_ehci.o
 obj-y += usb_xhci.o
+endif
diff --git a/arch/x86/cpu/ivybridge/fsp_configs.c b/arch/x86/cpu/ivybridge/fsp_configs.c
new file mode 100644
index 0000000..5d8b814
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/fsp_configs.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void update_fsp_configs(struct fsp_config_data *config,
+			struct fspinit_rtbuf *rt_buf)
+{
+	struct platform_config *plat_config = &config->plat_config;
+	struct memory_config *mem_config = &config->mem_config;
+	const void *blob = gd->fdt_blob;
+	int node;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IVYBRIDGE_FSP);
+	if (node < 0) {
+		debug("%s: Cannot find FSP node\n", __func__);
+		return;
+	}
+
+	plat_config->enable_ht =
+		fdtdec_get_bool(blob, node, "fsp,enable-ht");
+	plat_config->enable_turbo =
+		fdtdec_get_bool(blob, node, "fsp,enable-turbo");
+	plat_config->enable_memory_down =
+		fdtdec_get_bool(blob, node, "fsp,enable-memory-down");
+	plat_config->enable_fast_boot =
+		fdtdec_get_bool(blob, node, "fsp,enable-fast-boot");
+
+	/* Initialize runtime buffer for fsp_init() */
+	rt_buf->stack_top = config->common.stack_top - 32;
+	rt_buf->boot_mode = config->common.boot_mode;
+	rt_buf->plat_config = plat_config;
+
+	if (plat_config->enable_memory_down)
+		rt_buf->mem_config = mem_config;
+	else
+		rt_buf->mem_config = NULL;
+}
diff --git a/arch/x86/cpu/ivybridge/ivybridge.c b/arch/x86/cpu/ivybridge/ivybridge.c
new file mode 100644
index 0000000..afe7e57
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/ivybridge.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/post.h>
+#include <asm/processor.h>
+
+int arch_cpu_init(void)
+{
+	int ret;
+
+	post_code(POST_CPU_INIT);
+
+	ret = x86_cpu_init_f();
+	if (ret)
+		return ret;
+
+	return 0;
+}
diff --git a/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
new file mode 100644
index 0000000..24e2f2f
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+struct platform_config {
+	u8 enable_ht;
+	u8 enable_turbo;
+	u8 enable_memory_down;
+	u8 enable_fast_boot;
+};
+
+/*
+ * Dummy structure for now as currently only SPD is verified in U-Boot.
+ *
+ * We can add the missing parameters when adding support on a board with
+ * memory down configuration.
+ */
+struct memory_config {
+	u8 dummy;
+};
+
+struct fsp_config_data {
+	struct fsp_cfg_common common;
+	struct platform_config plat_config;
+	struct memory_config mem_config;
+};
+
+struct fspinit_rtbuf {
+	u32 stack_top;
+	u32 boot_mode;
+	struct platform_config *plat_config;
+	struct memory_config *mem_config;
+};
+
+#endif /* __FSP_CONFIGS_H__ */
diff --git a/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
new file mode 100644
index 0000000..be9f055
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+#ifndef __FSP_VPD_H__
+#define __FSP_VPD_H__
+
+/* IvyBridge FSP does not support VPD/UPD */
+
+#endif
-- 
1.8.2.1

^ permalink raw reply related	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 03/10] tools: microcode-tool: Support parsing header file with a license block
  2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
  2015-12-11 10:55 ` [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP Bin Meng
  2015-12-11 10:55 ` [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
  2015-12-19  2:52   ` Simon Glass
  2015-12-11 10:55 ` [U-Boot] [PATCH 04/10] x86: ivybridge: Add microcode blobs for all the steppings Bin Meng
                   ` (6 subsequent siblings)
  9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
  To: u-boot

The microcode header files in the Intel Chief River FSP package have
a license comment block. Update the microcode-tool to support parsing
it and extract the license text to the .dtsi file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 tools/microcode-tool.py | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py
index 71c2e91..790c27e 100755
--- a/tools/microcode-tool.py
+++ b/tools/microcode-tool.py
@@ -95,9 +95,23 @@ def ParseHeaderFiles(fname_list):
         name = os.path.splitext(name)[0]
         data = []
         with open(fname) as fd:
+            license_start = False
+            license_end = False
             for line in fd:
                 line = line.rstrip()
 
+                if len(line) >= 2:
+                    if line[0] == '/' and line[1] == '*':
+                        license_start = True
+                        continue
+                    if line[0] == '*' and line[1] == '/':
+                        license_end = True
+                        continue
+                if license_start and not license_end:
+                    # Ignore blank line
+                    if len(line) > 0:
+                        license_text.append(line)
+                    continue
                 # Omit anything after the last comma
                 words = line.split(',')[:-1]
                 data += [word + ',' for word in words]
-- 
1.8.2.1

^ permalink raw reply related	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 04/10] x86: ivybridge: Add microcode blobs for all the steppings
  2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
                   ` (2 preceding siblings ...)
  2015-12-11 10:55 ` [U-Boot] [PATCH 03/10] tools: microcode-tool: Support parsing header file with a license block Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
  2015-12-19  2:52   ` Simon Glass
  2015-12-11 10:55 ` [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver Bin Meng
                   ` (5 subsequent siblings)
  9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
  To: u-boot

This adds microcode blobs created from Intel FSP package for the
Chief River platform. They are for all the Ivy Bridge steppings:
306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
306a9 which is already in the U-Boot tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/dts/microcode/m12306a2_00000008.dtsi | 554 +++++++++++++++++++++
 arch/x86/dts/microcode/m12306a4_00000007.dtsi | 618 +++++++++++++++++++++++
 arch/x86/dts/microcode/m12306a5_00000007.dtsi | 618 +++++++++++++++++++++++
 arch/x86/dts/microcode/m12306a8_00000010.dtsi | 682 ++++++++++++++++++++++++++
 4 files changed, 2472 insertions(+)
 create mode 100644 arch/x86/dts/microcode/m12306a2_00000008.dtsi
 create mode 100644 arch/x86/dts/microcode/m12306a4_00000007.dtsi
 create mode 100644 arch/x86/dts/microcode/m12306a5_00000007.dtsi
 create mode 100644 arch/x86/dts/microcode/m12306a8_00000010.dtsi

diff --git a/arch/x86/dts/microcode/m12306a2_00000008.dtsi b/arch/x86/dts/microcode/m12306a2_00000008.dtsi
new file mode 100644
index 0000000..6b35c39
--- /dev/null
+++ b/arch/x86/dts/microcode/m12306a2_00000008.dtsi
@@ -0,0 +1,554 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ *   list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ *   be used to endorse or promote products derived from this software without
+ *   specific prior written permission.
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *   THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x8>;
+intel,date-code = <0x5182011>;
+intel,processor-signature = <0x306a2>;
+intel,checksum = <0xa0e51feb>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x08000000	0x11201805	0xa2060300
+	0xeb1fe5a0	0x01000000	0x12000000	0xd01f0000
+	0x00200000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x08000000
+	0x00000000	0x00000000	0x17051120	0xd1070000
+	0x01000000	0xa2060300	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x5665ff94	0x179da7cf	0x1e819fb2	0xb0c24e8e
+	0x5cb7beb5	0x43af9a6c	0xcb0b4ccc	0x195d8712
+	0xdb01345a	0xceecca42	0x5ee7d8b4	0x24afdbe6
+	0x5fb36178	0xbc17d76b	0x31b7b923	0xc81aec82
+	0x647b3320	0xf1db9653	0xff3b9759	0xe9c74b72
+	0x3b193752	0xc147860b	0x160e0d6a	0x5bdb9dbf
+	0x1ccce2ac	0x387670ad	0x2f106f05	0xf8607ea3
+	0x42562576	0x30e086fb	0x409a06b8	0xf1957736
+	0x5eb03f65	0xad147fab	0xe1a8e8b6	0x208d59d2
+	0x683fba2e	0xf172b378	0xf8138dba	0x61e81d1f
+	0xd551f997	0x28c79780	0x04f9db27	0xa80679b9
+	0xaca4e7ff	0x6876944b	0x26d7dbc1	0x77f7dc2a
+	0xf0bcb163	0x1b2a8e81	0x7b90aa49	0x8d5eaf2f
+	0x522384ae	0xae7f7082	0x412ba10a	0x1ce1baa0
+	0x478c29b4	0x9c09b4d2	0xf225f64f	0xd43026cd
+	0x81098579	0x7df5db05	0xa5815bb0	0xc73ee756
+	0x9738cb95	0xa5bd62e2	0x88e2c6b2	0x778e7fcb
+	0xd3bdb872	0x9404403f	0x5be6ad63	0x71dc4abc
+	0x11000000	0x72873db0	0x0f41a6d6	0x609f17c3
+	0x1b1349d0	0xe1950c52	0xdbc8e4fc	0xebc212b5
+	0x77697371	0x7b156982	0xe71e5ccf	0x78bd638c
+	0x1b196322	0x8b7ebfbf	0xc2e2588f	0xf139b826
+	0x98ac3169	0xaa9131b0	0x2d7563f8	0xa1300b39
+	0x5bd4675f	0x25a4b079	0xe006afb1	0x2bd60828
+	0x453a0abb	0x3b944679	0x33fd63fd	0xd26ff3c9
+	0x23c0a581	0xf3beb03a	0xc07109cb	0x2e4c27d9
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+	0xd6829c4d	0x8f178677	0x8ae6291d	0xb5660702
+	>;
diff --git a/arch/x86/dts/microcode/m12306a4_00000007.dtsi b/arch/x86/dts/microcode/m12306a4_00000007.dtsi
new file mode 100644
index 0000000..c39fbd3
--- /dev/null
+++ b/arch/x86/dts/microcode/m12306a4_00000007.dtsi
@@ -0,0 +1,618 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ *   list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ *   be used to endorse or promote products derived from this software without
+ *   specific prior written permission.
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *   THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x7>;
+intel,date-code = <0x9082011>;
+intel,processor-signature = <0x306a4>;
+intel,checksum = <0x7e23e5af>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x07000000	0x11200809	0xa4060300
+	0xafe5237e	0x01000000	0x12000000	0xd0230000
+	0x00240000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x07000000
+	0x00000000	0x00000000	0x07091120	0xd1080000
+	0x01000000	0xa4060300	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x9539a0b3	0xc7bb991d	0x308f0f1a	0xb1ba077d
+	0x8bd7260b	0xd710ad0c	0xf82ee64b	0xe6f11ce1
+	0xdb01345a	0xceecca42	0x5ee7d8b4	0x24afdbe6
+	0x5fb36178	0xbc17d76b	0x31b7b923	0xc81aec82
+	0x647b3320	0xf1db9653	0xff3b9759	0xe9c74b72
+	0x3b193752	0xc147860b	0x160e0d6a	0x5bdb9dbf
+	0x1ccce2ac	0x387670ad	0x2f106f05	0xf8607ea3
+	0x42562576	0x30e086fb	0x409a06b8	0xf1957736
+	0x5eb03f65	0xad147fab	0xe1a8e8b6	0x208d59d2
+	0x683fba2e	0xf172b378	0xf8138dba	0x61e81d1f
+	0xd551f997	0x28c79780	0x04f9db27	0xa80679b9
+	0xaca4e7ff	0x6876944b	0x26d7dbc1	0x77f7dc2a
+	0xf0bcb163	0x1b2a8e81	0x7b90aa49	0x8d5eaf2f
+	0x522384ae	0xae7f7082	0x412ba10a	0x1ce1baa0
+	0x478c29b4	0x9c09b4d2	0xf225f64f	0xd43026cd
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+	0xd3bdb872	0x9404403f	0x5be6ad63	0x71dc4abc
+	0x11000000	0x71f0ab19	0x85635e57	0xfecdeb36
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+	0xd39589f4	0x3159c597	0x76a0a4ec	0xf434b1c5
+	0xf3a26de7	0xe9b69e3c	0xceb232f8	0x7bc91c43
+	0x225cfa3a	0xdbabb166	0x04d4782f	0xd573884a
+	0x351f5f88	0x4acda1e6	0x2cb93b68	0xed4b0663
+	0x1dd147b0	0x4b64aa81	0x9baaddd3	0xdb305d03
+	0xe44403aa	0xd52140b8	0x442e2197	0xfb8f8aa2
+	0xa1d2b054	0x30ac7b0e	0x535ff138	0xa34c29fb
+	0x4dcff8e5	0x4d4b5af7	0x75846d8b	0x29060275
+	0x154f0dbc	0xf506c696	0x18706d08	0xbe1cddfe
+	0xc972edf3	0x070f4aae	0xe5055290	0x12ff9063
+	0xe4b81a09	0x11ad8348	0x184faea6	0xfe9b3674
+	0xd8a68c8c	0x28366da2	0xd0729297	0x8c07e77b
+	0xe85cb507	0x54d582d1	0x0e10aa56	0x5f79aff3
+	0xb5c2f58c	0x0976ca59	0xd43bed61	0x9e76951d
+	0x4bc2542e	0x7a1870fc	0x2cd01266	0xcc717daa
+	0x045e2757	0xa5b943c8	0xbbb21e51	0xa19b070c
+	0x985e3e58	0xb0f22523	0x1dfac693	0xe2491946
+	0x649791b6	0x54d4f8fc	0x2920c0c0	0x45af983c
+	0xd400878f	0xbf94ce47	0x00dacb15	0x8f79afc0
+	0x96d4d1f6	0xdacc4fee	0x3eac2a87	0x89f808a3
+	0xa8963eb3	0x3bfbf9fc	0x16970a5b	0xdc925ecb
+	0xfa5e4920	0x219ffbea	0xfb442d8f	0x32a5d657
+	0x7db7483a	0xfb330167	0xe75f7f87	0xea1de0e1
+	0x764b080a	0xed1eab80	0x6b75f59a	0x8dceba7f
+	0x735a7fce	0x68128837	0x7243057b	0x4da7a027
+	0xc1c502ca	0xa5f2bcc4	0xf2c6209c	0xb675c45d
+	0xa5aef423	0x362b5df4	0x7840609c	0x714209ea
+	0x3919be09	0xc67c360b	0x6ffe8d84	0x3dcc0e10
+	0x558ec8dd	0xa2285d7b	0x9eb86078	0xb4685e77
+	0x3840ab30	0x2ac2fdb1	0xc6b795c0	0x834c15c0
+	0xaa0ff942	0x74fdc7e3	0x87ab3565	0xa9d3f71c
+	0x53ad4955	0xad5191de	0x3e30a79e	0xee227702
+	0x5910cbaa	0xce926dbc	0x629937d9	0x271e98ea
+	0x29ac6f12	0x09248669	0x74d8fbb5	0x435a83c3
+	0x93dd39a3	0x7bcab8ab	0xf86858ac	0x403823a8
+	0xd9fb5669	0xddfdc2b6	0x9b7e771a	0xf7a6a574
+	0x1bdc0062	0x54c621be	0x45a49ac5	0xf4b5c38c
+	0xe7916b1f	0x4ea7f121	0xd5457986	0x6bb57a6f
+	0x1bc4d42b	0x2ab0ee84	0x5b8e508e	0x6adf0b60
+	0x1c39dc48	0x25d58fce	0x54327b32	0x93718903
+	0x991e452b	0x627cc0d3	0x15233871	0xf921f79a
+	0xea6475d1	0x9b155143	0x5914ee94	0xbbeb43cf
+	0xbd590426	0x8aaaa0c4	0x50b174a1	0x51aa1955
+	0xea349dfc	0x005a2de4	0x4603a63a	0x971af0b8
+	0xbcd89a17	0x1d49e631	0x63d3a40c	0x63b0f1eb
+	0x975757fe	0x706e086e	0x161d0cad	0x5b5f4fe0
+	0x4a82f4de	0x34800a89	0xdcfeeb96	0xae9c0bb8
+	0xa6422c15	0x8ee1b10d	0xa454ec0b	0x1a51e7eb
+	0xd2767564	0x8541c726	0x7e0a8cb8	0xbd6f58ef
+	0x7325c5fd	0x5f8b8144	0xb18853e2	0xd6ac3e90
+	0xeccfdfaa	0x8bed8778	0x7d65f220	0x86502ddb
+	0x272d7bbd	0x9546beb4	0x2fdbc971	0x8f86c26d
+	0x317131ee	0x06a2d84b	0xcfaeb274	0xbdc64496
+	0x842eee16	0xc5596e5e	0x3fc8d83e	0x60ce3e3d
+	0x233ff26f	0x8e7eea69	0x3dfb8b62	0x0bd1271f
+	0x3276add3	0xdce0f322	0x272f2fed	0x310b01b9
+	0xec13dbff	0x44ecef5f	0x716a95b1	0x8e2ed760
+	0xfc1cdbf3	0x363ab021	0x529c749c	0xb8361787
+	0xb576b8dd	0x05ba72be	0xbd94ddca	0x995823cd
+	0x4bf10e99	0x6350d475	0x6fab0d5d	0xa3fb7ef0
+	0xa755d719	0xefeb5c22	0x8369b60e	0xa190b7b2
+	0xf1ca5eba	0x406fbd8f	0x0b858d59	0x9f4f3a99
+	0x600706c0	0x8efb77fd	0x8ebd23fe	0xa82b4e93
+	0x44d50e4f	0x92a2b5a1	0xde8229a0	0xa9128ba4
+	0x6dc829bb	0x5d63bac1	0x8948d416	0xbb85eebc
+	0x4b280f18	0x6156e24b	0x5271526e	0x3a550970
+	0x7212c942	0x09040eba	0x0c199ae0	0x3f41b3f9
+	0x8d439401	0x83319b2d	0xf3deffb4	0xfd813e2a
+	0xa8ac6a50	0x72858022	0x5650a6ea	0x8b9e18a3
+	0x7dc2d48e	0xabf0c35c	0xe9d93f5c	0x228412d4
+	0xa7b07016	0x0babb01b	0x36faa524	0x3157fe90
+	0x4cf0fd08	0x1272a76a	0x8e701e54	0xd1ed3067
+	0xe92bc6ac	0xea2fcc5d	0xdae1a6c7	0x4ec3465f
+	0x97556141	0xda282893	0x2bdf77f3	0x458abb7b
+	0x8c98d27e	0x9f2ddc8e	0x4bf66134	0x7ef33d1d
+	0xe7bfef39	0xa9b37d3e	0x2272b785	0x41bc32d3
+	0x16790e7a	0xfcd172a9	0x4dcbdb4f	0xadc6cea4
+	0xe72aab79	0xd3a530cd	0x153171ea	0x60d6122e
+	0x1b00ebde	0x366861f2	0x6781fc14	0xe6d6189c
+	0x3b9beebb	0x5c239e07	0x51999573	0x5b900c94
+	0x52a14fae	0xc7c0bdfb	0x5bebb646	0xaaebca2f
+	0x360c6d2f	0xc8b43453	0x16ae683d	0x11248d2a
+	0x08fa3017	0x2bfc636f	0x7360ae91	0x793ad23c
+	0x7d2bc4bc	0x2d505664	0xee449c94	0xbd0beb6a
+	0xa9b818e7	0x251354ca	0x119825e5	0xae8b8d2c
+	0xeea15a2f	0x8b3c47ad	0x2af74ac7	0xaedb8156
+	0x9b96ee47	0x05034a2f	0x752f8722	0x0f1ee372
+	0xff55b4b5	0xd12d4ead	0x554c31c4	0xc167849a
+	0x118d9c61	0x9825a5b5	0xd1941592	0xa21440d6
+	0x0c8fa874	0xd23ff93c	0xf592f75b	0x6d171131
+	0xe1cc848b	0xe73fe5cf	0x38677f4a	0xddbbd004
+	0x6af79754	0xa666b38e	0xf5afba55	0x036b1f0b
+	0xd55860f2	0x1efdbe6f	0xafc557a4	0x3b24c27d
+	0x68f319ef	0xf863285e	0x80e88563	0xbe2af6a4
+	0x81360909	0xcfbaac9a	0xa0a07505	0x8c653634
+	0xf630bc25	0xdea1640f	0x51445022	0x8bd02194
+	0x593185c9	0xc23f98f1	0x06b6d384	0x432278ed
+	0x9c422519	0x0664dc91	0x733e7075	0x9e05a4c2
+	0x1b014110	0xc4787233	0x4aad488b	0x756f0d47
+	0x9e29a6df	0xabde4b5d	0x23727bdb	0xf1e3a05d
+	0xa1f22c40	0x2d290090	0x62d3b212	0xcc247195
+	0xcd5c84a1	0xf277c61f	0x4f9f213a	0xa69e7391
+	0xf09f4162	0x44771471	0x6be202f9	0xf27e05bd
+	0xef27ffc6	0xb94d8b95	0xcc124e11	0x6d22e955
+	0x8c572ef0	0xc59727f0	0xa68aa858	0x034de5f4
+	0x242700ae	0xcad4225a	0xb5e792ea	0xf791ab32
+	0x8f75a863	0xd078bb02	0xec889a62	0xbae59fa8
+	0xd0e96b37	0x7127e3a9	0x69283a7c	0x7fe26fca
+	0x3b33f97f	0xef3bfad2	0x0a33c011	0x060e0e58
+	0x27de1402	0x55f0b8c9	0xf48de31c	0xacbc1c7e
+	0x228459e6	0x9119a04c	0xeae173ef	0x50347a6c
+	0x6da1ae72	0xcea1256b	0xc328fe6a	0x85a48b53
+	0xd8bdb49b	0x857cd611	0x2218a975	0x4893fbe3
+	0xbd0b7590	0xdc35b430	0x0b37d8a4	0xc1938a77
+	0x78423be3	0xbb14bb91	0x0c900fe5	0x82037d1e
+	0x1fc0a8c5	0x5b83cd7a	0xf1a7ff8d	0x36cb83e6
+	>;
diff --git a/arch/x86/dts/microcode/m12306a5_00000007.dtsi b/arch/x86/dts/microcode/m12306a5_00000007.dtsi
new file mode 100644
index 0000000..de50372
--- /dev/null
+++ b/arch/x86/dts/microcode/m12306a5_00000007.dtsi
@@ -0,0 +1,618 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ *   list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ *   be used to endorse or promote products derived from this software without
+ *   specific prior written permission.
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *   THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x7>;
+intel,date-code = <0x9092011>;
+intel,processor-signature = <0x306a5>;
+intel,checksum = <0x8e38731>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x07000000	0x11200909	0xa5060300
+	0x3187e308	0x01000000	0x12000000	0xd0230000
+	0x00240000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x07000000
+	0x00000000	0x00000000	0x08091120	0x71080000
+	0x01000000	0xa5060300	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x27649db1	0x904b6445	0x6acff7e8	0xc4ac0631
+	0x6830ec45	0x3aece98d	0x97bf40c8	0x83b8fef0
+	0xdb01345a	0xceecca42	0x5ee7d8b4	0x24afdbe6
+	0x5fb36178	0xbc17d76b	0x31b7b923	0xc81aec82
+	0x647b3320	0xf1db9653	0xff3b9759	0xe9c74b72
+	0x3b193752	0xc147860b	0x160e0d6a	0x5bdb9dbf
+	0x1ccce2ac	0x387670ad	0x2f106f05	0xf8607ea3
+	0x42562576	0x30e086fb	0x409a06b8	0xf1957736
+	0x5eb03f65	0xad147fab	0xe1a8e8b6	0x208d59d2
+	0x683fba2e	0xf172b378	0xf8138dba	0x61e81d1f
+	0xd551f997	0x28c79780	0x04f9db27	0xa80679b9
+	0xaca4e7ff	0x6876944b	0x26d7dbc1	0x77f7dc2a
+	0xf0bcb163	0x1b2a8e81	0x7b90aa49	0x8d5eaf2f
+	0x522384ae	0xae7f7082	0x412ba10a	0x1ce1baa0
+	0x478c29b4	0x9c09b4d2	0xf225f64f	0xd43026cd
+	0x81098579	0x7df5db05	0xa5815bb0	0xc73ee756
+	0x9738cb95	0xa5bd62e2	0x88e2c6b2	0x778e7fcb
+	0xd3bdb872	0x9404403f	0x5be6ad63	0x71dc4abc
+	0x11000000	0xb290ba8e	0x6671b099	0x7834fb60
+	0xe02e439f	0x55712161	0x5dca20ba	0xb62c06df
+	0x83d86103	0x35cbe438	0xeb7841c9	0xded7ad9a
+	0xda76b9f2	0xa39233f5	0x11377a10	0x6928a0e1
+	0xf6164be1	0xab9cb400	0x0ac5e864	0x978e6cdc
+	0x51d9070c	0x3786d896	0xa6b103d0	0x288c8c83
+	0x9c644099	0xf9a8a7ad	0xd2a96566	0x2e985d7e
+	0x3531b0b8	0x3906909b	0xce3878c3	0x30b950a6
+	0x536b312c	0xb9f07473	0x29366b16	0x7a515f52
+	0xce7d21ff	0xfe5aef73	0x69b91f78	0xd50b9686
+	0xa384ac5c	0x6e90981b	0xc37028fa	0xc448c695
+	0x3c5275e0	0x2ea780c0	0x5fe9aeb5	0xa733e8e1
+	0x2a04c422	0x68243f2e	0x5311d43b	0x93c27dfc
+	0xc78b431f	0x9a7bd54e	0x7731f225	0x0f71db56
+	0xf89a8f8c	0xc5eb2d2a	0x45f973ec	0xbb0635b3
+	0x5b825acf	0x8744ccef	0xceb1dfca	0x5e5b882f
+	0x356cfd00	0x68e42c02	0xf0ea6e97	0xa0c1327c
+	0x5fb06338	0x3e7df893	0x5c3eb0ec	0xac7cc79f
+	0x3dee3b4b	0x313a2915	0x4002db54	0xe8a96a04
+	0xb79c367e	0x6d53a3a8	0x9b2720c7	0xf5e7dee4
+	0x357fc3d7	0xcfc9b54e	0x72f9732e	0x3ccbe991
+	0xe0486033	0xabeab549	0x032089b2	0xeb1467b3
+	0x3898e23d	0x4f25f3d4	0xe2f64597	0x3e7facd4
+	0x455514e6	0x99dea4e4	0xc1201200	0x72d68181
+	0x25046d7e	0xd3b6ada4	0xd3f358b2	0xb6a0dcf5
+	0xfbf43626	0xd9cafa7a	0x27ec8d4a	0x84d60c14
+	0x35e79275	0x413169be	0xbc9847c4	0x0ddcad0f
+	0x5e098c03	0x03187763	0xed64abff	0x8eaada0c
+	0xdf378018	0xf394b0fa	0xd4abca64	0x3ad203b6
+	0x1347cdf9	0xffaf1040	0x078c6baf	0xf2e7d31f
+	0xdfc334c5	0x061d2348	0x85877503	0x561b6cef
+	0xfc9aa2ed	0x6057d0b6	0x288df59a	0xda7c47f2
+	0x727a8584	0x58f74d64	0x8afa48dc	0xf50d3582
+	0x9f42eec8	0x776d1b6a	0x35f42768	0xbdb7f7bb
+	0xa239bc05	0x1d26bcce	0x025568ca	0xa2ef8189
+	0x0054417e	0xf9aff2b5	0x56cc33be	0xed695186
+	0x58b21d0d	0xea2215c7	0xa565b724	0x2931c422
+	0xe20b2043	0xa85a082d	0xd7760789	0x58c317cd
+	0x8c500d70	0xecd22975	0x79542e54	0x790b048f
+	0xcbbc98fb	0x125b81f9	0xe3e74009	0xc6f4ebc8
+	0x1e22f4b7	0x0485cac9	0xeb4dc6c9	0xab9076a3
+	0x9feccd38	0x733e57dc	0xe250d25c	0xf0eb5a8f
+	0x3db33c3c	0x36c52b3b	0xfe5f92fa	0x0ddc38bf
+	0x003c6542	0x154abb1d	0x4feb8d85	0x6aae78dd
+	0x59282b12	0x04fec81c	0xf6f117c7	0x7123b56e
+	0xd8c53d48	0xff2eeac6	0x09716dee	0x5d24cb13
+	0xae7c77ef	0xf0213c38	0xd7290320	0xfe3ce627
+	0x9402607f	0x42ebf5c3	0x4b25a536	0x7167f997
+	0xe456ed20	0x5a8ed54c	0x8f774e9c	0xa9f1bf83
+	0x2322ca10	0x3bd6021f	0x2ad0affb	0x0a727ca8
+	0x228cf77f	0x19f54f70	0x2b7cc811	0xa7193b61
+	0xcc097688	0x395a8700	0x073e2b6b	0x8e90c718
+	0x0855f8c6	0x7de3d62b	0x2f582aee	0xeb8667b7
+	0x6a09f600	0x119a656a	0x7502100c	0x36d51cb0
+	0xb398a2fe	0xce1a11fe	0xa75b725b	0xf8d69c5a
+	0x69b6a07f	0x3b5e712b	0x07d647d0	0x80bbe6af
+	0x80cdefb0	0x03ae17e9	0xda7da860	0x39610997
+	0x67afea64	0x2d141230	0xd845efe5	0x346b9c22
+	0xf03d45ce	0xa7f96ffd	0x21bbd7fd	0x035297c4
+	0x27b88b33	0x8ff80f90	0xa41161cc	0xe38a33d1
+	0x3d12c73c	0xc81ca705	0x55bb79a9	0xc80037b2
+	0x2b1b7c7d	0x47ccc91e	0x440370f4	0xb754bfe2
+	0xf9774b91	0xa8d2fa85	0xb7db3a31	0x102a7131
+	0x61a200b0	0xea8bf0f9	0x826ca613	0xd3842856
+	0x27fa5f1b	0xdc6f7aa8	0xc4351ff1	0x13e8d56c
+	0x3b81f6fb	0x444bb6a0	0xb5fadf26	0xf1e0fd81
+	0x5c75fa49	0x1e66f533	0x74f83da7	0x749327f5
+	0x1f41d35d	0xabb10c2c	0x15ff553f	0xbb5ad732
+	0x904b2bde	0x6eb6c5d7	0xc38cef3e	0x5b62a4c7
+	0x4c1d0297	0xeb0d88e3	0xe147c6c8	0x726bde4d
+	0x2cce53ca	0x2e0ad784	0xb5ce9c2e	0x04fa3a1c
+	0x85fdc1ba	0x87a73107	0x3b1a12db	0x84f7c886
+	0xbb9c65d3	0xf319fa80	0x8684ad1a	0x8b675754
+	0xcefe8be8	0x19fb7f42	0x9fbc80de	0xea169c83
+	0x7aeb705a	0xee25f4ee	0x2f51d222	0xe553b558
+	0x3bbc3526	0x9b99ac52	0x97b7fa61	0x997ff0fd
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+	0x5d3240e0	0x951c867b	0x9e695e32	0x998fe6ce
+	0x513ea21d	0xa52e2c8b	0x19e811b9	0xf7b8404f
+	0x9e70972b	0x913a6bba	0x48e10b9a	0x7e011ed3
+	0x734c76f4	0xe1599757	0xaaae937b	0x51100d47
+	0x7d17124e	0x35ecfd95	0x2e953315	0xf5ff688b
+	0xed16901e	0x90428937	0x9e2070af	0xe4ef8897
+	0xc443333f	0xeec2c3ff	0xd194031d	0xff460594
+	0xd1e9cd6a	0xb1d70ef3	0x341500c0	0x9e90b9cb
+	0x469a4773	0x8de2477c	0x117fc666	0x4f9054ff
+	0xc927dbed	0x67c74937	0x3baf30ea	0x40936d14
+	0x0c9ac739	0x041137e0	0x3d059009	0xb7f5421a
+	0xbb0126af	0xce177510	0xf6de21c9	0xb5f3c076
+	0x0f2fff63	0x86eafd85	0x802188eb	0x0f7bbf4d
+	0xcbd9c89e	0xfd9a22f3	0xedd2c250	0x6c58a749
+	0xa14f1a77	0x4d530eee	0xacf5122f	0x5ec73aa7
+	0x6fafb960	0xa183fff7	0x3c70bbe2	0x02633064
+	0xe58b5614	0x1134d39d	0xf8f881d2	0x69d59940
+	0x868185e9	0x9d0890fa	0x7d9bf165	0x5bb8db70
+	0xa8945b39	0xa7d9feef	0x1407353f	0x43d1617e
+	0x120d0afe	0xaac34195	0xa57168df	0xcb961fd5
+	0xc3224007	0xf59e9967	0x8f15d16a	0xa1316dc9
+	0xcb26f47f	0xc527ea60	0x926d3346	0x2c6b68de
+	0x1b3006fb	0xb2756318	0xaca473af	0x272b57cb
+	0xd60d2c46	0x4e95e451	0xa2f394f1	0x683214d2
+	0xb9605bdc	0xa115d6e4	0xa6083a9c	0x68dc3d47
+	0x5a8f50ce	0x169b2488	0x27208e8e	0xe58ad90b
+	0x45d701e8	0x4112922f	0xb9aa2b3f	0xede2202a
+	0xa392f747	0xb4bfa7ad	0xce1fd86f	0x70ef8742
+	0x20953b5b	0x13ebd4ee	0xf595936b	0xc9e8dedd
+	0x9500e2fd	0xb310d9f5	0x85a0bdde	0x61c15820
+	0x1115f8d3	0x8785f7be	0x41c14891	0x7933dfc2
+	0x71d1b4ba	0xa23b8102	0x5faeb285	0x8e57ea62
+	0xcc850793	0xc87939d2	0x59e20f98	0xca1a3b98
+	0x33b06934	0xee5a3331	0xbdd162f3	0xaeef3bbb
+	0x78a32364	0x605fe058	0x46b26fdc	0x12837872
+	0x16099e34	0x085f188c	0xfe5e4cc8	0xd93cd8a1
+	0x6dc59005	0x28316a2e	0x9195e418	0x0e214d25
+	0xfe0e5b53	0x6e9c76fe	0x1dcb3a92	0x9913d086
+	0x645123e4	0xc908a92b	0x4b88bf41	0x2097f641
+	0x80e244b8	0x5e003730	0x5a0f58d3	0x16088761
+	0xd28591cf	0xce0fe936	0x045553a1	0x26c00405
+	0x6e4bf3f0	0x64290de6	0xe9a19aff	0xd87bf684
+	0xed4daf00	0x2810c0db	0x128cfee0	0x1e508c6d
+	0x49467929	0xbbfb2b1d	0xd9c32057	0x6ece8a60
+	0x22e2d5bc	0xd1abc452	0x1d6ad999	0x8a55d752
+	0xbb1d05d3	0xfddd231d	0xd4015973	0x5622ec3b
+	0x09dd64f1	0xa9d70f43	0x68e7297e	0x339d7030
+	0x4e895dff	0xf4670d21	0x0936a426	0xd122a9df
+	0xd216184f	0x387ba4a0	0xc8243d33	0x856697d0
+	0xf6abcaef	0x84d7a4a4	0x4dbee515	0x93c9e8e5
+	0xb29193a6	0x4f1f7d60	0x76155a55	0xdcac3a70
+	0x8bfabc0d	0xf9a3e9f4	0x0394ae0e	0xf6f119cb
+	0xabad1677	0x10acd369	0x978d5da0	0xcf002655
+	0xe82fb631	0x0aa94bc1	0x722d2cd4	0xd719a922
+	0xa757ba81	0x81fbd096	0xf9a551e2	0x76149e2d
+	0x1ddc020a	0xd372ecdb	0xd9638c1a	0xa1e88b8a
+	0x50078c91	0x214850fe	0x25d6b007	0x727de93e
+	0xf03cc409	0x053795dc	0x1ef31bd4	0x2f5c10c9
+	0xfccebcd1	0x44ac9ee9	0x80428302	0x4acef759
+	0xd91b7495	0x31f152e1	0x72ed8eff	0x0085114e
+	0x81bbaf96	0x84ecedff	0xbef7bb0c	0xb5c848db
+	0x23b345ea	0xab388f25	0xd30f937c	0x71f79868
+	0x0f525e32	0xdbfa767b	0xcf0de0b8	0x7af15903
+	0xa11eee62	0x70cf63d5	0x4458af62	0x56d50908
+	0x9da8403f	0x221da3cc	0xbd0aade5	0x183d267e
+	0x3e156120	0x9b509a32	0x3b5ddce8	0xc11669fd
+	0xa917981a	0x7da3cdc8	0x783babe8	0x51bf0088
+	0x9c00c498	0x1e874f17	0x46deb849	0x0fbf988e
+	0xa5446f28	0x7e6f0822	0x6cf41525	0x6c72bffc
+	0x720c723d	0x2b55fe0c	0xf18768ef	0x5aab31f9
+	0x789ced3a	0x96310d66	0xeffc13c8	0xf876eb4b
+	0x3d873163	0x13fc946d	0xe8d8ddf0	0x210b9b69
+	0xfc303435	0xc0445e72	0x0837fd7f	0xbae8ddf1
+	0xc0e9c2bc	0x995280dc	0x46685fda	0xf3af75d4
+	0xe7ded1be	0xdcafd05a	0x206ee6d7	0x8f6033be
+	0x215b79ce	0xed907e16	0x5601af38	0x0973ac88
+	0xd53350d2	0x9d16abdc	0x4d370a82	0x844bd339
+	0xf794dd28	0x92d34b83	0x059613da	0xaad853c0
+	0x0b58b92c	0xe930d280	0x3ae36754	0x49b1d72f
+	0xa886613a	0x88d74d88	0x8f56701d	0xf1e818ee
+	0xb2795931	0x48b661e2	0xa221d210	0x3bb81578
+	0x418b80ff	0x3e86c6b9	0xaed36f80	0x4141343e
+	0xad1ceaa3	0x3329cbdf	0x857da730	0x31d4a9a6
+	0x277c5e78	0xb32c94da	0x674203b0	0x0c449415
+	0x4677ae79	0x25abf896	0xa1091aab	0x2825835b
+	0xe679b6e2	0x205d8da7	0xe4e1aac8	0x95830755
+	0x40e6e4bb	0x610cfbdf	0xca1b1c44	0x3fe7308d
+	0xb3e930fa	0x076bf0d8	0x354e1b7f	0xadf06e4d
+	0x6db0643a	0x36d4bc97	0xeb22d83e	0x3099966f
+	0xac073c10	0xd5e437e5	0xbbb909a3	0x4feb8b83
+	0xedd7f264	0xbdcadef1	0xf3086990	0xece45074
+	0xf952de8d	0x6292598b	0xbc80abbf	0x7393cb7b
+	0xb5a2f4cd	0x1ca8c4c2	0xaf05b117	0x0672793f
+	0xd0d075c0	0x48418531	0x8d011a01	0x15c51e9b
+	0xc51e7e51	0xa974bab5	0x95109a8c	0x06eb3ca1
+	0x87a097f0	0xad14a4d0	0x314191b1	0x5627955e
+	0x458c6134	0xb10f0a92	0x96acaef3	0xd90457f1
+	0x4de019ae	0xeba25c70	0xebe5c14b	0x158d3898
+	0xf0691820	0x161df4bb	0x136e0c58	0x3af86045
+	0x1bc6e724	0x23101c77	0x153431d4	0xd609b2c0
+	0xaa1ae519	0x2be7a14b	0xe7bcc16c	0xc2dc8079
+	0xb49905fb	0xd95e3f33	0xb92e63f4	0xd3cd2c98
+	0x190354d7	0xa62dce06	0xfa600031	0xefc6efd3
+	0x1d3b654c	0xb639ccd0	0x2b7b0983	0x63eae4b9
+	0xd54b0d33	0x08aa5eea	0x99be4902	0xcc1078a1
+	0x1c0c0341	0xc82720e1	0xdcd9417b	0x9fa87ac3
+	0xa77356a3	0x9f35e75e	0xdc6b4248	0x1a146d1b
+	0xa7fbb7d9	0x1e21490a	0x27b91430	0x594975c1
+	0x54d33a1c	0x12096461	0x2427f1f5	0x110d0724
+	0xa72c6e3d	0x6e09f629	0xbcacad98	0x9732276a
+	0x749107e5	0xebf47d70	0x6b6c4c63	0xfb22cb3e
+	0x3684453d	0x3dfc9181	0xc5bbe7eb	0x7d3464f3
+	0x7db3db12	0x69f8d54a	0xc3cb57e9	0xa3a6c364
+	0x5408adfb	0x260f2384	0x5baf6f43	0xd3791026
+	0x2719238f	0x68d4f3cd	0xc67bcdbb	0xb23e47aa
+	0x33c0e8ec	0x8eb2ed26	0xb45d0553	0xa0a51edf
+	0x63d94bbe	0x3b7997e2	0xa8247af2	0x66af60ff
+	0xa5cf96d5	0x357bfd57	0xea573081	0xd953943a
+	0x4b70801a	0x5b18a19c	0x83547b44	0xd1225a31
+	0xaaecdc1d	0xd9bc2dc5	0xdbab4697	0xe837c74b
+	0xf3afdeb4	0xa4ae7b27	0x67f514d5	0x135d8d7f
+	0x718cc961	0x3fa14697	0xd76b4e28	0x7377f49f
+	0x0e1723b2	0xb2b34ca2	0xe5a713af	0xd0f2eef9
+	0xd425d842	0x1bf685de	0xfc688084	0xe01d0db4
+	0x2b33af87	0x523f542e	0x583949fb	0x716d5dcf
+	0xf2b516b2	0xbbb40cb1	0x28a395af	0x416d8047
+	0x3add469e	0x2bdda5d5	0x4a0bab2f	0xbb26bb5a
+	0xa5c4458f	0x87aea38d	0x0d84fbbc	0xc91c5dee
+	0x226d403f	0xa89803b1	0x362f6461	0xd327ccc3
+	0x0d3172fe	0x5ee8f57a	0xed862a4e	0xc9e72fca
+	0xaf37a7bb	0x0e823c62	0xc1f1d185	0x32e22081
+	0x72427d25	0x9492c7ad	0xaed29771	0xdff35edf
+	0xbdef0a5e	0x5d9d2f18	0xa0bc1ee9	0x0c397a65
+	0xc911d530	0x481d294c	0x1a84ce5d	0xf5a5504b
+	0x22cfca7e	0xaff7e8e9	0x0394d9b1	0x7832305b
+	0xf853d344	0x89571b4e	0xd2e2bfdd	0x0c72e467
+	0xb236aea0	0xde6cabce	0xfce515d5	0x0f8c4779
+	0x3c74d971	0x81b0b3e3	0x2d4c4ecc	0xf4da0ae0
+	0xa0947a82	0x47609cd3	0x6f81ad8f	0x2bf75b0c
+	0x46cf40b8	0x344f9edf	0xbad2a5af	0x9e13f884
+	0x205ea013	0xd54fcb5d	0x20a86658	0x739cfb67
+	0x7971ea26	0x7841375b	0x649b81e7	0x31ab0179
+	0xb0730487	0xdba21463	0xa5f6cb07	0xd4f92687
+	0xca5fbcda	0xc8de464e	0xc7263f7b	0xb93678db
+	0x1b3ca8dd	0x4636a901	0xd4a16614	0xf96c26e1
+	0xc58c8da6	0x2965c74a	0x59ff32cd	0x4d77e88e
+	0x23843ad3	0xa85b9246	0xfd2d5bef	0x1257bf58
+	0x9c0aa762	0x9ec8ac35	0x77d9bc0a	0xa2bbdee5
+	0x56d690cf	0x5cdc4461	0x3ef6afed	0xaeb51f80
+	0x492d6fc9	0xfe4df4b1	0xce23606f	0x40eff82d
+	0x715eaa41	0xa4e8b2ad	0x19c3e72f	0x9333d4f2
+	0x9b902cf0	0x70c9bbd4	0x9901f889	0xc342ab6d
+	0xd36492ae	0x38dc739c	0x0928ffce	0x8d724b2b
+	0xd5b29bbc	0xa0ce992d	0x8856178b	0x026948bf
+	0x08809e04	0x541c960d	0x210b71e0	0xf1b9e474
+	0x85bca8cc	0x90ce42b7	0x6682b7d8	0xe0c50c48
+	0x25a8075e	0x33dc1ab1	0xf0ff1627	0x89d6d8e9
+	0x4790ebbb	0x7ba5cfb5	0xe97327bb	0xb06fa0d6
+	0x7db34b48	0xdf96d115	0xce3fb871	0x03b1557c
+	0x7eb6d43c	0xceaf3826	0x247e0851	0x840637d2
+	0x9f979955	0x08f67a6a	0x525d8295	0xdee447c9
+	0x91ed75bc	0xe4960419	0xb9700051	0x0344b46e
+	0xbd6b6827	0xa38ab219	0x817e8ba0	0xe86dd20f
+	0xb9240181	0x4765dd8c	0xc59d8325	0x9b8cfb61
+	0x6632d86e	0xaf8c2a11	0xbc47dcfb	0x26544374
+	0xe2beca9d	0xf6355863	0x4291bd11	0x94489a1c
+	0xc52476f9	0x05fb6fda	0x4d315edb	0xa8e285d0
+	0x0cd624e3	0x599b9d80	0xd21d8746	0x4d9f3528
+	0x3a634276	0x9a1f1481	0xa5a015ee	0x6639f7bd
+	0xd5d20e14	0xe90d52f1	0x3318a40d	0xf3f4f5db
+	0xb92a7eb5	0x2d730844	0x8282ae9d	0x2f369ced
+	0x5355d63d	0x984d651b	0x47041c38	0xd65d225b
+	0xfc2c77a5	0x8822efe6	0x49087974	0xff3c04f0
+	0xcba80501	0x7e6e1c68	0xa7b7421d	0x6b906771
+	0x4b2b3b5e	0x233421e5	0x78d0d0d8	0x222dad37
+	0x875b564f	0x336662fa	0x2bfae345	0x47ff9f91
+	0xb3e7beee	0x3a7ae071	0x3bd0f29e	0xaee9af97
+	0x6f0d58fd	0xb5147803	0x32a6ea49	0x70a0a245
+	0x25b0ace0	0x281e4418	0xfcb5553f	0x1151518f
+	0x50e67760	0x068c8b22	0xbed7234a	0x4120c5d6
+	0xec22b6d5	0xc600bef1	0xfd9bd4a2	0xa29451b6
+	0xcd51bac2	0xc1bd0e26	0xe8432d25	0x2deb06a0
+	0x9ae54a7a	0x536799e4	0xef4fab62	0x4c9f3e5d
+	0xeda219fb	0x5947eebd	0x2dec73ae	0x11da15cf
+	0x94ddc24c	0x2c28b710	0xa5c3620c	0x0722dd36
+	0xedd98464	0xafa8e23c	0xfd750c04	0x829dc6d6
+	0x6ee56697	0x2cf2380f	0x3cfa8cd6	0xfa42971f
+	0x415ad936	0x0b1fea9a	0x65c8b5d2	0x1a5828a6
+	0x4295092a	0x54596d12	0xa419acef	0xefeddbf9
+	0xcabda915	0x053abb3c	0xe4b38d10	0x141d9ebc
+	0xcceb3e75	0xa4fdd9cf	0x9450f718	0xe2a7e7e0
+	0xbf98f6a0	0x4885a7d5	0x53f871b3	0x0a57e4cf
+	0x22b36b98	0xd705d611	0x12db0f11	0x546186e1
+	0x2629257f	0x74587452	0x2659526c	0x2913ca70
+	0xb3d5b27e	0x1040c827	0x18a192d1	0x2731ba8a
+	0x5865a15d	0x12b9dce7	0xd0b05fea	0xe35d2de2
+	0x0f1fc309	0x28df230d	0xcac0338a	0x724f0b25
+	0x0a36bfeb	0x4c196443	0x392068ee	0x8cc1a2d9
+	0xbc4f0871	0xea33986e	0x22e90aa1	0x2a43d9e3
+	0x81214348	0x3745f469	0xaed24012	0x092a728f
+	0x6b5bb659	0xb46d810d	0xc146cfa5	0xdd3e6954
+	0x20d6283c	0x0a47baee	0x45aa3873	0xe2c0795b
+	0xf1cb3519	0x566f951f	0x5e34314d	0xab31c4f1
+	0x10e0b305	0xfa7d0a3c	0x9adc26fc	0x55fc8af5
+	0x90314c7d	0xa54954f9	0x27cc0f21	0xbe30da42
+	0xa04432b0	0x670e176c	0x904a4df4	0x4342618d
+	0x8b43d3f8	0x086fbc28	0x54954d7a	0x73502d23
+	0x2ebbaa2e	0x2549f553	0x06946ef5	0x61b621d4
+	0xafde5d4c	0xbc0faabe	0x0e110c04	0x44ddda52
+	0xad3883ba	0x1464c595	0x3c5d9f28	0x95573165
+	0x3e92db93	0x41f19b03	0xb60a4c71	0xf519a623
+	0x5dc2b562	0xa822e25d	0x09ba6793	0x5e3f5958
+	0xb80ae32a	0x3f2a8120	0x50cab916	0x8a2664c7
+	0xe9a0730e	0x74ef9c02	0xbe1b891b	0x8cdeb1cb
+	0x8f05f87e	0xf4ebaee8	0x12fab9dd	0xfbc8ab3c
+	0xe6d443b8	0xbaaf9253	0xa4b28356	0x3a105c02
+	0xb3ceb634	0x26c2d231	0x1e509d45	0xb010dc16
+	0xbaed93e6	0xffd995a5	0x2274c579	0x081c20f5
+	0x0e890545	0x9bf20a67	0x534d1668	0xbe0d8a9e
+	0xe6a3b6a6	0xa19826e8	0x8c369600	0x9b00d171
+	0xdec22ff7	0x0de50b44	0x4ca2d735	0xe9142307
+	0xb2d75e8f	0x74018651	0x8a93b3dc	0x679f8926
+	0xf216f6dc	0xaebc58e5	0x820b6760	0x6e49feb6
+	0x3ad58a8f	0x62ab576e	0x31829e46	0xb1a2bd35
+	0xd3db9735	0x248c8e9a	0x8db52fa6	0x8b65b2de
+	0xebfee08e	0x0d2bdaa1	0xb3d9a282	0xde361f30
+	0xc121c45c	0x12cdcb27	0x8d7ab875	0xcefac8dc
+	0x573f8424	0x783fb263	0xbc2d8f2f	0x04f05791
+	0xa880912a	0x22042163	0xb7891d1d	0x27a3b82a
+	0x70e35ee9	0xb0b74dc8	0x72b51ef4	0xc074941c
+	0xeb765569	0x8fba1f5b	0x044aaefa	0xc0db48d0
+	0x31bed72a	0x7f5ad220	0x132e1da0	0x4cc7e7b5
+	0x145a80c6	0x39367173	0x0689d163	0x96822f9a
+	>;
diff --git a/arch/x86/dts/microcode/m12306a8_00000010.dtsi b/arch/x86/dts/microcode/m12306a8_00000010.dtsi
new file mode 100644
index 0000000..0672ff1
--- /dev/null
+++ b/arch/x86/dts/microcode/m12306a8_00000010.dtsi
@@ -0,0 +1,682 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ *   list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ *   be used to endorse or promote products derived from this software without
+ *   specific prior written permission.
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *   THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x10>;
+intel,date-code = <0x2202012>;
+intel,processor-signature = <0x306a8>;
+intel,checksum = <0xe44a4ef2>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x10000000	0x12202002	0xa8060300
+	0xf24e4ae4	0x01000000	0x12000000	0xd0270000
+	0x00280000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x10000000
+	0x00000000	0x00000000	0x17021220	0xe1090000
+	0x01000000	0xa8060300	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x493d401b	0x64106cf1	0x0ffc7f0f	0x9b4b97f6
+	0xb8fab9c2	0x46353316	0x0247d91b	0x3c36c361
+	0xdb01345a	0xceecca42	0x5ee7d8b4	0x24afdbe6
+	0x5fb36178	0xbc17d76b	0x31b7b923	0xc81aec82
+	0x647b3320	0xf1db9653	0xff3b9759	0xe9c74b72
+	0x3b193752	0xc147860b	0x160e0d6a	0x5bdb9dbf
+	0x1ccce2ac	0x387670ad	0x2f106f05	0xf8607ea3
+	0x42562576	0x30e086fb	0x409a06b8	0xf1957736
+	0x5eb03f65	0xad147fab	0xe1a8e8b6	0x208d59d2
+	0x683fba2e	0xf172b378	0xf8138dba	0x61e81d1f
+	0xd551f997	0x28c79780	0x04f9db27	0xa80679b9
+	0xaca4e7ff	0x6876944b	0x26d7dbc1	0x77f7dc2a
+	0xf0bcb163	0x1b2a8e81	0x7b90aa49	0x8d5eaf2f
+	0x522384ae	0xae7f7082	0x412ba10a	0x1ce1baa0
+	0x478c29b4	0x9c09b4d2	0xf225f64f	0xd43026cd
+	0x81098579	0x7df5db05	0xa5815bb0	0xc73ee756
+	0x9738cb95	0xa5bd62e2	0x88e2c6b2	0x778e7fcb
+	0xd3bdb872	0x9404403f	0x5be6ad63	0x71dc4abc
+	0x11000000	0xe5ffd18e	0x9c10c032	0xef097758
+	0x5b44fb3b	0xabbc6973	0xb040312f	0x6267ab0a
+	0x35ef3655	0x694c0da7	0x6eaf94db	0x293feb5f
+	0x225a62bf	0x550edd27	0x8e4da670	0x9afcd29b
+	0x62ad52f1	0xddcdc6fb	0x059e156b	0x9472a491
+	0x20d8e6fb	0x7041822d	0x5af9c518	0x7e6c342f
+	0xb113a311	0xdec46650	0x91c8a91c	0x157cde4d
+	0xec563d5d	0x92470d0e	0x373c488c	0xf18a8f84
+	0x757fa8ad	0xf8959ce7	0x95e1e3c9	0x47347f30
+	0xfbd6e4a3	0x18c2f2e2	0xb6c6eb68	0xd2a81838
+	0xa44964bb	0x36893d55	0x0b411d47	0x5addcf15
+	0x47584269	0x972c08b3	0x0935b300	0xec7d36a7
+	0x1c373823	0x487626be	0xacfecd64	0x6688c83c
+	0xb96f01f9	0x2b6c9719	0x97e955da	0xc4f3b25a
+	0xfcf12050	0x961bc5be	0x53ebb1e4	0xdc7deaa3
+	0x3b86819a	0x7c498a21	0x129bc1b6	0x2aa5c324
+	0x6fb58020	0x0c8e24a8	0xb7c1f0cf	0x37287581
+	0xf417e311	0x5fd7b8cb	0xe615c56a	0x6a6c6aa7
+	0x46c97d63	0xcc71adee	0x239b7483	0xea6750f7
+	0x17bae7c2	0xbf4de5e1	0x6c37a1e0	0x314fc762
+	0x68bffc94	0x4069875c	0x60d3a593	0x3a923495
+	0x70f7a899	0xc959db6f	0xfd440374	0x0be4f668
+	0xc15b74e9	0x9eb15fc7	0x04dc5939	0x1c2d0faf
+	0x8ca378c9	0x15aaae90	0x2c53e471	0x2ada3977
+	0x750d6d3b	0xd3e27cdd	0xf63ece4c	0xcbbf9463
+	0xf0b26aad	0xacc9dc7e	0xcb2131eb	0xc2da14bc
+	0x01b57719	0x901319e9	0x86b16d25	0x89fe5e27
+	0xfa3135cd	0x51ebcf8e	0x91b36807	0x6efb87a1
+	0xbe05489f	0x0461f6c7	0x4f1ddb59	0x007a7e35
+	0xdde5c360	0xf137a520	0x153d9512	0xebe49940
+	0xb81727b3	0xdff04ada	0x504811d5	0x6192a2a1
+	0x418ad287	0x44278f0f	0xc8d70fcc	0x5d5953ca
+	0xeca4ae03	0xb507f886	0x90a6726b	0xec2c60b6
+	0xfe003923	0x8cd52bb2	0x87397bbb	0xec98c514
+	0x28501352	0xd5518d70	0xf3258a19	0x15e4e0f4
+	0xae272618	0x164ece6f	0x19b5449c	0x2717cf2a
+	0xffee98cf	0xf18d6c04	0xffb6f744	0x5ed2cb50
+	0x9421a65a	0x76150be7	0x9689d9eb	0xe6ce395b
+	0xa5857737	0xe51b5a0f	0x5cc95766	0x365a6f04
+	0xee8a6d1b	0x219da3e7	0x81004946	0xce4f00f9
+	0x852eebd0	0x3a39b164	0x96863ddd	0x43b46d69
+	0x064e138b	0x2ac312a3	0xe7eac082	0xb958803f
+	0x3138940e	0x4c1d5d99	0x49e9ed02	0xeb3a904e
+	0x14c2ce82	0x8449493e	0x3cdd6dbf	0xdddb592e
+	0xaae39fca	0x163c6e65	0xee5a0e52	0xae8c2f8c
+	0x07fd1416	0x406bd0dc	0x52811c06	0x18316363
+	0xf954d2eb	0xa8ec83dc	0xe24996e9	0xc92af45f
+	0x5a73f1d0	0xf5b9948f	0xa6960f5f	0xef3d1266
+	0x97ac2b43	0x20ce72fe	0x0d774f96	0x29653967
+	0xca765fe6	0x470ded7f	0x42a9b87e	0x3c9cfb36
+	0xcd9354db	0x0f2fa889	0xb35e5c71	0xc3da1e0d
+	0x85f9bfd0	0x1afc94a1	0xf05524d4	0x2b2138ef
+	0x3c77b905	0x55d26a06	0xcc3a045d	0xad05a556
+	0xef80f5b7	0x3ca6e8de	0xc40df9e4	0xdc5bdd8a
+	0xdee9349d	0x258ecbc9	0xa29faf0e	0xf41daab4
+	0x47af938b	0x6a6a1cf1	0x7a3d2f4a	0x11ede796
+	0x61f25722	0x6864a35e	0xb4d96fae	0xcdc6a722
+	0xce64615d	0xef56b252	0x0b89020b	0x2a1ac24c
+	0x582c3283	0x124f274e	0xf6a58fdc	0x847c262d
+	0x31517f9b	0x8cd34984	0xc60f7204	0xa94875c1
+	0x12abf4e6	0xfbdd2b29	0xdb51a1c1	0xb10f9ec9
+	0xc52b5d3c	0xfa5f75c4	0xb63c6fef	0x8ccd4fe0
+	0x74b6cc11	0x013babd9	0x0bc30209	0xb1597dcf
+	0xbda5ac76	0x0371d13a	0x67252505	0xf3081369
+	0x0d7a4e53	0x25f89a9f	0xd0d9e53f	0xa25d897d
+	0x822f83e0	0x3008eae6	0x428d3320	0x9890d235
+	0xfec38910	0x56c87e21	0x7f7f594b	0xdf46866a
+	0x34a34b40	0x0987267e	0xb47033d1	0x331f5d40
+	0x935a4ec5	0xab480f95	0x1803d8e7	0x00e2e693
+	0xab18b053	0x1cf706dd	0x7dda5849	0xb422e2e3
+	0xba5fd0f3	0x3aee2ce1	0x33b21147	0x5fdec0d7
+	0xd509d289	0x61187bf4	0xf7687684	0x48edbc90
+	0x519dcd0b	0x77f026eb	0xc52eb470	0x1d4dd497
+	0x2fa69c9c	0x8fcfef0d	0x1ed8a0b3	0x9312d199
+	0x596b55be	0xc8c68e56	0x6aa8dc28	0x3100ec70
+	0x737bfff7	0x40e51f14	0x695baf1f	0xad786740
+	0x6278b108	0xcd066fb0	0x74f9d22c	0x9dd7d6f6
+	0xc9d8d081	0xb82f32ae	0x797beeed	0xa34ce8dd
+	0xd57ad56e	0xa4bec19f	0xe2cc7268	0xd2b85f64
+	0x4faf835d	0xda6f3933	0x28397cd3	0x010b5a17
+	0x6d904bfb	0x26fc2b26	0xdc7b440c	0x4e985f16
+	0x92fb8abe	0xab8d7b77	0xb906004f	0xb0bdac98
+	0xee64230b	0xe768ebf6	0x3c96a534	0x4e2aa084
+	0x5f4c5c4a	0x7bff964e	0x4b4fdde3	0xfc36550b
+	0xe90220be	0x0056c3d4	0x65599751	0x00c71265
+	0x83011ea4	0x5bd8113f	0x616bc4ab	0xcdbbfdab
+	0x187abde6	0xcb0b2059	0x24244c94	0xa05cac8b
+	0x15e0e4eb	0xe93d7e1e	0xd4016e08	0x8144e1e9
+	0x1c256625	0x841f4379	0x782edb54	0x6a70674d
+	0x5de874f9	0x075b423b	0x71a8adc4	0x3f7c5ed1
+	0xc045ffb0	0xd94e8bbf	0xf7ff3edc	0xb1d3aab5
+	0x7e78f4b5	0x2e9f0c64	0x17efe45a	0x2a2dd14b
+	0x9eda4e59	0x2c3689c7	0xe15e5efc	0xf4f11a2f
+	0x0edb0000	0xf7afa169	0x05558b03	0x1ed6aa69
+	0x8174d362	0x922814cc	0xcfb1c31c	0xe7cbaba6
+	0x6aa77d7a	0xea48a37b	0x23b7a2af	0xc2b602da
+	0x03076aeb	0xef659eb5	0x3c2833e6	0x7dd8521b
+	0xe80a8ff3	0xe3af24d2	0x6d15f067	0x1c05b90b
+	0x306e10ea	0xd45b1a99	0xc65a85ac	0xb4ddda13
+	0x1f2b0bbe	0x716421c1	0x33c2f599	0x0deba688
+	0xa44de1c2	0x1d33833e	0x3d454600	0x07cdb855
+	0x57b42914	0x2b3015d8	0xf7893119	0xa754aa11
+	0xfc8bab1c	0x6aabb3ff	0xeb9a35ba	0x9433e224
+	0x88225f56	0xb3376d46	0x9203225d	0xfdd591f8
+	0xb4452f63	0xeccbcf9c	0x60d07a28	0x021f7b69
+	0xc355e1f5	0xdabc3f4b	0x3a3925e8	0xffc15e96
+	0xd37cf717	0xbd580830	0x9527f96c	0x91b1119b
+	0x527baf62	0xdcd8cb14	0xceff6ef8	0x7a64b27d
+	0xc2bced42	0x62693867	0x171d7869	0x82a502af
+	0x98c84c3e	0x8a0dd77e	0xcb01c7bb	0x91373992
+	0xd28e7281	0x487d2036	0x1e98d48c	0x60f56b74
+	0x3199129d	0xab6205ca	0x95c811b6	0xce78fbbb
+	0x92f0b76a	0x2a448276	0x975d891a	0x5c945417
+	0xc2ff2603	0x045c8a04	0xc8b41e0c	0x461623d6
+	0x640bb5bd	0x386feb24	0x5ecc0bdc	0x1c56fd05
+	0x3c6b32a1	0xde2d2b8a	0x1f76b23e	0xc78c9108
+	0x5febf899	0x3c55d772	0x226aa903	0x4916231d
+	0x44928c52	0x7dfe932a	0xb4420968	0x1997faaa
+	0xb9a3dab1	0x5bec5d70	0xcb5dba0d	0xcc4052bb
+	0xfc26b557	0xf04a044a	0x83ad1b1b	0x781935b0
+	0xd3fe7102	0x210b7f15	0x0002e47f	0x95709de3
+	0x7ccbab76	0x701f28b1	0xc2151880	0xb88778eb
+	0x33bfeeb0	0x1498b52f	0x2694b5bb	0x85332e53
+	0x103b6ddf	0xb410d999	0x3687d2fe	0x92fdecd7
+	0x6c7d4179	0x89a2fc40	0xc8a2a4b0	0xc140a6a6
+	0x36b20598	0x3c6e05b6	0x2d67b87b	0xc09b651c
+	0x2cd528f0	0x2e2f38b7	0xee7fa2fb	0x84075fca
+	0x98bacf32	0x2b965415	0xd019df29	0x83a5e980
+	0xde8322b6	0xf592ef9d	0x22be4a4b	0x5568e883
+	0xaf95393b	0x43b2f828	0xe44f0894	0x0c17a91a
+	0x46271d4c	0x3ea308ba	0x757ab95f	0xeb841efb
+	0x86def448	0x806b7e0a	0x704125ce	0xb103138d
+	0xc70bdc0f	0x9b020964	0x8d5326c3	0x22265cf1
+	0x07e9158e	0x1b77f0e7	0xc4249a77	0x0ec99717
+	0x91f9860f	0xa22527bf	0x1c351901	0x8dd07723
+	0x1b10062a	0x75db2a1b	0x300f48c7	0xe2b47dc5
+	0xf9be873e	0xeb78cba6	0x48a02062	0xe57a4d34
+	0x8d6d6093	0x0f3748af	0xea0fd86a	0xbb57cac5
+	0x1aae31a2	0xc68f6732	0xfe6d09a2	0xa8ec7655
+	0x15fb82e4	0x0fd62a02	0xde712cc6	0xa6983f8d
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+	0xca8fc8b1	0x87cc7eb0	0xaad2814b	0x53736976
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+	0x6833ad36	0xa0ac765a	0x479ac6b6	0x3297deb0
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+	0x5ac8cfcc	0x8b6f0821	0x85743e1c	0xf84b5389
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+	0xb67017a6	0xd3234e88	0x279d5ca4	0x3f63ba99
+	0x21622bbf	0x07caf2eb	0x8b7076ab	0x8e4ebcbd
+	0xd10a0bfb	0xf55952f9	0xf488837a	0x8ffae6fb
+	0x71d76515	0x44fb3730	0x7a7c61b7	0x1bd1e2de
+	0x8a92eaaf	0xb21e7751	0xb28522e5	0xedd3b173
+	0x03882afd	0xfab1fd71	0xf5b8d389	0x0073ba5b
+	0x83c4bdde	0x0ae4303c	0x445ca8b9	0x6b757b77
+	0xfeb103e9	0xccd485bc	0x0ad310c2	0xe2192e5c
+	0x4dec1c82	0xee1986b7	0x352a80c8	0xa8151575
+	0x6fe0d28f	0x771c3d8f	0x871e87e1	0xdacebc59
+	0xe8ca49f6	0xb926a028	0xa6b3e515	0xefa223a5
+	0x8a54e354	0x897e5a4d	0x21b8224d	0xd416f2ec
+	0xcbe7f0bd	0xb2447fea	0x9e793f69	0x0fef54ad
+	0xe8b59733	0xcf1f604a	0xb6fcca90	0x828ab637
+	0x544d1f6a	0xd3f9bb08	0xd33e5002	0xf2bb0902
+	0xbacb7493	0x8f49ee50	0xc8b026fd	0x548c5f6a
+	0xa69ac56c	0x3048c9fe	0x2f4099be	0x5e2db858
+	0x86af0440	0x63ad790c	0x2f21596a	0xa678770e
+	0x6d35026b	0x60e5ffd7	0xd8c5ee84	0x0e8f4a5f
+	0xb32368ab	0x06ce6d77	0xaff9a8a7	0x9b7bfe08
+	0xf1c41bd9	0x5d97e65a	0xae3185d0	0x04a81ce0
+	0x515afaf2	0xcc0bed19	0x7fa0ed19	0x29d747da
+	0xb3be6d42	0xaea891fc	0x596327f6	0x169685d7
+	0xaec527c3	0x58d7f4a5	0x1ec8f0fb	0x5121ab73
+	0x77482d34	0xb9374023	0x593f2fb7	0x806bd03c
+	0x0c3d2df9	0x48db6a6a	0x8d4e3bf0	0xf7c0b614
+	0x4277692e	0x8bd2a7e8	0x2ced9478	0xd6d0958f
+	0x1f11c590	0x64eea64e	0xfd0d9181	0xfe337731
+	0xf2e4d68b	0x5f5c5e22	0xba1be116	0x01947bd2
+	0x6e6f5cf0	0x99ed610b	0x1c9c6591	0xb5b9e932
+	0x1881f045	0x4a07d22c	0x2534671a	0xf98db0e6
+	0x3eecedcc	0x03d88a38	0x473f8803	0x0e964e29
+	0xe7865109	0x067ce3a2	0xb67ea547	0xc9478d11
+	0x77824680	0xe44e870b	0x26409f76	0xf56325e4
+	0x83850a25	0x5778bde0	0xeccc9cbe	0x2b2a510c
+	0x00fb4fe5	0xb1e44d88	0x25017b6f	0x6a07d28a
+	0xc63259df	0x6138534e	0xb365098e	0x9063c5e5
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+	0xad955974	0x5ddaf59f	0xb444e3c3	0x48c0da41
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+	0xad0eaf72	0x9fb4dc0e	0xba8dec9f	0x92ebb8b1
+	0x17cfb953	0xbd1aa608	0xa7488be0	0x07020299
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+	0x8303a6d3	0xc6f8ba69	0xdd78d4ef	0x98b195af
+	0x50f92a15	0x2066c503	0x61281597	0x5d0197b7
+	0x59e6f0be	0x02423dd6	0x9b4d27af	0xb2a0755d
+	0x72f2eb4e	0xdb5aa819	0xddb42e82	0x9688712a
+	0xb430e384	0x6484e439	0x44f68d17	0x195c6382
+	0xddee2db1	0xd9af2e18	0x7fbd30d6	0x2ac223db
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+	0x9c233021	0xc074a29c	0xe7b8f28f	0xd0adf47f
+	0x23cdf70d	0x6795e85d	0x1168d6ea	0x3c8bb4c7
+	0xad1d00c9	0xf3eeb5d0	0x2f950982	0x9fbbde57
+	0xdc733a93	0xb23e2beb	0x7dbb34af	0xf1323cff
+	0xf6c9a9bc	0xf69900a6	0x9447ab0b	0xf03e55fa
+	0x2816479b	0x487e507e	0x494087fb	0x0601d1ef
+	0x27c86510	0x6a14691a	0xb78886de	0xe89e8c84
+	0xf2cd073c	0x09144b70	0xa82227a5	0x82f88828
+	0x71f7e10a	0x6c2b46b6	0xf813fe7d	0xf76d2602
+	0x044d5543	0x9e1b6a76	0x967ad7b5	0xe803b0a7
+	0x01e03dd9	0x6d5c94d8	0x112357c8	0x8e0bfe12
+	0xcc8c7461	0xfbc1c562	0x9838886c	0xa16c46a7
+	0x020631ad	0x70fb29ff	0x5f5f1795	0x07a762e8
+	0x3467aa2b	0xd396d1d7	0xa12aaf4c	0xd3c13b6b
+	0xf158d7dd	0x17b1317a	0xd847a91d	0x7612ab8e
+	>;
-- 
1.8.2.1

^ permalink raw reply related	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver
  2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
                   ` (3 preceding siblings ...)
  2015-12-11 10:55 ` [U-Boot] [PATCH 04/10] x86: ivybridge: Add microcode blobs for all the steppings Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
  2015-12-19  2:52   ` Simon Glass
  2015-12-11 10:55 ` [U-Boot] [PATCH 06/10] x86: ivybridge: Do not require HAVE_INTEL_ME Bin Meng
                   ` (4 subsequent siblings)
  9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
  To: u-boot

The SMSC SIO1007 superio chipset integrates two ns16550 compatible
serial ports for legacy applications, 16 GPIO pins and some other
functionalities like power management.

This adds a simple driver to enable serial port and handle GPIO.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 drivers/misc/Makefile       |   1 +
 drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++
 include/smsc_sio1007.h      | 115 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 242 insertions(+)
 create mode 100644 drivers/misc/smsc_sio1007.c
 create mode 100644 include/smsc_sio1007.h

diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index aa137f5..6952f8ce 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C
 obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
 endif
 obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
+obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
 obj-$(CONFIG_STATUS_LED) += status_led.o
 obj-$(CONFIG_SANDBOX) += swap_case.o
 obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c
new file mode 100644
index 0000000..79e9e15
--- /dev/null
+++ b/drivers/misc/smsc_sio1007.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <smsc_sio1007.h>
+
+static inline u8 sio1007_read(int port, int reg)
+{
+	outb(reg, port);
+
+	return inb(port + 1);
+}
+
+static inline void sio1007_write(int port, int reg, int val)
+{
+	outb(reg, port);
+	outb(val, port + 1);
+}
+
+static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set)
+{
+	sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);
+}
+
+void sio1007_enable_serial(int port, int num, int iobase, int irq)
+{
+	if (num < 0 || num > SIO1007_UART_NUM)
+		return;
+
+	/* enter configuration state */
+	outb(0x55, port);
+
+	/* power on serial port and set up its i/o base & irq */
+	if (!num) {
+		sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);
+		sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);
+		sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);
+	} else {
+		sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);
+		sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);
+		sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);
+	}
+
+	/* exit configuration state */
+	outb(0xaa, port);
+}
+
+void sio1007_enable_runtime(int port, int iobase)
+{
+	/* enter configuration state */
+	outb(0x55, port);
+
+	/* set i/o base for the runtime register block */
+	sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);
+	sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);
+	/* turn on address decoding for this block */
+	sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);
+
+	/* exit configuration state */
+	outb(0xaa, port);
+}
+
+void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type)
+{
+	int reg = GPIO0_DIR;
+
+	if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
+		return;
+	if (gpio >= GPIO_NUM_PER_GROUP) {
+		reg = GPIO1_DIR;
+		gpio -= GPIO_NUM_PER_GROUP;
+	}
+
+	/* enter configuration state */
+	outb(0x55, port);
+
+	/* set gpio pin direction, polority and type */
+	sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);
+	sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);
+	sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);
+
+	/* exit configuration state */
+	outb(0xaa, port);
+}
+
+int sio1007_gpio_get_value(int port, int gpio)
+{
+	int reg = GPIO0_DATA;
+	int val;
+
+	if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
+		return -EINVAL;
+	if (gpio >= GPIO_NUM_PER_GROUP) {
+		reg = GPIO1_DATA;
+		gpio -= GPIO_NUM_PER_GROUP;
+	}
+
+	val = inb(port + reg);
+	if (val & (1 << gpio))
+		return 1;
+	else
+		return 0;
+}
+
+void sio1007_gpio_set_value(int port, int gpio, int val)
+{
+	int reg = GPIO0_DATA;
+	u8 data;
+
+	if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
+		return;
+	if (gpio >= GPIO_NUM_PER_GROUP) {
+		reg = GPIO1_DATA;
+		gpio -= GPIO_NUM_PER_GROUP;
+	}
+
+	data = inb(port + reg);
+	data &= ~(1 << gpio);
+	data |= (val << gpio);
+	outb(data, port + reg);
+}
diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h
new file mode 100644
index 0000000..eff57a7
--- /dev/null
+++ b/include/smsc_sio1007.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SMSC_SIO1007_H_
+#define _SMSC_SIO1007_H_
+
+/*
+ * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
+ * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
+ * SYSOPT0 and SYSOPT1 determines one of the following addresses.
+ */
+#define SIO1007_IOPORT0		0x002e
+#define SIO1007_IOPORT1		0x004e
+#define SIO1007_IOPORT2		0x162e
+#define SIO1007_IOPORT3		0x164e
+
+/* SIO1007 registers */
+
+#define DEV_POWER_CTRL		0x02
+#define UART1_POWER_ON		(1 << 3)
+#define UART2_POWER_ON		(1 << 7)
+
+#define UART1_IOBASE		0x24
+#define UART2_IOBASE		0x25
+#define UART_IRQ		0x28
+
+#define RTR_IOBASE_HIGH		0x21
+#define RTR_IOBASE_LOW		0x30
+
+#define GPIO0_DIR		0x31
+#define GPIO1_DIR		0x35
+#define GPIO_DIR_INPUT		0
+#define GPIO_DIR_OUTPUT		1
+
+#define GPIO0_POL		0x32
+#define GPIO1_POL		0x36
+#define GPIO_POL_NO_INVERT	0
+#define GPIO_POL_INVERT		1
+
+#define GPIO0_TYPE		0x33
+#define GPIO1_TYPE		0x37
+#define GPIO_TYPE_PUSH_PULL	0
+#define GPIO_TYPE_OPEN_DRAIN	1
+
+#define DEV_ACTIVATE		0x3a
+#define RTR_EN			(1 << 1)
+
+/* Runtime register offset */
+
+#define GPIO0_DATA		0xc
+#define GPIO1_DATA		0xe
+
+/* Number of serial ports supported */
+#define SIO1007_UART_NUM	2
+
+/* Number of gpio pins supported */
+#define GPIO_NUM_PER_GROUP	8
+#define GPIO_GROUP_NUM		2
+#define SIO1007_GPIO_NUM	(GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
+
+/**
+ * Configure the I/O port address of the specified serial device and
+ * enable the serial device.
+ *
+ * @port:	SIO1007 I/O port address
+ * @num:	serial device number (0 or 1)
+ * @iobase:	processor I/O port address to assign to this serial device
+ * @irq:	processor IRQ number to assign to this serial device
+ */
+void sio1007_enable_serial(int port, int num, int iobase, int irq);
+
+/**
+ * Configure the I/O port address of the runtime register block and
+ * enable the address decoding.
+ *
+ * @port:	SIO1007 I/O port address
+ * @iobase:	processor I/O port address to assign to the runtime registers
+ */
+void sio1007_enable_runtime(int port, int iobase);
+
+/**
+ * Configure the direction/polority/type of a specified GPIO pin
+ *
+ * @port:	SIO1007 I/O port address
+ * @gpio:	GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
+ * @dir:	GPIO_DIR_INPUT or GPIO_DIR_OUTPUT
+ * @pol:	GPIO_POL_NO_INVERT or GPIO_POL_INVERT
+ * @type:	GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN
+ */
+void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type);
+
+/**
+ * Get a GPIO pin value.
+ * This will work whether the GPIO is an input or an output.
+ *
+ * @port:	runtime register block I/O port address
+ * @gpio:	GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
+ * @return:	0 if low, 1 if high, -EINVAL if gpio number is invalid
+ */
+int sio1007_gpio_get_value(int port, int gpio);
+
+/**
+ * Set a GPIO pin value.
+ * This will only work when the GPIO is configured as an output.
+ *
+ * @port:	runtime register block I/O port address
+ * @gpio:	GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
+ * @val:	0 if low, 1 if high
+ */
+void sio1007_gpio_set_value(int port, int gpio, int val);
+
+#endif /* _SMSC_SIO1007_H_ */
-- 
1.8.2.1

^ permalink raw reply related	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 06/10] x86: ivybridge: Do not require HAVE_INTEL_ME
  2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
                   ` (4 preceding siblings ...)
  2015-12-11 10:55 ` [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
  2015-12-19  2:52   ` Simon Glass
  2015-12-11 10:55 ` [U-Boot] [PATCH 07/10] x86: fsp: Make sure HOB list is not overwritten by U-Boot Bin Meng
                   ` (3 subsequent siblings)
  9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
  To: u-boot

Do not set HAVE_INTEL_ME by default as for some cases Intel ME
firmware even does not reside on the same SPI flash as U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/ivybridge/Kconfig         | 1 -
 board/google/chromebook_link/Kconfig   | 1 +
 board/google/chromebox_panther/Kconfig | 1 +
 3 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index 36b74c2..b9f290a 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -48,7 +48,6 @@ config DCACHE_RAM_MRC_VAR_SIZE
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select SMM_TSEG
-	select HAVE_INTEL_ME
 	select X86_RAMTEST
 
 config SMM_TSEG_SIZE
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
index 6b13939..fa12f33 100644
--- a/board/google/chromebook_link/Kconfig
+++ b/board/google/chromebook_link/Kconfig
@@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select X86_RESET_VECTOR
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
+	select HAVE_INTEL_ME
 	select BOARD_ROMSIZE_KB_8192
 
 config PCIE_ECAM_BASE
diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig
index ae96d23..2af3aa9 100644
--- a/board/google/chromebox_panther/Kconfig
+++ b/board/google/chromebox_panther/Kconfig
@@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select X86_RESET_VECTOR
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
+	select HAVE_INTEL_ME
 	select BOARD_ROMSIZE_KB_8192
 
 config SYS_CAR_ADDR
-- 
1.8.2.1

^ permalink raw reply related	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 07/10] x86: fsp: Make sure HOB list is not overwritten by U-Boot
  2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
                   ` (5 preceding siblings ...)
  2015-12-11 10:55 ` [U-Boot] [PATCH 06/10] x86: ivybridge: Do not require HAVE_INTEL_ME Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
  2015-12-19  2:52   ` Simon Glass
  2015-12-11 10:55 ` [U-Boot] [PATCH 08/10] x86: fsp: Always use hex numbers in the hob command output Bin Meng
                   ` (2 subsequent siblings)
  9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
  To: u-boot

Intel IvyBridge FSP seems to be buggy that it does not report memory
used by FSP itself as reserved in the resource descriptor HOB. The
FSP specification does not describe how resource descriptor HOBs are
generated by the FSP to describe what memory regions. It looks newer
FSPs like Queensbay and BayTrail do not have such issue. This causes
U-Boot relocation overwrites the important boot service data which is
used by FSP, and the subsequent call to fsp_notify() will fail.

To resolve this, we find out the lowest memory base address allocated
by FSP for the boot service data when walking through the HOB list in
fsp_get_usable_lowmem_top(). Check whether the memory top address is
below the FSP HOB list, and if not, use the lowest memory base address
allocated by FSP as the memory top address.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/lib/fsp/fsp_support.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index 875c96a..d6bbe1a 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -223,7 +223,9 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list)
 {
 	const struct hob_header *hdr;
 	struct hob_res_desc *res_desc;
+	struct hob_mem_alloc *res_mem;
 	phys_addr_t phys_start;
+	phys_addr_t mem_base = 0;
 	u32 top;
 
 	/* Get the HOB list for processing */
@@ -242,9 +244,34 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list)
 					top += (u32)(res_desc->len);
 			}
 		}
+
+		/*
+		 * Find out the lowest memory base address allocated by FSP
+		 * for the boot service data
+		 */
+		if (hdr->type == HOB_TYPE_MEM_ALLOC) {
+			res_mem = (struct hob_mem_alloc *)hdr;
+			if (!mem_base)
+				mem_base = res_mem->mem_base;
+			if (res_mem->mem_base < mem_base)
+				mem_base = res_mem->mem_base;
+		}
+
 		hdr = get_next_hob(hdr);
 	}
 
+	/*
+	 * Check whether the memory top address is below the FSP HOB list.
+	 * If not, use the lowest memory base address allocated by FSP as
+	 * the memory top address. This is to prevent U-Boot relocation
+	 * overwrites the important boot service data which is used by FSP,
+	 * otherwise the subsequent call to fsp_notify() will fail.
+	 */
+	if (top > (u32)hob_list) {
+		debug("Adjust memory top address due to a buggy FSP\n");
+		top = (u32)mem_base;
+	}
+
 	return top;
 }
 
-- 
1.8.2.1

^ permalink raw reply related	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 08/10] x86: fsp: Always use hex numbers in the hob command output
  2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
                   ` (6 preceding siblings ...)
  2015-12-11 10:55 ` [U-Boot] [PATCH 07/10] x86: fsp: Make sure HOB list is not overwritten by U-Boot Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
  2015-12-19  2:52   ` Simon Glass
  2015-12-11 10:55 ` [U-Boot] [PATCH 09/10] x86: ivybridge: Add macros for LPC decode ranges Bin Meng
  2015-12-11 10:55 ` [U-Boot] [PATCH 10/10] x86: Add Intel Cougar Canyon 2 board Bin Meng
  9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
  To: u-boot

In the 'fsp hob' command output, decimal numbers and hexadecimal
numbers are used mixedly. Now change to always use hex numbers
to keep consistency.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/lib/fsp/cmd_fsp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/lib/fsp/cmd_fsp.c b/arch/x86/lib/fsp/cmd_fsp.c
index 4959edf..2554663 100644
--- a/arch/x86/lib/fsp/cmd_fsp.c
+++ b/arch/x86/lib/fsp/cmd_fsp.c
@@ -69,7 +69,7 @@ static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf("---|----------|-----------|------|-");
 	printf("------------------------------------------\n");
 	while (!end_of_hob(hdr)) {
-		printf("%-2d | %08x | ", i, (unsigned int)hdr);
+		printf("%02x | %08x | ", i, (unsigned int)hdr);
 		type = hdr->type;
 		if (type == HOB_TYPE_UNUSED)
 			desc = "*Unused*";
@@ -79,7 +79,7 @@ static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			desc = hob_type[type];
 		else
 			desc = "*Invalid*";
-		printf("%-9s | %-4d | ", desc, hdr->len);
+		printf("%-9s | %04x | ", desc, hdr->len);
 
 		if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC ||
 		    type == HOB_TYPE_GUID_EXT) {
-- 
1.8.2.1

^ permalink raw reply related	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 09/10] x86: ivybridge: Add macros for LPC decode ranges
  2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
                   ` (7 preceding siblings ...)
  2015-12-11 10:55 ` [U-Boot] [PATCH 08/10] x86: fsp: Always use hex numbers in the hob command output Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
  2015-12-19  2:52   ` Simon Glass
  2015-12-11 10:55 ` [U-Boot] [PATCH 10/10] x86: Add Intel Cougar Canyon 2 board Bin Meng
  9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
  To: u-boot

Add several macros for LPC decode registers on PCH.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/include/asm/arch-ivybridge/pch.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index 21df083..31437c8 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -105,6 +105,8 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
 #define GPIO_ROUT		0xb8
 
 #define LPC_IO_DEC		0x80 /* IO Decode Ranges Register */
+#define  COMB_DEC_RANGE		(1 << 4)  /* 0x2f8-0x2ff (COM2) */
+#define  COMA_DEC_RANGE		(0 << 0)  /* 0x3f8-0x3ff (COM1) */
 #define LPC_EN			0x82 /* LPC IF Enables Register */
 #define  CNF2_LPC_EN		(1 << 13) /* 0x4e/0x4f */
 #define  CNF1_LPC_EN		(1 << 12) /* 0x2e/0x2f */
@@ -121,6 +123,14 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
 #define LPC_GEN3_DEC		0x8c /* LPC IF Generic Decode Range 3 */
 #define LPC_GEN4_DEC		0x90 /* LPC IF Generic Decode Range 4 */
 #define LPC_GENX_DEC(x)		(0x84 + 4 * (x))
+#define  GEN_DEC_RANGE_256B	0xfc0000  /* 256 Bytes */
+#define  GEN_DEC_RANGE_128B	0x7c0000  /* 128 Bytes */
+#define  GEN_DEC_RANGE_64B	0x3c0000  /* 64 Bytes */
+#define  GEN_DEC_RANGE_32B	0x1c0000  /* 32 Bytes */
+#define  GEN_DEC_RANGE_16B	0x0c0000  /* 16 Bytes */
+#define  GEN_DEC_RANGE_8B	0x040000  /* 8 Bytes */
+#define  GEN_DEC_RANGE_4B	0x000000  /* 4 Bytes */
+#define  GEN_DEC_RANGE_EN	(1 << 0)  /* Range Enable */
 
 /* PCI Configuration Space (D31:F1): IDE */
 #define PCH_IDE_DEV		PCI_BDF(0, 0x1f, 1)
-- 
1.8.2.1

^ permalink raw reply related	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 10/10] x86: Add Intel Cougar Canyon 2 board
  2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
                   ` (8 preceding siblings ...)
  2015-12-11 10:55 ` [U-Boot] [PATCH 09/10] x86: ivybridge: Add macros for LPC decode ranges Bin Meng
@ 2015-12-11 10:55 ` Bin Meng
  2015-12-19  2:52   ` Simon Glass
  9 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-11 10:55 UTC (permalink / raw)
  To: u-boot

This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

 arch/x86/dts/Makefile                     |  1 +
 arch/x86/dts/cougarcanyon2.dts            | 96 +++++++++++++++++++++++++++++++
 board/intel/Kconfig                       |  9 +++
 board/intel/cougarcanyon2/Kconfig         | 25 ++++++++
 board/intel/cougarcanyon2/MAINTAINERS     |  6 ++
 board/intel/cougarcanyon2/Makefile        |  7 +++
 board/intel/cougarcanyon2/cougarcanyon2.c | 48 ++++++++++++++++
 board/intel/cougarcanyon2/start.S         |  9 +++
 configs/cougarcanyon2_defconfig           | 21 +++++++
 include/configs/cougarcanyon2.h           | 34 +++++++++++
 10 files changed, 256 insertions(+)
 create mode 100644 arch/x86/dts/cougarcanyon2.dts
 create mode 100644 board/intel/cougarcanyon2/Kconfig
 create mode 100644 board/intel/cougarcanyon2/MAINTAINERS
 create mode 100644 board/intel/cougarcanyon2/Makefile
 create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c
 create mode 100644 board/intel/cougarcanyon2/start.S
 create mode 100644 configs/cougarcanyon2_defconfig
 create mode 100644 include/configs/cougarcanyon2.h

diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 64e5694..84feb19 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -5,6 +5,7 @@
 dtb-y += bayleybay.dtb \
 	chromebook_link.dtb \
 	chromebox_panther.dtb \
+	cougarcanyon2.dtb \
 	crownbay.dtb \
 	efi.dtb \
 	galileo.dtb \
diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts
new file mode 100644
index 0000000..486999e
--- /dev/null
+++ b/arch/x86/dts/cougarcanyon2.dts
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+/include/ "keyboard.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+	model = "Intel Cougar Canyon 2";
+	compatible = "intel,cougarcanyon2", "intel,chiefriver";
+
+	aliases {
+		spi0 = "/spi";
+	};
+
+	config {
+		silent_console = <0>;
+	};
+
+	chosen {
+		stdout-path = "/serial";
+	};
+
+	microcode {
+		update at 0 {
+#include "microcode/m12306a2_00000008.dtsi"
+		};
+		update at 1 {
+#include "microcode/m12306a4_00000007.dtsi"
+		};
+		update at 2 {
+#include "microcode/m12306a5_00000007.dtsi"
+		};
+		update at 3 {
+#include "microcode/m12306a8_00000010.dtsi"
+		};
+		update at 4 {
+#include "microcode/m12306a9_0000001b.dtsi"
+		};
+	};
+
+	fsp {
+		compatible = "intel,ivybridge-fsp";
+		fsp,enable-ht;
+	};
+
+	pci {
+		#address-cells = <3>;
+		#size-cells = <2>;
+		compatible = "pci-x86";
+		u-boot,dm-pre-reloc;
+		ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
+			  0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
+			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+	};
+
+	gpioa {
+		compatible = "intel,ich6-gpio";
+		u-boot,dm-pre-reloc;
+		reg = <0 0x10>;
+		bank-name = "A";
+	};
+
+	gpiob {
+		compatible = "intel,ich6-gpio";
+		u-boot,dm-pre-reloc;
+		reg = <0x30 0x10>;
+		bank-name = "B";
+	};
+
+	gpioc {
+		compatible = "intel,ich6-gpio";
+		u-boot,dm-pre-reloc;
+		reg = <0x40 0x10>;
+		bank-name = "C";
+	};
+
+	spi {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "intel,ich-spi";
+		spi-flash at 0 {
+			reg = <0>;
+			compatible = "winbond,w25q64bv", "spi-flash";
+			memory-map = <0xff800000 0x00800000>;
+		};
+	};
+
+};
diff --git a/board/intel/Kconfig b/board/intel/Kconfig
index f7d71c3..4d341aa 100644
--- a/board/intel/Kconfig
+++ b/board/intel/Kconfig
@@ -18,6 +18,14 @@ config TARGET_BAYLEYBAY
 	  4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC,
 	  PCIe and some other sensor interfaces.
 
+config TARGET_COUGARCANYON2
+	bool "Cougar Canyon 2"
+	help
+	  This is the Intel Cougar Canyon 2 Customer Reference Board. It
+	  is built on the Chief River platform with Intel Ivybridge Processor
+	  and Panther Point chipset. The board has 4GB RAM, with some other
+	  peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI.
+
 config TARGET_CROWNBAY
 	bool "Crown Bay"
 	help
@@ -54,6 +62,7 @@ config TARGET_MINNOWMAX
 endchoice
 
 source "board/intel/bayleybay/Kconfig"
+source "board/intel/cougarcanyon2/Kconfig"
 source "board/intel/crownbay/Kconfig"
 source "board/intel/galileo/Kconfig"
 source "board/intel/minnowmax/Kconfig"
diff --git a/board/intel/cougarcanyon2/Kconfig b/board/intel/cougarcanyon2/Kconfig
new file mode 100644
index 0000000..95a617b
--- /dev/null
+++ b/board/intel/cougarcanyon2/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_COUGARCANYON2
+
+config SYS_BOARD
+	default "cougarcanyon2"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "ivybridge"
+
+config SYS_CONFIG_NAME
+	default "cougarcanyon2"
+
+config SYS_TEXT_BASE
+	default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select NORTHBRIDGE_INTEL_IVYBRIDGE
+	select HAVE_FSP
+	select BOARD_ROMSIZE_KB_2048
+
+endif
diff --git a/board/intel/cougarcanyon2/MAINTAINERS b/board/intel/cougarcanyon2/MAINTAINERS
new file mode 100644
index 0000000..a486739
--- /dev/null
+++ b/board/intel/cougarcanyon2/MAINTAINERS
@@ -0,0 +1,6 @@
+INTEL COUGAR CANYON 2 BOARD
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/intel/cougarcanyon2/
+F:	include/configs/cougarcanyon2.h
+F:	configs/cougarcanyon2_defconfig
diff --git a/board/intel/cougarcanyon2/Makefile b/board/intel/cougarcanyon2/Makefile
new file mode 100644
index 0000000..807f284
--- /dev/null
+++ b/board/intel/cougarcanyon2/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= cougarcanyon2.o start.o
diff --git a/board/intel/cougarcanyon2/cougarcanyon2.c b/board/intel/cougarcanyon2/cougarcanyon2.c
new file mode 100644
index 0000000..4cc47fb
--- /dev/null
+++ b/board/intel/cougarcanyon2/cougarcanyon2.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ibmpc.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+#include <pci.h>
+#include <smsc_sio1007.h>
+
+#define SIO1007_RUNTIME_IOPORT	0x180
+
+int board_early_init_f(void)
+{
+	/* Initialize LPC interface to turn on superio chipset decode range */
+	x86_pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC,
+			       COMA_DEC_RANGE | COMB_DEC_RANGE);
+	x86_pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | COMA_LPC_EN);
+	x86_pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, GEN_DEC_RANGE_256B |
+			       (SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN);
+	x86_pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, GEN_DEC_RANGE_16B |
+			       SIO1007_RUNTIME_IOPORT | GEN_DEC_RANGE_EN);
+
+	/* Enable legacy serial port at 0x3f8 */
+	sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ);
+
+	/* Enable SIO1007 runtime I/O port at 0x180 */
+	sio1007_enable_runtime(SIO1007_IOPORT3, SIO1007_RUNTIME_IOPORT);
+
+	/*
+	 * On Cougar Canyon 2 board, the RS232 transiver connected to serial
+	 * port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007.
+	 * Set the pin value to 1 to enable the RS232 transiver.
+	 */
+	sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT,
+			    GPIO_POL_NO_INVERT, GPIO_TYPE_PUSH_PULL);
+	sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1);
+
+	return 0;
+}
+
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
+{
+	return;
+}
diff --git a/board/intel/cougarcanyon2/start.S b/board/intel/cougarcanyon2/start.S
new file mode 100644
index 0000000..a71db69
--- /dev/null
+++ b/board/intel/cougarcanyon2/start.S
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+	jmp	early_board_init_ret
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
new file mode 100644
index 0000000..2d23dc3
--- /dev/null
+++ b/configs/cougarcanyon2_defconfig
@@ -0,0 +1,21 @@
+CONFIG_X86=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2"
+CONFIG_TARGET_COUGARCANYON2=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_VSNPRINTF=y
diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h
new file mode 100644
index 0000000..faac552
--- /dev/null
+++ b/include/configs/cougarcanyon2.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(2 << 20)
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SMSC_SIO1007
+
+#define CONFIG_PCI_PNP
+
+#define CONFIG_STD_DEVICES_SETTINGS	"stdin=serial,i8042-kbd,usbkbd\0" \
+					"stdout=serial,vga\0" \
+					"stderr=serial,vga\0"
+
+#define CONFIG_SCSI_DEV_LIST		\
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
+
+/* Environment configuration */
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x5ff000
+
+/* Video is not supported for now */
+#undef CONFIG_VIDEO
+#undef CONFIG_CFB_CONSOLE
+
+#endif	/* __CONFIG_H */
-- 
1.8.2.1

^ permalink raw reply related	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP
  2015-12-11 10:55 ` [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP Bin Meng
@ 2015-12-19  2:51   ` Simon Glass
  2015-12-21  2:33     ` Bin Meng
  2015-12-21  7:50     ` Bin Meng
  0 siblings, 2 replies; 39+ messages in thread
From: Simon Glass @ 2015-12-19  2:51 UTC (permalink / raw)
  To: u-boot

Hi Bin,

On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  include/fdtdec.h | 1 +
>  lib/fdtdec.c     | 1 +
>  2 files changed, 2 insertions(+)
>
> diff --git a/include/fdtdec.h b/include/fdtdec.h
> index 7fe657d..c515a3c 100644
> --- a/include/fdtdec.h
> +++ b/include/fdtdec.h
> @@ -169,6 +169,7 @@ enum fdt_compat_id {
>         COMPAT_ALTERA_SOCFPGA_DWMMC,    /* SoCFPGA DWMMC controller */
>         COMPAT_INTEL_BAYTRAIL_FSP,      /* Intel Bay Trail FSP */
>         COMPAT_INTEL_BAYTRAIL_FSP_MDP,  /* Intel FSP memory-down params */
> +       COMPAT_INTEL_IVYBRIDGE_FSP,     /* Intel Ivy Bridge FSP */
>
>         COMPAT_COUNT,
>  };
> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> index 82d0090..002594d 100644
> --- a/lib/fdtdec.c
> +++ b/lib/fdtdec.c
> @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
>         COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
>         COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
>         COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
> +       COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
>  };
>
>  const char *fdtdec_get_compatible(enum fdt_compat_id id)
> --
> 1.8.2.1
>

Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>

We should create an FSP uclass I think.

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support
  2015-12-11 10:55 ` [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support Bin Meng
@ 2015-12-19  2:52   ` Simon Glass
  2015-12-21  2:27     ` Bin Meng
  0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19  2:52 UTC (permalink / raw)
  To: u-boot

On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> IvyBridge FSP package is built with a base address at 0xfff80000,
> and does not use UPD data region. This adds basic FSP support.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/ivybridge/Kconfig                     |  8 ++++
>  arch/x86/cpu/ivybridge/Makefile                    |  4 ++
>  arch/x86/cpu/ivybridge/fsp_configs.c               | 45 ++++++++++++++++++++++
>  arch/x86/cpu/ivybridge/ivybridge.c                 | 22 +++++++++++
>  .../include/asm/arch-ivybridge/fsp/fsp_configs.h   | 40 +++++++++++++++++++
>  arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h  | 12 ++++++
>  6 files changed, 131 insertions(+)
>  create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
>  create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h

Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>

One question: why do we need an Intel license on this code?

- Simon

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 03/10] tools: microcode-tool: Support parsing header file with a license block
  2015-12-11 10:55 ` [U-Boot] [PATCH 03/10] tools: microcode-tool: Support parsing header file with a license block Bin Meng
@ 2015-12-19  2:52   ` Simon Glass
  2015-12-21  7:50     ` Bin Meng
  0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19  2:52 UTC (permalink / raw)
  To: u-boot

On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> The microcode header files in the Intel Chief River FSP package have
> a license comment block. Update the microcode-tool to support parsing
> it and extract the license text to the .dtsi file.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  tools/microcode-tool.py | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 04/10] x86: ivybridge: Add microcode blobs for all the steppings
  2015-12-11 10:55 ` [U-Boot] [PATCH 04/10] x86: ivybridge: Add microcode blobs for all the steppings Bin Meng
@ 2015-12-19  2:52   ` Simon Glass
  2015-12-21  7:50     ` Bin Meng
  0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19  2:52 UTC (permalink / raw)
  To: u-boot

On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> This adds microcode blobs created from Intel FSP package for the
> Chief River platform. They are for all the Ivy Bridge steppings:
> 306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
> 306a9 which is already in the U-Boot tree.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/dts/microcode/m12306a2_00000008.dtsi | 554 +++++++++++++++++++++
>  arch/x86/dts/microcode/m12306a4_00000007.dtsi | 618 +++++++++++++++++++++++
>  arch/x86/dts/microcode/m12306a5_00000007.dtsi | 618 +++++++++++++++++++++++
>  arch/x86/dts/microcode/m12306a8_00000010.dtsi | 682 ++++++++++++++++++++++++++
>  4 files changed, 2472 insertions(+)
>  create mode 100644 arch/x86/dts/microcode/m12306a2_00000008.dtsi
>  create mode 100644 arch/x86/dts/microcode/m12306a4_00000007.dtsi
>  create mode 100644 arch/x86/dts/microcode/m12306a5_00000007.dtsi
>  create mode 100644 arch/x86/dts/microcode/m12306a8_00000010.dtsi

Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver
  2015-12-11 10:55 ` [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver Bin Meng
@ 2015-12-19  2:52   ` Simon Glass
  2015-12-21  2:42     ` Bin Meng
  0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19  2:52 UTC (permalink / raw)
  To: u-boot

Hi Bin,

On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> The SMSC SIO1007 superio chipset integrates two ns16550 compatible
> serial ports for legacy applications, 16 GPIO pins and some other
> functionalities like power management.
>
> This adds a simple driver to enable serial port and handle GPIO.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  drivers/misc/Makefile       |   1 +
>  drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++
>  include/smsc_sio1007.h      | 115 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 242 insertions(+)
>  create mode 100644 drivers/misc/smsc_sio1007.c
>  create mode 100644 include/smsc_sio1007.h
>
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index aa137f5..6952f8ce 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C
>  obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
>  endif
>  obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
> +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
>  obj-$(CONFIG_STATUS_LED) += status_led.o
>  obj-$(CONFIG_SANDBOX) += swap_case.o
>  obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
> diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c
> new file mode 100644
> index 0000000..79e9e15
> --- /dev/null
> +++ b/drivers/misc/smsc_sio1007.c
> @@ -0,0 +1,126 @@
> +/*
> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <errno.h>
> +#include <smsc_sio1007.h>
> +
> +static inline u8 sio1007_read(int port, int reg)
> +{
> +       outb(reg, port);
> +
> +       return inb(port + 1);
> +}
> +
> +static inline void sio1007_write(int port, int reg, int val)
> +{
> +       outb(reg, port);
> +       outb(val, port + 1);
> +}
> +
> +static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set)
> +{
> +       sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);
> +}
> +
> +void sio1007_enable_serial(int port, int num, int iobase, int irq)
> +{
> +       if (num < 0 || num > SIO1007_UART_NUM)
> +               return;
> +
> +       /* enter configuration state */
> +       outb(0x55, port);
> +
> +       /* power on serial port and set up its i/o base & irq */
> +       if (!num) {
> +               sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);
> +               sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);
> +               sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);
> +       } else {
> +               sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);
> +               sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);
> +               sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);
> +       }
> +
> +       /* exit configuration state */
> +       outb(0xaa, port);
> +}
> +
> +void sio1007_enable_runtime(int port, int iobase)
> +{
> +       /* enter configuration state */
> +       outb(0x55, port);
> +
> +       /* set i/o base for the runtime register block */
> +       sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);
> +       sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);
> +       /* turn on address decoding for this block */
> +       sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);
> +
> +       /* exit configuration state */
> +       outb(0xaa, port);
> +}
> +
> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type)
> +{
> +       int reg = GPIO0_DIR;
> +
> +       if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
> +               return;
> +       if (gpio >= GPIO_NUM_PER_GROUP) {
> +               reg = GPIO1_DIR;
> +               gpio -= GPIO_NUM_PER_GROUP;
> +       }
> +
> +       /* enter configuration state */
> +       outb(0x55, port);
> +
> +       /* set gpio pin direction, polority and type */
> +       sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);
> +       sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);
> +       sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);
> +
> +       /* exit configuration state */
> +       outb(0xaa, port);
> +}
> +
> +int sio1007_gpio_get_value(int port, int gpio)
> +{
> +       int reg = GPIO0_DATA;
> +       int val;
> +
> +       if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
> +               return -EINVAL;
> +       if (gpio >= GPIO_NUM_PER_GROUP) {
> +               reg = GPIO1_DATA;
> +               gpio -= GPIO_NUM_PER_GROUP;
> +       }
> +
> +       val = inb(port + reg);
> +       if (val & (1 << gpio))
> +               return 1;
> +       else
> +               return 0;
> +}
> +
> +void sio1007_gpio_set_value(int port, int gpio, int val)
> +{
> +       int reg = GPIO0_DATA;
> +       u8 data;
> +
> +       if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
> +               return;
> +       if (gpio >= GPIO_NUM_PER_GROUP) {
> +               reg = GPIO1_DATA;
> +               gpio -= GPIO_NUM_PER_GROUP;
> +       }
> +
> +       data = inb(port + reg);
> +       data &= ~(1 << gpio);
> +       data |= (val << gpio);
> +       outb(data, port + reg);
> +}

This should be modeled as a GPIO driver in the GPIO uclass.

> diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h
> new file mode 100644
> index 0000000..eff57a7
> --- /dev/null
> +++ b/include/smsc_sio1007.h
> @@ -0,0 +1,115 @@
> +/*
> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#ifndef _SMSC_SIO1007_H_
> +#define _SMSC_SIO1007_H_
> +
> +/*
> + * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
> + * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
> + * SYSOPT0 and SYSOPT1 determines one of the following addresses.
> + */
> +#define SIO1007_IOPORT0                0x002e
> +#define SIO1007_IOPORT1                0x004e
> +#define SIO1007_IOPORT2                0x162e
> +#define SIO1007_IOPORT3                0x164e
> +
> +/* SIO1007 registers */
> +
> +#define DEV_POWER_CTRL         0x02
> +#define UART1_POWER_ON         (1 << 3)
> +#define UART2_POWER_ON         (1 << 7)
> +
> +#define UART1_IOBASE           0x24
> +#define UART2_IOBASE           0x25
> +#define UART_IRQ               0x28
> +
> +#define RTR_IOBASE_HIGH                0x21
> +#define RTR_IOBASE_LOW         0x30
> +
> +#define GPIO0_DIR              0x31
> +#define GPIO1_DIR              0x35
> +#define GPIO_DIR_INPUT         0
> +#define GPIO_DIR_OUTPUT                1
> +
> +#define GPIO0_POL              0x32
> +#define GPIO1_POL              0x36
> +#define GPIO_POL_NO_INVERT     0
> +#define GPIO_POL_INVERT                1
> +
> +#define GPIO0_TYPE             0x33
> +#define GPIO1_TYPE             0x37
> +#define GPIO_TYPE_PUSH_PULL    0
> +#define GPIO_TYPE_OPEN_DRAIN   1
> +
> +#define DEV_ACTIVATE           0x3a
> +#define RTR_EN                 (1 << 1)
> +
> +/* Runtime register offset */
> +
> +#define GPIO0_DATA             0xc
> +#define GPIO1_DATA             0xe
> +
> +/* Number of serial ports supported */
> +#define SIO1007_UART_NUM       2
> +
> +/* Number of gpio pins supported */
> +#define GPIO_NUM_PER_GROUP     8
> +#define GPIO_GROUP_NUM         2
> +#define SIO1007_GPIO_NUM       (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
> +
> +/**
> + * Configure the I/O port address of the specified serial device and
> + * enable the serial device.
> + *
> + * @port:      SIO1007 I/O port address
> + * @num:       serial device number (0 or 1)
> + * @iobase:    processor I/O port address to assign to this serial device
> + * @irq:       processor IRQ number to assign to this serial device
> + */
> +void sio1007_enable_serial(int port, int num, int iobase, int irq);

I wonder if we need a parent device which provides access to these
features, and then a GPIO child device?

> +
> +/**
> + * Configure the I/O port address of the runtime register block and
> + * enable the address decoding.
> + *
> + * @port:      SIO1007 I/O port address
> + * @iobase:    processor I/O port address to assign to the runtime registers
> + */
> +void sio1007_enable_runtime(int port, int iobase);
> +
> +/**
> + * Configure the direction/polority/type of a specified GPIO pin
> + *
> + * @port:      SIO1007 I/O port address
> + * @gpio:      GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
> + * @dir:       GPIO_DIR_INPUT or GPIO_DIR_OUTPUT
> + * @pol:       GPIO_POL_NO_INVERT or GPIO_POL_INVERT
> + * @type:      GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN
> + */
> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type);
> +
> +/**
> + * Get a GPIO pin value.
> + * This will work whether the GPIO is an input or an output.
> + *
> + * @port:      runtime register block I/O port address
> + * @gpio:      GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
> + * @return:    0 if low, 1 if high, -EINVAL if gpio number is invalid
> + */
> +int sio1007_gpio_get_value(int port, int gpio);
> +
> +/**
> + * Set a GPIO pin value.
> + * This will only work when the GPIO is configured as an output.
> + *
> + * @port:      runtime register block I/O port address
> + * @gpio:      GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
> + * @val:       0 if low, 1 if high
> + */
> +void sio1007_gpio_set_value(int port, int gpio, int val);
> +
> +#endif /* _SMSC_SIO1007_H_ */
> --
> 1.8.2.1
>


Regards,
Simon

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 06/10] x86: ivybridge: Do not require HAVE_INTEL_ME
  2015-12-11 10:55 ` [U-Boot] [PATCH 06/10] x86: ivybridge: Do not require HAVE_INTEL_ME Bin Meng
@ 2015-12-19  2:52   ` Simon Glass
  2015-12-21  7:50     ` Bin Meng
  0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19  2:52 UTC (permalink / raw)
  To: u-boot

On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> Do not set HAVE_INTEL_ME by default as for some cases Intel ME
> firmware even does not reside on the same SPI flash as U-Boot.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/ivybridge/Kconfig         | 1 -
>  board/google/chromebook_link/Kconfig   | 1 +
>  board/google/chromebox_panther/Kconfig | 1 +
>  3 files changed, 2 insertions(+), 1 deletion(-)

Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 07/10] x86: fsp: Make sure HOB list is not overwritten by U-Boot
  2015-12-11 10:55 ` [U-Boot] [PATCH 07/10] x86: fsp: Make sure HOB list is not overwritten by U-Boot Bin Meng
@ 2015-12-19  2:52   ` Simon Glass
  2015-12-21  2:36     ` Bin Meng
  0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19  2:52 UTC (permalink / raw)
  To: u-boot

Hi Bin,

On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> Intel IvyBridge FSP seems to be buggy that it does not report memory
> used by FSP itself as reserved in the resource descriptor HOB. The
> FSP specification does not describe how resource descriptor HOBs are
> generated by the FSP to describe what memory regions. It looks newer
> FSPs like Queensbay and BayTrail do not have such issue. This causes
> U-Boot relocation overwrites the important boot service data which is
> used by FSP, and the subsequent call to fsp_notify() will fail.
>
> To resolve this, we find out the lowest memory base address allocated
> by FSP for the boot service data when walking through the HOB list in
> fsp_get_usable_lowmem_top(). Check whether the memory top address is
> below the FSP HOB list, and if not, use the lowest memory base address
> allocated by FSP as the memory top address.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/lib/fsp/fsp_support.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>

But if this is a bug I'd prefer to have it behind an #iffdef, or with
a large comment in the code. Otherwise we might think it is an
important feature for all platforms.

>
> diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
> index 875c96a..d6bbe1a 100644
> --- a/arch/x86/lib/fsp/fsp_support.c
> +++ b/arch/x86/lib/fsp/fsp_support.c
> @@ -223,7 +223,9 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list)
>  {
>         const struct hob_header *hdr;
>         struct hob_res_desc *res_desc;
> +       struct hob_mem_alloc *res_mem;
>         phys_addr_t phys_start;
> +       phys_addr_t mem_base = 0;
>         u32 top;
>
>         /* Get the HOB list for processing */
> @@ -242,9 +244,34 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list)
>                                         top += (u32)(res_desc->len);
>                         }
>                 }
> +
> +               /*
> +                * Find out the lowest memory base address allocated by FSP
> +                * for the boot service data
> +                */
> +               if (hdr->type == HOB_TYPE_MEM_ALLOC) {
> +                       res_mem = (struct hob_mem_alloc *)hdr;
> +                       if (!mem_base)
> +                               mem_base = res_mem->mem_base;
> +                       if (res_mem->mem_base < mem_base)
> +                               mem_base = res_mem->mem_base;
> +               }
> +
>                 hdr = get_next_hob(hdr);
>         }
>
> +       /*
> +        * Check whether the memory top address is below the FSP HOB list.
> +        * If not, use the lowest memory base address allocated by FSP as
> +        * the memory top address. This is to prevent U-Boot relocation
> +        * overwrites the important boot service data which is used by FSP,
> +        * otherwise the subsequent call to fsp_notify() will fail.
> +        */
> +       if (top > (u32)hob_list) {
> +               debug("Adjust memory top address due to a buggy FSP\n");
> +               top = (u32)mem_base;
> +       }
> +
>         return top;
>  }
>
> --
> 1.8.2.1
>

Regards,
Simon

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 08/10] x86: fsp: Always use hex numbers in the hob command output
  2015-12-11 10:55 ` [U-Boot] [PATCH 08/10] x86: fsp: Always use hex numbers in the hob command output Bin Meng
@ 2015-12-19  2:52   ` Simon Glass
  2015-12-21  7:50     ` Bin Meng
  0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19  2:52 UTC (permalink / raw)
  To: u-boot

On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> In the 'fsp hob' command output, decimal numbers and hexadecimal
> numbers are used mixedly. Now change to always use hex numbers
> to keep consistency.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/lib/fsp/cmd_fsp.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Acked-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 09/10] x86: ivybridge: Add macros for LPC decode ranges
  2015-12-11 10:55 ` [U-Boot] [PATCH 09/10] x86: ivybridge: Add macros for LPC decode ranges Bin Meng
@ 2015-12-19  2:52   ` Simon Glass
  2015-12-21  7:50     ` Bin Meng
  0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19  2:52 UTC (permalink / raw)
  To: u-boot

On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> Add several macros for LPC decode registers on PCH.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/include/asm/arch-ivybridge/pch.h | 10 ++++++++++
>  1 file changed, 10 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 10/10] x86: Add Intel Cougar Canyon 2 board
  2015-12-11 10:55 ` [U-Boot] [PATCH 10/10] x86: Add Intel Cougar Canyon 2 board Bin Meng
@ 2015-12-19  2:52   ` Simon Glass
  2015-12-21  2:34     ` Bin Meng
  0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-19  2:52 UTC (permalink / raw)
  To: u-boot

Hi Bin,

On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> This adds basic support to Intel Cougar Canyon 2 board, a board
> based on Chief River platform with an Ivy Bridge processor and
> a Panther Point chipset.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
>  arch/x86/dts/Makefile                     |  1 +
>  arch/x86/dts/cougarcanyon2.dts            | 96 +++++++++++++++++++++++++++++++
>  board/intel/Kconfig                       |  9 +++
>  board/intel/cougarcanyon2/Kconfig         | 25 ++++++++
>  board/intel/cougarcanyon2/MAINTAINERS     |  6 ++
>  board/intel/cougarcanyon2/Makefile        |  7 +++
>  board/intel/cougarcanyon2/cougarcanyon2.c | 48 ++++++++++++++++
>  board/intel/cougarcanyon2/start.S         |  9 +++
>  configs/cougarcanyon2_defconfig           | 21 +++++++
>  include/configs/cougarcanyon2.h           | 34 +++++++++++
>  10 files changed, 256 insertions(+)
>  create mode 100644 arch/x86/dts/cougarcanyon2.dts
>  create mode 100644 board/intel/cougarcanyon2/Kconfig
>  create mode 100644 board/intel/cougarcanyon2/MAINTAINERS
>  create mode 100644 board/intel/cougarcanyon2/Makefile
>  create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c
>  create mode 100644 board/intel/cougarcanyon2/start.S
>  create mode 100644 configs/cougarcanyon2_defconfig
>  create mode 100644 include/configs/cougarcanyon2.h

Acked-by: Simon Glass <sjg@chromium.org>

A few nits though:
- Include order - <asm/... should go after the normal includes
- can we drop the calls to x86_pci_...? Please check it on top of the
u-boot-dm/pcif-working series

- Simon

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support
  2015-12-19  2:52   ` Simon Glass
@ 2015-12-21  2:27     ` Bin Meng
  2015-12-23 16:44       ` Simon Glass
  0 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-21  2:27 UTC (permalink / raw)
  To: u-boot

Hi Simon,

On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> IvyBridge FSP package is built with a base address at 0xfff80000,
>> and does not use UPD data region. This adds basic FSP support.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/ivybridge/Kconfig                     |  8 ++++
>>  arch/x86/cpu/ivybridge/Makefile                    |  4 ++
>>  arch/x86/cpu/ivybridge/fsp_configs.c               | 45 ++++++++++++++++++++++
>>  arch/x86/cpu/ivybridge/ivybridge.c                 | 22 +++++++++++
>>  .../include/asm/arch-ivybridge/fsp/fsp_configs.h   | 40 +++++++++++++++++++
>>  arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h  | 12 ++++++
>>  6 files changed, 131 insertions(+)
>>  create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
>>  create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
>>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
>>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested on link (ivybridge non-FSP)
> Tested-by: Simon Glass <sjg@chromium.org>
>
> One question: why do we need an Intel license on this code?
>

It was a copy and paste from other platform (queensbay and baytrail)
files. Do you think we should change it to GPLv2+?

Regards,
Bin

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP
  2015-12-19  2:51   ` Simon Glass
@ 2015-12-21  2:33     ` Bin Meng
  2016-02-06  4:29       ` Bin Meng
  2015-12-21  7:50     ` Bin Meng
  1 sibling, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-21  2:33 UTC (permalink / raw)
  To: u-boot

Hi Simon,

On Sat, Dec 19, 2015 at 10:51 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  include/fdtdec.h | 1 +
>>  lib/fdtdec.c     | 1 +
>>  2 files changed, 2 insertions(+)
>>
>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>> index 7fe657d..c515a3c 100644
>> --- a/include/fdtdec.h
>> +++ b/include/fdtdec.h
>> @@ -169,6 +169,7 @@ enum fdt_compat_id {
>>         COMPAT_ALTERA_SOCFPGA_DWMMC,    /* SoCFPGA DWMMC controller */
>>         COMPAT_INTEL_BAYTRAIL_FSP,      /* Intel Bay Trail FSP */
>>         COMPAT_INTEL_BAYTRAIL_FSP_MDP,  /* Intel FSP memory-down params */
>> +       COMPAT_INTEL_IVYBRIDGE_FSP,     /* Intel Ivy Bridge FSP */
>>
>>         COMPAT_COUNT,
>>  };
>> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
>> index 82d0090..002594d 100644
>> --- a/lib/fdtdec.c
>> +++ b/lib/fdtdec.c
>> @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
>>         COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
>>         COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
>>         COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
>> +       COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
>>  };
>>
>>  const char *fdtdec_get_compatible(enum fdt_compat_id id)
>> --
>> 1.8.2.1
>>
>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested on link (ivybridge non-FSP)
> Tested-by: Simon Glass <sjg@chromium.org>
>
> We should create an FSP uclass I think.

Maybe, I will add this in my todo list for next release.

Regards,
Bin

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 10/10] x86: Add Intel Cougar Canyon 2 board
  2015-12-19  2:52   ` Simon Glass
@ 2015-12-21  2:34     ` Bin Meng
  0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21  2:34 UTC (permalink / raw)
  To: u-boot

Hi Simon,

On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> This adds basic support to Intel Cougar Canyon 2 board, a board
>> based on Chief River platform with an Ivy Bridge processor and
>> a Panther Point chipset.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>
>> ---
>>
>>  arch/x86/dts/Makefile                     |  1 +
>>  arch/x86/dts/cougarcanyon2.dts            | 96 +++++++++++++++++++++++++++++++
>>  board/intel/Kconfig                       |  9 +++
>>  board/intel/cougarcanyon2/Kconfig         | 25 ++++++++
>>  board/intel/cougarcanyon2/MAINTAINERS     |  6 ++
>>  board/intel/cougarcanyon2/Makefile        |  7 +++
>>  board/intel/cougarcanyon2/cougarcanyon2.c | 48 ++++++++++++++++
>>  board/intel/cougarcanyon2/start.S         |  9 +++
>>  configs/cougarcanyon2_defconfig           | 21 +++++++
>>  include/configs/cougarcanyon2.h           | 34 +++++++++++
>>  10 files changed, 256 insertions(+)
>>  create mode 100644 arch/x86/dts/cougarcanyon2.dts
>>  create mode 100644 board/intel/cougarcanyon2/Kconfig
>>  create mode 100644 board/intel/cougarcanyon2/MAINTAINERS
>>  create mode 100644 board/intel/cougarcanyon2/Makefile
>>  create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c
>>  create mode 100644 board/intel/cougarcanyon2/start.S
>>  create mode 100644 configs/cougarcanyon2_defconfig
>>  create mode 100644 include/configs/cougarcanyon2.h
>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> A few nits though:
> - Include order - <asm/... should go after the normal includes
> - can we drop the calls to x86_pci_...? Please check it on top of the
> u-boot-dm/pcif-working series
>

Yep, I plan to do v2 after all your previous DM patches are applied.

Regards,
Bin

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 07/10] x86: fsp: Make sure HOB list is not overwritten by U-Boot
  2015-12-19  2:52   ` Simon Glass
@ 2015-12-21  2:36     ` Bin Meng
  0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21  2:36 UTC (permalink / raw)
  To: u-boot

Hi Simon,

On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Intel IvyBridge FSP seems to be buggy that it does not report memory
>> used by FSP itself as reserved in the resource descriptor HOB. The
>> FSP specification does not describe how resource descriptor HOBs are
>> generated by the FSP to describe what memory regions. It looks newer
>> FSPs like Queensbay and BayTrail do not have such issue. This causes
>> U-Boot relocation overwrites the important boot service data which is
>> used by FSP, and the subsequent call to fsp_notify() will fail.
>>
>> To resolve this, we find out the lowest memory base address allocated
>> by FSP for the boot service data when walking through the HOB list in
>> fsp_get_usable_lowmem_top(). Check whether the memory top address is
>> below the FSP HOB list, and if not, use the lowest memory base address
>> allocated by FSP as the memory top address.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/lib/fsp/fsp_support.c | 27 +++++++++++++++++++++++++++
>>  1 file changed, 27 insertions(+)
>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested on link (ivybridge non-FSP)
> Tested-by: Simon Glass <sjg@chromium.org>
>
> But if this is a bug I'd prefer to have it behind an #iffdef, or with
> a large comment in the code. Otherwise we might think it is an
> important feature for all platforms.
>

Yep, will change to use #ifdef in v2.

Regards,
Bin

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver
  2015-12-19  2:52   ` Simon Glass
@ 2015-12-21  2:42     ` Bin Meng
  2016-01-06  0:24       ` Simon Glass
  0 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2015-12-21  2:42 UTC (permalink / raw)
  To: u-boot

Hi Simon,

On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> The SMSC SIO1007 superio chipset integrates two ns16550 compatible
>> serial ports for legacy applications, 16 GPIO pins and some other
>> functionalities like power management.
>>
>> This adds a simple driver to enable serial port and handle GPIO.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  drivers/misc/Makefile       |   1 +
>>  drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++
>>  include/smsc_sio1007.h      | 115 ++++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 242 insertions(+)
>>  create mode 100644 drivers/misc/smsc_sio1007.c
>>  create mode 100644 include/smsc_sio1007.h
>>
>> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
>> index aa137f5..6952f8ce 100644
>> --- a/drivers/misc/Makefile
>> +++ b/drivers/misc/Makefile
>> @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C
>>  obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
>>  endif
>>  obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
>> +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
>>  obj-$(CONFIG_STATUS_LED) += status_led.o
>>  obj-$(CONFIG_SANDBOX) += swap_case.o
>>  obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
>> diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c
>> new file mode 100644
>> index 0000000..79e9e15
>> --- /dev/null
>> +++ b/drivers/misc/smsc_sio1007.c
>> @@ -0,0 +1,126 @@
>> +/*
>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
>> + *
>> + * SPDX-License-Identifier:    GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/io.h>
>> +#include <errno.h>
>> +#include <smsc_sio1007.h>
>> +
>> +static inline u8 sio1007_read(int port, int reg)
>> +{
>> +       outb(reg, port);
>> +
>> +       return inb(port + 1);
>> +}
>> +
>> +static inline void sio1007_write(int port, int reg, int val)
>> +{
>> +       outb(reg, port);
>> +       outb(val, port + 1);
>> +}
>> +
>> +static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set)
>> +{
>> +       sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);
>> +}
>> +
>> +void sio1007_enable_serial(int port, int num, int iobase, int irq)
>> +{
>> +       if (num < 0 || num > SIO1007_UART_NUM)
>> +               return;
>> +
>> +       /* enter configuration state */
>> +       outb(0x55, port);
>> +
>> +       /* power on serial port and set up its i/o base & irq */
>> +       if (!num) {
>> +               sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);
>> +               sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);
>> +               sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);
>> +       } else {
>> +               sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);
>> +               sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);
>> +               sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);
>> +       }
>> +
>> +       /* exit configuration state */
>> +       outb(0xaa, port);
>> +}
>> +
>> +void sio1007_enable_runtime(int port, int iobase)
>> +{
>> +       /* enter configuration state */
>> +       outb(0x55, port);
>> +
>> +       /* set i/o base for the runtime register block */
>> +       sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);
>> +       sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);
>> +       /* turn on address decoding for this block */
>> +       sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);
>> +
>> +       /* exit configuration state */
>> +       outb(0xaa, port);
>> +}
>> +
>> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type)
>> +{
>> +       int reg = GPIO0_DIR;
>> +
>> +       if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>> +               return;
>> +       if (gpio >= GPIO_NUM_PER_GROUP) {
>> +               reg = GPIO1_DIR;
>> +               gpio -= GPIO_NUM_PER_GROUP;
>> +       }
>> +
>> +       /* enter configuration state */
>> +       outb(0x55, port);
>> +
>> +       /* set gpio pin direction, polority and type */
>> +       sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);
>> +       sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);
>> +       sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);
>> +
>> +       /* exit configuration state */
>> +       outb(0xaa, port);
>> +}
>> +
>> +int sio1007_gpio_get_value(int port, int gpio)
>> +{
>> +       int reg = GPIO0_DATA;
>> +       int val;
>> +
>> +       if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>> +               return -EINVAL;
>> +       if (gpio >= GPIO_NUM_PER_GROUP) {
>> +               reg = GPIO1_DATA;
>> +               gpio -= GPIO_NUM_PER_GROUP;
>> +       }
>> +
>> +       val = inb(port + reg);
>> +       if (val & (1 << gpio))
>> +               return 1;
>> +       else
>> +               return 0;
>> +}
>> +
>> +void sio1007_gpio_set_value(int port, int gpio, int val)
>> +{
>> +       int reg = GPIO0_DATA;
>> +       u8 data;
>> +
>> +       if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>> +               return;
>> +       if (gpio >= GPIO_NUM_PER_GROUP) {
>> +               reg = GPIO1_DATA;
>> +               gpio -= GPIO_NUM_PER_GROUP;
>> +       }
>> +
>> +       data = inb(port + reg);
>> +       data &= ~(1 << gpio);
>> +       data |= (val << gpio);
>> +       outb(data, port + reg);
>> +}
>
> This should be modeled as a GPIO driver in the GPIO uclass.
>
>> diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h
>> new file mode 100644
>> index 0000000..eff57a7
>> --- /dev/null
>> +++ b/include/smsc_sio1007.h
>> @@ -0,0 +1,115 @@
>> +/*
>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
>> + *
>> + * SPDX-License-Identifier:    GPL-2.0+
>> + */
>> +
>> +#ifndef _SMSC_SIO1007_H_
>> +#define _SMSC_SIO1007_H_
>> +
>> +/*
>> + * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
>> + * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
>> + * SYSOPT0 and SYSOPT1 determines one of the following addresses.
>> + */
>> +#define SIO1007_IOPORT0                0x002e
>> +#define SIO1007_IOPORT1                0x004e
>> +#define SIO1007_IOPORT2                0x162e
>> +#define SIO1007_IOPORT3                0x164e
>> +
>> +/* SIO1007 registers */
>> +
>> +#define DEV_POWER_CTRL         0x02
>> +#define UART1_POWER_ON         (1 << 3)
>> +#define UART2_POWER_ON         (1 << 7)
>> +
>> +#define UART1_IOBASE           0x24
>> +#define UART2_IOBASE           0x25
>> +#define UART_IRQ               0x28
>> +
>> +#define RTR_IOBASE_HIGH                0x21
>> +#define RTR_IOBASE_LOW         0x30
>> +
>> +#define GPIO0_DIR              0x31
>> +#define GPIO1_DIR              0x35
>> +#define GPIO_DIR_INPUT         0
>> +#define GPIO_DIR_OUTPUT                1
>> +
>> +#define GPIO0_POL              0x32
>> +#define GPIO1_POL              0x36
>> +#define GPIO_POL_NO_INVERT     0
>> +#define GPIO_POL_INVERT                1
>> +
>> +#define GPIO0_TYPE             0x33
>> +#define GPIO1_TYPE             0x37
>> +#define GPIO_TYPE_PUSH_PULL    0
>> +#define GPIO_TYPE_OPEN_DRAIN   1
>> +
>> +#define DEV_ACTIVATE           0x3a
>> +#define RTR_EN                 (1 << 1)
>> +
>> +/* Runtime register offset */
>> +
>> +#define GPIO0_DATA             0xc
>> +#define GPIO1_DATA             0xe
>> +
>> +/* Number of serial ports supported */
>> +#define SIO1007_UART_NUM       2
>> +
>> +/* Number of gpio pins supported */
>> +#define GPIO_NUM_PER_GROUP     8
>> +#define GPIO_GROUP_NUM         2
>> +#define SIO1007_GPIO_NUM       (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
>> +
>> +/**
>> + * Configure the I/O port address of the specified serial device and
>> + * enable the serial device.
>> + *
>> + * @port:      SIO1007 I/O port address
>> + * @num:       serial device number (0 or 1)
>> + * @iobase:    processor I/O port address to assign to this serial device
>> + * @irq:       processor IRQ number to assign to this serial device
>> + */
>> +void sio1007_enable_serial(int port, int num, int iobase, int irq);
>
> I wonder if we need a parent device which provides access to these
> features, and then a GPIO child device?

I was thinking we create a superio uclass for this, but I found it's
not generic enough to abstract the ops for this uclass, if we take a
look at the existing SMSC LPC47M and this new one. Given these
routines will only need to be called just once during boot up, I
decided not to use driver model on this type of device.

>
>> +
>> +/**
>> + * Configure the I/O port address of the runtime register block and
>> + * enable the address decoding.
>> + *
>> + * @port:      SIO1007 I/O port address
>> + * @iobase:    processor I/O port address to assign to the runtime registers
>> + */
>> +void sio1007_enable_runtime(int port, int iobase);
>> +
>> +/**
>> + * Configure the direction/polority/type of a specified GPIO pin
>> + *
>> + * @port:      SIO1007 I/O port address
>> + * @gpio:      GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
>> + * @dir:       GPIO_DIR_INPUT or GPIO_DIR_OUTPUT
>> + * @pol:       GPIO_POL_NO_INVERT or GPIO_POL_INVERT
>> + * @type:      GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN
>> + */
>> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type);
>> +
>> +/**
>> + * Get a GPIO pin value.
>> + * This will work whether the GPIO is an input or an output.
>> + *
>> + * @port:      runtime register block I/O port address
>> + * @gpio:      GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
>> + * @return:    0 if low, 1 if high, -EINVAL if gpio number is invalid
>> + */
>> +int sio1007_gpio_get_value(int port, int gpio);
>> +
>> +/**
>> + * Set a GPIO pin value.
>> + * This will only work when the GPIO is configured as an output.
>> + *
>> + * @port:      runtime register block I/O port address
>> + * @gpio:      GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
>> + * @val:       0 if low, 1 if high
>> + */
>> +void sio1007_gpio_set_value(int port, int gpio, int val);
>> +
>> +#endif /* _SMSC_SIO1007_H_ */
>> --
>> 1.8.2.1
>>

Regards,
Bin

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP
  2015-12-19  2:51   ` Simon Glass
  2015-12-21  2:33     ` Bin Meng
@ 2015-12-21  7:50     ` Bin Meng
  1 sibling, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21  7:50 UTC (permalink / raw)
  To: u-boot

On Sat, Dec 19, 2015 at 10:51 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  include/fdtdec.h | 1 +
>>  lib/fdtdec.c     | 1 +
>>  2 files changed, 2 insertions(+)
>>
>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>> index 7fe657d..c515a3c 100644
>> --- a/include/fdtdec.h
>> +++ b/include/fdtdec.h
>> @@ -169,6 +169,7 @@ enum fdt_compat_id {
>>         COMPAT_ALTERA_SOCFPGA_DWMMC,    /* SoCFPGA DWMMC controller */
>>         COMPAT_INTEL_BAYTRAIL_FSP,      /* Intel Bay Trail FSP */
>>         COMPAT_INTEL_BAYTRAIL_FSP_MDP,  /* Intel FSP memory-down params */
>> +       COMPAT_INTEL_IVYBRIDGE_FSP,     /* Intel Ivy Bridge FSP */
>>
>>         COMPAT_COUNT,
>>  };
>> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
>> index 82d0090..002594d 100644
>> --- a/lib/fdtdec.c
>> +++ b/lib/fdtdec.c
>> @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
>>         COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
>>         COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
>>         COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
>> +       COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
>>  };
>>
>>  const char *fdtdec_get_compatible(enum fdt_compat_id id)
>> --
>> 1.8.2.1
>>
>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested on link (ivybridge non-FSP)
> Tested-by: Simon Glass <sjg@chromium.org>
>

applied to u-boot-x86/next, thanks!

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 03/10] tools: microcode-tool: Support parsing header file with a license block
  2015-12-19  2:52   ` Simon Glass
@ 2015-12-21  7:50     ` Bin Meng
  0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21  7:50 UTC (permalink / raw)
  To: u-boot

On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> The microcode header files in the Intel Chief River FSP package have
>> a license comment block. Update the microcode-tool to support parsing
>> it and extract the license text to the .dtsi file.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  tools/microcode-tool.py | 14 ++++++++++++++
>>  1 file changed, 14 insertions(+)
>
> Acked-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/next, thanks!

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 04/10] x86: ivybridge: Add microcode blobs for all the steppings
  2015-12-19  2:52   ` Simon Glass
@ 2015-12-21  7:50     ` Bin Meng
  0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21  7:50 UTC (permalink / raw)
  To: u-boot

On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> This adds microcode blobs created from Intel FSP package for the
>> Chief River platform. They are for all the Ivy Bridge steppings:
>> 306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
>> 306a9 which is already in the U-Boot tree.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/dts/microcode/m12306a2_00000008.dtsi | 554 +++++++++++++++++++++
>>  arch/x86/dts/microcode/m12306a4_00000007.dtsi | 618 +++++++++++++++++++++++
>>  arch/x86/dts/microcode/m12306a5_00000007.dtsi | 618 +++++++++++++++++++++++
>>  arch/x86/dts/microcode/m12306a8_00000010.dtsi | 682 ++++++++++++++++++++++++++
>>  4 files changed, 2472 insertions(+)
>>  create mode 100644 arch/x86/dts/microcode/m12306a2_00000008.dtsi
>>  create mode 100644 arch/x86/dts/microcode/m12306a4_00000007.dtsi
>>  create mode 100644 arch/x86/dts/microcode/m12306a5_00000007.dtsi
>>  create mode 100644 arch/x86/dts/microcode/m12306a8_00000010.dtsi
>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested on link (ivybridge non-FSP)
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/next, thanks!

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 06/10] x86: ivybridge: Do not require HAVE_INTEL_ME
  2015-12-19  2:52   ` Simon Glass
@ 2015-12-21  7:50     ` Bin Meng
  0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21  7:50 UTC (permalink / raw)
  To: u-boot

On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Do not set HAVE_INTEL_ME by default as for some cases Intel ME
>> firmware even does not reside on the same SPI flash as U-Boot.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/ivybridge/Kconfig         | 1 -
>>  board/google/chromebook_link/Kconfig   | 1 +
>>  board/google/chromebox_panther/Kconfig | 1 +
>>  3 files changed, 2 insertions(+), 1 deletion(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested on link (ivybridge non-FSP)
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/next, thanks!

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 08/10] x86: fsp: Always use hex numbers in the hob command output
  2015-12-19  2:52   ` Simon Glass
@ 2015-12-21  7:50     ` Bin Meng
  0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21  7:50 UTC (permalink / raw)
  To: u-boot

On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> In the 'fsp hob' command output, decimal numbers and hexadecimal
>> numbers are used mixedly. Now change to always use hex numbers
>> to keep consistency.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/lib/fsp/cmd_fsp.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/next, thanks!

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 09/10] x86: ivybridge: Add macros for LPC decode ranges
  2015-12-19  2:52   ` Simon Glass
@ 2015-12-21  7:50     ` Bin Meng
  0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-21  7:50 UTC (permalink / raw)
  To: u-boot

On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Add several macros for LPC decode registers on PCH.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/include/asm/arch-ivybridge/pch.h | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested on link (ivybridge non-FSP)
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/next, thanks!

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support
  2015-12-21  2:27     ` Bin Meng
@ 2015-12-23 16:44       ` Simon Glass
  2015-12-23 22:48         ` Bin Meng
  0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2015-12-23 16:44 UTC (permalink / raw)
  To: u-boot

Hi Bin,

On 20 December 2015 at 19:27, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> IvyBridge FSP package is built with a base address at 0xfff80000,
>>> and does not use UPD data region. This adds basic FSP support.
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> ---
>>>
>>>  arch/x86/cpu/ivybridge/Kconfig                     |  8 ++++
>>>  arch/x86/cpu/ivybridge/Makefile                    |  4 ++
>>>  arch/x86/cpu/ivybridge/fsp_configs.c               | 45 ++++++++++++++++++++++
>>>  arch/x86/cpu/ivybridge/ivybridge.c                 | 22 +++++++++++
>>>  .../include/asm/arch-ivybridge/fsp/fsp_configs.h   | 40 +++++++++++++++++++
>>>  arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h  | 12 ++++++
>>>  6 files changed, 131 insertions(+)
>>>  create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
>>>  create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
>>>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
>>>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
>>
>> Acked-by: Simon Glass <sjg@chromium.org>
>> Tested on link (ivybridge non-FSP)
>> Tested-by: Simon Glass <sjg@chromium.org>
>>
>> One question: why do we need an Intel license on this code?
>>
>
> It was a copy and paste from other platform (queensbay and baytrail)
> files. Do you think we should change it to GPLv2+?

Hmm - is it using this license because it was written by Intel, or
because you modified it from the FSP code that was written by Intel?
If so, then I suppose it is reasonable to use the Intel license.

Regards,
Simon

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support
  2015-12-23 16:44       ` Simon Glass
@ 2015-12-23 22:48         ` Bin Meng
  0 siblings, 0 replies; 39+ messages in thread
From: Bin Meng @ 2015-12-23 22:48 UTC (permalink / raw)
  To: u-boot

Hi Simon,

On Thu, Dec 24, 2015 at 12:44 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 20 December 2015 at 19:27, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
>>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>> IvyBridge FSP package is built with a base address at 0xfff80000,
>>>> and does not use UPD data region. This adds basic FSP support.
>>>>
>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>>> ---
>>>>
>>>>  arch/x86/cpu/ivybridge/Kconfig                     |  8 ++++
>>>>  arch/x86/cpu/ivybridge/Makefile                    |  4 ++
>>>>  arch/x86/cpu/ivybridge/fsp_configs.c               | 45 ++++++++++++++++++++++
>>>>  arch/x86/cpu/ivybridge/ivybridge.c                 | 22 +++++++++++
>>>>  .../include/asm/arch-ivybridge/fsp/fsp_configs.h   | 40 +++++++++++++++++++
>>>>  arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h  | 12 ++++++
>>>>  6 files changed, 131 insertions(+)
>>>>  create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c
>>>>  create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c
>>>>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
>>>>  create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
>>>
>>> Acked-by: Simon Glass <sjg@chromium.org>
>>> Tested on link (ivybridge non-FSP)
>>> Tested-by: Simon Glass <sjg@chromium.org>
>>>
>>> One question: why do we need an Intel license on this code?
>>>
>>
>> It was a copy and paste from other platform (queensbay and baytrail)
>> files. Do you think we should change it to GPLv2+?
>
> Hmm - is it using this license because it was written by Intel, or
> because you modified it from the FSP code that was written by Intel?
> If so, then I suppose it is reasonable to use the Intel license.
>

The file was not written by Intel. Current U-Boot implementation is
our own. I will change the license in v2.

Regards,
Bin

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver
  2015-12-21  2:42     ` Bin Meng
@ 2016-01-06  0:24       ` Simon Glass
  2016-01-26  8:29         ` Bin Meng
  0 siblings, 1 reply; 39+ messages in thread
From: Simon Glass @ 2016-01-06  0:24 UTC (permalink / raw)
  To: u-boot

Hi Bin,

On 20 December 2015 at 19:42, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
>> Hi Bin,
>>
>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> The SMSC SIO1007 superio chipset integrates two ns16550 compatible
>>> serial ports for legacy applications, 16 GPIO pins and some other
>>> functionalities like power management.
>>>
>>> This adds a simple driver to enable serial port and handle GPIO.
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> ---
>>>
>>>  drivers/misc/Makefile       |   1 +
>>>  drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++
>>>  include/smsc_sio1007.h      | 115 ++++++++++++++++++++++++++++++++++++++++
>>>  3 files changed, 242 insertions(+)
>>>  create mode 100644 drivers/misc/smsc_sio1007.c
>>>  create mode 100644 include/smsc_sio1007.h
>>>
>>> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
>>> index aa137f5..6952f8ce 100644
>>> --- a/drivers/misc/Makefile
>>> +++ b/drivers/misc/Makefile
>>> @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C
>>>  obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
>>>  endif
>>>  obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
>>> +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
>>>  obj-$(CONFIG_STATUS_LED) += status_led.o
>>>  obj-$(CONFIG_SANDBOX) += swap_case.o
>>>  obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
>>> diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c
>>> new file mode 100644
>>> index 0000000..79e9e15
>>> --- /dev/null
>>> +++ b/drivers/misc/smsc_sio1007.c
>>> @@ -0,0 +1,126 @@
>>> +/*
>>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
>>> + *
>>> + * SPDX-License-Identifier:    GPL-2.0+
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <asm/io.h>
>>> +#include <errno.h>
>>> +#include <smsc_sio1007.h>
>>> +
>>> +static inline u8 sio1007_read(int port, int reg)
>>> +{
>>> +       outb(reg, port);
>>> +
>>> +       return inb(port + 1);
>>> +}
>>> +
>>> +static inline void sio1007_write(int port, int reg, int val)
>>> +{
>>> +       outb(reg, port);
>>> +       outb(val, port + 1);
>>> +}
>>> +
>>> +static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set)
>>> +{
>>> +       sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);
>>> +}
>>> +
>>> +void sio1007_enable_serial(int port, int num, int iobase, int irq)
>>> +{
>>> +       if (num < 0 || num > SIO1007_UART_NUM)
>>> +               return;
>>> +
>>> +       /* enter configuration state */
>>> +       outb(0x55, port);
>>> +
>>> +       /* power on serial port and set up its i/o base & irq */
>>> +       if (!num) {
>>> +               sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);
>>> +               sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);
>>> +               sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);
>>> +       } else {
>>> +               sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);
>>> +               sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);
>>> +               sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);
>>> +       }
>>> +
>>> +       /* exit configuration state */
>>> +       outb(0xaa, port);
>>> +}
>>> +
>>> +void sio1007_enable_runtime(int port, int iobase)
>>> +{
>>> +       /* enter configuration state */
>>> +       outb(0x55, port);
>>> +
>>> +       /* set i/o base for the runtime register block */
>>> +       sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);
>>> +       sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);
>>> +       /* turn on address decoding for this block */
>>> +       sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);
>>> +
>>> +       /* exit configuration state */
>>> +       outb(0xaa, port);
>>> +}
>>> +
>>> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type)
>>> +{
>>> +       int reg = GPIO0_DIR;
>>> +
>>> +       if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>>> +               return;
>>> +       if (gpio >= GPIO_NUM_PER_GROUP) {
>>> +               reg = GPIO1_DIR;
>>> +               gpio -= GPIO_NUM_PER_GROUP;
>>> +       }
>>> +
>>> +       /* enter configuration state */
>>> +       outb(0x55, port);
>>> +
>>> +       /* set gpio pin direction, polority and type */
>>> +       sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);
>>> +       sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);
>>> +       sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);
>>> +
>>> +       /* exit configuration state */
>>> +       outb(0xaa, port);
>>> +}
>>> +
>>> +int sio1007_gpio_get_value(int port, int gpio)
>>> +{
>>> +       int reg = GPIO0_DATA;
>>> +       int val;
>>> +
>>> +       if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>>> +               return -EINVAL;
>>> +       if (gpio >= GPIO_NUM_PER_GROUP) {
>>> +               reg = GPIO1_DATA;
>>> +               gpio -= GPIO_NUM_PER_GROUP;
>>> +       }
>>> +
>>> +       val = inb(port + reg);
>>> +       if (val & (1 << gpio))
>>> +               return 1;
>>> +       else
>>> +               return 0;
>>> +}
>>> +
>>> +void sio1007_gpio_set_value(int port, int gpio, int val)
>>> +{
>>> +       int reg = GPIO0_DATA;
>>> +       u8 data;
>>> +
>>> +       if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>>> +               return;
>>> +       if (gpio >= GPIO_NUM_PER_GROUP) {
>>> +               reg = GPIO1_DATA;
>>> +               gpio -= GPIO_NUM_PER_GROUP;
>>> +       }
>>> +
>>> +       data = inb(port + reg);
>>> +       data &= ~(1 << gpio);
>>> +       data |= (val << gpio);
>>> +       outb(data, port + reg);
>>> +}
>>
>> This should be modeled as a GPIO driver in the GPIO uclass.
>>
>>> diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h
>>> new file mode 100644
>>> index 0000000..eff57a7
>>> --- /dev/null
>>> +++ b/include/smsc_sio1007.h
>>> @@ -0,0 +1,115 @@
>>> +/*
>>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
>>> + *
>>> + * SPDX-License-Identifier:    GPL-2.0+
>>> + */
>>> +
>>> +#ifndef _SMSC_SIO1007_H_
>>> +#define _SMSC_SIO1007_H_
>>> +
>>> +/*
>>> + * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
>>> + * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
>>> + * SYSOPT0 and SYSOPT1 determines one of the following addresses.
>>> + */
>>> +#define SIO1007_IOPORT0                0x002e
>>> +#define SIO1007_IOPORT1                0x004e
>>> +#define SIO1007_IOPORT2                0x162e
>>> +#define SIO1007_IOPORT3                0x164e
>>> +
>>> +/* SIO1007 registers */
>>> +
>>> +#define DEV_POWER_CTRL         0x02
>>> +#define UART1_POWER_ON         (1 << 3)
>>> +#define UART2_POWER_ON         (1 << 7)
>>> +
>>> +#define UART1_IOBASE           0x24
>>> +#define UART2_IOBASE           0x25
>>> +#define UART_IRQ               0x28
>>> +
>>> +#define RTR_IOBASE_HIGH                0x21
>>> +#define RTR_IOBASE_LOW         0x30
>>> +
>>> +#define GPIO0_DIR              0x31
>>> +#define GPIO1_DIR              0x35
>>> +#define GPIO_DIR_INPUT         0
>>> +#define GPIO_DIR_OUTPUT                1
>>> +
>>> +#define GPIO0_POL              0x32
>>> +#define GPIO1_POL              0x36
>>> +#define GPIO_POL_NO_INVERT     0
>>> +#define GPIO_POL_INVERT                1
>>> +
>>> +#define GPIO0_TYPE             0x33
>>> +#define GPIO1_TYPE             0x37
>>> +#define GPIO_TYPE_PUSH_PULL    0
>>> +#define GPIO_TYPE_OPEN_DRAIN   1
>>> +
>>> +#define DEV_ACTIVATE           0x3a
>>> +#define RTR_EN                 (1 << 1)
>>> +
>>> +/* Runtime register offset */
>>> +
>>> +#define GPIO0_DATA             0xc
>>> +#define GPIO1_DATA             0xe
>>> +
>>> +/* Number of serial ports supported */
>>> +#define SIO1007_UART_NUM       2
>>> +
>>> +/* Number of gpio pins supported */
>>> +#define GPIO_NUM_PER_GROUP     8
>>> +#define GPIO_GROUP_NUM         2
>>> +#define SIO1007_GPIO_NUM       (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
>>> +
>>> +/**
>>> + * Configure the I/O port address of the specified serial device and
>>> + * enable the serial device.
>>> + *
>>> + * @port:      SIO1007 I/O port address
>>> + * @num:       serial device number (0 or 1)
>>> + * @iobase:    processor I/O port address to assign to this serial device
>>> + * @irq:       processor IRQ number to assign to this serial device
>>> + */
>>> +void sio1007_enable_serial(int port, int num, int iobase, int irq);
>>
>> I wonder if we need a parent device which provides access to these
>> features, and then a GPIO child device?
>
> I was thinking we create a superio uclass for this, but I found it's
> not generic enough to abstract the ops for this uclass, if we take a
> look at the existing SMSC LPC47M and this new one. Given these
> routines will only need to be called just once during boot up, I
> decided not to use driver model on this type of device.
>

But won't we want to use the 'gpio' command to access these GPIOs?

>>
>>> +
>>> +/**
>>> + * Configure the I/O port address of the runtime register block and
>>> + * enable the address decoding.
>>> + *
>>> + * @port:      SIO1007 I/O port address
>>> + * @iobase:    processor I/O port address to assign to the runtime registers
>>> + */
>>> +void sio1007_enable_runtime(int port, int iobase);
>>> +
>>> +/**
>>> + * Configure the direction/polority/type of a specified GPIO pin
>>> + *
>>> + * @port:      SIO1007 I/O port address
>>> + * @gpio:      GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
>>> + * @dir:       GPIO_DIR_INPUT or GPIO_DIR_OUTPUT
>>> + * @pol:       GPIO_POL_NO_INVERT or GPIO_POL_INVERT
>>> + * @type:      GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN
>>> + */
>>> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type);
>>> +
>>> +/**
>>> + * Get a GPIO pin value.
>>> + * This will work whether the GPIO is an input or an output.
>>> + *
>>> + * @port:      runtime register block I/O port address
>>> + * @gpio:      GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
>>> + * @return:    0 if low, 1 if high, -EINVAL if gpio number is invalid
>>> + */
>>> +int sio1007_gpio_get_value(int port, int gpio);
>>> +
>>> +/**
>>> + * Set a GPIO pin value.
>>> + * This will only work when the GPIO is configured as an output.
>>> + *
>>> + * @port:      runtime register block I/O port address
>>> + * @gpio:      GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
>>> + * @val:       0 if low, 1 if high
>>> + */
>>> +void sio1007_gpio_set_value(int port, int gpio, int val);
>>> +
>>> +#endif /* _SMSC_SIO1007_H_ */
>>> --
>>> 1.8.2.1
>>>
>
> Regards,
> Bin

Regards,
Simon

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver
  2016-01-06  0:24       ` Simon Glass
@ 2016-01-26  8:29         ` Bin Meng
  2016-01-26 17:03           ` Simon Glass
  0 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2016-01-26  8:29 UTC (permalink / raw)
  To: u-boot

Hi Simon,

On Wed, Jan 6, 2016 at 8:24 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 20 December 2015 at 19:42, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
>>> Hi Bin,
>>>
>>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>> The SMSC SIO1007 superio chipset integrates two ns16550 compatible
>>>> serial ports for legacy applications, 16 GPIO pins and some other
>>>> functionalities like power management.
>>>>
>>>> This adds a simple driver to enable serial port and handle GPIO.
>>>>
>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>>> ---
>>>>
>>>>  drivers/misc/Makefile       |   1 +
>>>>  drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++
>>>>  include/smsc_sio1007.h      | 115 ++++++++++++++++++++++++++++++++++++++++
>>>>  3 files changed, 242 insertions(+)
>>>>  create mode 100644 drivers/misc/smsc_sio1007.c
>>>>  create mode 100644 include/smsc_sio1007.h
>>>>
>>>> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
>>>> index aa137f5..6952f8ce 100644
>>>> --- a/drivers/misc/Makefile
>>>> +++ b/drivers/misc/Makefile
>>>> @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C
>>>>  obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
>>>>  endif
>>>>  obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
>>>> +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
>>>>  obj-$(CONFIG_STATUS_LED) += status_led.o
>>>>  obj-$(CONFIG_SANDBOX) += swap_case.o
>>>>  obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
>>>> diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c
>>>> new file mode 100644
>>>> index 0000000..79e9e15
>>>> --- /dev/null
>>>> +++ b/drivers/misc/smsc_sio1007.c
>>>> @@ -0,0 +1,126 @@
>>>> +/*
>>>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
>>>> + *
>>>> + * SPDX-License-Identifier:    GPL-2.0+
>>>> + */
>>>> +
>>>> +#include <common.h>
>>>> +#include <asm/io.h>
>>>> +#include <errno.h>
>>>> +#include <smsc_sio1007.h>
>>>> +
>>>> +static inline u8 sio1007_read(int port, int reg)
>>>> +{
>>>> +       outb(reg, port);
>>>> +
>>>> +       return inb(port + 1);
>>>> +}
>>>> +
>>>> +static inline void sio1007_write(int port, int reg, int val)
>>>> +{
>>>> +       outb(reg, port);
>>>> +       outb(val, port + 1);
>>>> +}
>>>> +
>>>> +static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set)
>>>> +{
>>>> +       sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);
>>>> +}
>>>> +
>>>> +void sio1007_enable_serial(int port, int num, int iobase, int irq)
>>>> +{
>>>> +       if (num < 0 || num > SIO1007_UART_NUM)
>>>> +               return;
>>>> +
>>>> +       /* enter configuration state */
>>>> +       outb(0x55, port);
>>>> +
>>>> +       /* power on serial port and set up its i/o base & irq */
>>>> +       if (!num) {
>>>> +               sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);
>>>> +               sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);
>>>> +               sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);
>>>> +       } else {
>>>> +               sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);
>>>> +               sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);
>>>> +               sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);
>>>> +       }
>>>> +
>>>> +       /* exit configuration state */
>>>> +       outb(0xaa, port);
>>>> +}
>>>> +
>>>> +void sio1007_enable_runtime(int port, int iobase)
>>>> +{
>>>> +       /* enter configuration state */
>>>> +       outb(0x55, port);
>>>> +
>>>> +       /* set i/o base for the runtime register block */
>>>> +       sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);
>>>> +       sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);
>>>> +       /* turn on address decoding for this block */
>>>> +       sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);
>>>> +
>>>> +       /* exit configuration state */
>>>> +       outb(0xaa, port);
>>>> +}
>>>> +
>>>> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type)
>>>> +{
>>>> +       int reg = GPIO0_DIR;
>>>> +
>>>> +       if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>>>> +               return;
>>>> +       if (gpio >= GPIO_NUM_PER_GROUP) {
>>>> +               reg = GPIO1_DIR;
>>>> +               gpio -= GPIO_NUM_PER_GROUP;
>>>> +       }
>>>> +
>>>> +       /* enter configuration state */
>>>> +       outb(0x55, port);
>>>> +
>>>> +       /* set gpio pin direction, polority and type */
>>>> +       sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);
>>>> +       sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);
>>>> +       sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);
>>>> +
>>>> +       /* exit configuration state */
>>>> +       outb(0xaa, port);
>>>> +}
>>>> +
>>>> +int sio1007_gpio_get_value(int port, int gpio)
>>>> +{
>>>> +       int reg = GPIO0_DATA;
>>>> +       int val;
>>>> +
>>>> +       if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>>>> +               return -EINVAL;
>>>> +       if (gpio >= GPIO_NUM_PER_GROUP) {
>>>> +               reg = GPIO1_DATA;
>>>> +               gpio -= GPIO_NUM_PER_GROUP;
>>>> +       }
>>>> +
>>>> +       val = inb(port + reg);
>>>> +       if (val & (1 << gpio))
>>>> +               return 1;
>>>> +       else
>>>> +               return 0;
>>>> +}
>>>> +
>>>> +void sio1007_gpio_set_value(int port, int gpio, int val)
>>>> +{
>>>> +       int reg = GPIO0_DATA;
>>>> +       u8 data;
>>>> +
>>>> +       if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
>>>> +               return;
>>>> +       if (gpio >= GPIO_NUM_PER_GROUP) {
>>>> +               reg = GPIO1_DATA;
>>>> +               gpio -= GPIO_NUM_PER_GROUP;
>>>> +       }
>>>> +
>>>> +       data = inb(port + reg);
>>>> +       data &= ~(1 << gpio);
>>>> +       data |= (val << gpio);
>>>> +       outb(data, port + reg);
>>>> +}
>>>
>>> This should be modeled as a GPIO driver in the GPIO uclass.
>>>
>>>> diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h
>>>> new file mode 100644
>>>> index 0000000..eff57a7
>>>> --- /dev/null
>>>> +++ b/include/smsc_sio1007.h
>>>> @@ -0,0 +1,115 @@
>>>> +/*
>>>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
>>>> + *
>>>> + * SPDX-License-Identifier:    GPL-2.0+
>>>> + */
>>>> +
>>>> +#ifndef _SMSC_SIO1007_H_
>>>> +#define _SMSC_SIO1007_H_
>>>> +
>>>> +/*
>>>> + * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
>>>> + * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
>>>> + * SYSOPT0 and SYSOPT1 determines one of the following addresses.
>>>> + */
>>>> +#define SIO1007_IOPORT0                0x002e
>>>> +#define SIO1007_IOPORT1                0x004e
>>>> +#define SIO1007_IOPORT2                0x162e
>>>> +#define SIO1007_IOPORT3                0x164e
>>>> +
>>>> +/* SIO1007 registers */
>>>> +
>>>> +#define DEV_POWER_CTRL         0x02
>>>> +#define UART1_POWER_ON         (1 << 3)
>>>> +#define UART2_POWER_ON         (1 << 7)
>>>> +
>>>> +#define UART1_IOBASE           0x24
>>>> +#define UART2_IOBASE           0x25
>>>> +#define UART_IRQ               0x28
>>>> +
>>>> +#define RTR_IOBASE_HIGH                0x21
>>>> +#define RTR_IOBASE_LOW         0x30
>>>> +
>>>> +#define GPIO0_DIR              0x31
>>>> +#define GPIO1_DIR              0x35
>>>> +#define GPIO_DIR_INPUT         0
>>>> +#define GPIO_DIR_OUTPUT                1
>>>> +
>>>> +#define GPIO0_POL              0x32
>>>> +#define GPIO1_POL              0x36
>>>> +#define GPIO_POL_NO_INVERT     0
>>>> +#define GPIO_POL_INVERT                1
>>>> +
>>>> +#define GPIO0_TYPE             0x33
>>>> +#define GPIO1_TYPE             0x37
>>>> +#define GPIO_TYPE_PUSH_PULL    0
>>>> +#define GPIO_TYPE_OPEN_DRAIN   1
>>>> +
>>>> +#define DEV_ACTIVATE           0x3a
>>>> +#define RTR_EN                 (1 << 1)
>>>> +
>>>> +/* Runtime register offset */
>>>> +
>>>> +#define GPIO0_DATA             0xc
>>>> +#define GPIO1_DATA             0xe
>>>> +
>>>> +/* Number of serial ports supported */
>>>> +#define SIO1007_UART_NUM       2
>>>> +
>>>> +/* Number of gpio pins supported */
>>>> +#define GPIO_NUM_PER_GROUP     8
>>>> +#define GPIO_GROUP_NUM         2
>>>> +#define SIO1007_GPIO_NUM       (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
>>>> +
>>>> +/**
>>>> + * Configure the I/O port address of the specified serial device and
>>>> + * enable the serial device.
>>>> + *
>>>> + * @port:      SIO1007 I/O port address
>>>> + * @num:       serial device number (0 or 1)
>>>> + * @iobase:    processor I/O port address to assign to this serial device
>>>> + * @irq:       processor IRQ number to assign to this serial device
>>>> + */
>>>> +void sio1007_enable_serial(int port, int num, int iobase, int irq);
>>>
>>> I wonder if we need a parent device which provides access to these
>>> features, and then a GPIO child device?
>>
>> I was thinking we create a superio uclass for this, but I found it's
>> not generic enough to abstract the ops for this uclass, if we take a
>> look at the existing SMSC LPC47M and this new one. Given these
>> routines will only need to be called just once during boot up, I
>> decided not to use driver model on this type of device.
>>
>
> But won't we want to use the 'gpio' command to access these GPIOs?
>

I don't see value of accessing them after boot. Also as you can see,
these superio chipsets are really not good candidates to model. To
operate on a specific GPIO pin, we need access two IO ports which
looks quite weird, but unfortunately that is how the chipset was
designed :(

[snip]

Regards,
Bin

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver
  2016-01-26  8:29         ` Bin Meng
@ 2016-01-26 17:03           ` Simon Glass
  0 siblings, 0 replies; 39+ messages in thread
From: Simon Glass @ 2016-01-26 17:03 UTC (permalink / raw)
  To: u-boot

Hi Bin,

On 26 January 2016 at 01:29, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Wed, Jan 6, 2016 at 8:24 AM, Simon Glass <sjg@chromium.org> wrote:
> > Hi Bin,
> >
> > On 20 December 2015 at 19:42, Bin Meng <bmeng.cn@gmail.com> wrote:
> >> Hi Simon,
> >>
> >> On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass <sjg@chromium.org> wrote:
> >>> Hi Bin,
> >>>
> >>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
> >>>> The SMSC SIO1007 superio chipset integrates two ns16550 compatible
> >>>> serial ports for legacy applications, 16 GPIO pins and some other
> >>>> functionalities like power management.
> >>>>
> >>>> This adds a simple driver to enable serial port and handle GPIO.
> >>>>
> >>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> >>>> ---
> >>>>
> >>>>  drivers/misc/Makefile       |   1 +
> >>>>  drivers/misc/smsc_sio1007.c | 126 ++++++++++++++++++++++++++++++++++++++++++++
> >>>>  include/smsc_sio1007.h      | 115 ++++++++++++++++++++++++++++++++++++++++
> >>>>  3 files changed, 242 insertions(+)
> >>>>  create mode 100644 drivers/misc/smsc_sio1007.c
> >>>>  create mode 100644 include/smsc_sio1007.h
> >>>>
> >>>> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> >>>> index aa137f5..6952f8ce 100644
> >>>> --- a/drivers/misc/Makefile
> >>>> +++ b/drivers/misc/Makefile
> >>>> @@ -29,6 +29,7 @@ ifdef CONFIG_DM_I2C
> >>>>  obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
> >>>>  endif
> >>>>  obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
> >>>> +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
> >>>>  obj-$(CONFIG_STATUS_LED) += status_led.o
> >>>>  obj-$(CONFIG_SANDBOX) += swap_case.o
> >>>>  obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
> >>>> diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c
> >>>> new file mode 100644
> >>>> index 0000000..79e9e15
> >>>> --- /dev/null
> >>>> +++ b/drivers/misc/smsc_sio1007.c
> >>>> @@ -0,0 +1,126 @@
> >>>> +/*
> >>>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
> >>>> + *
> >>>> + * SPDX-License-Identifier:    GPL-2.0+
> >>>> + */
> >>>> +
> >>>> +#include <common.h>
> >>>> +#include <asm/io.h>
> >>>> +#include <errno.h>
> >>>> +#include <smsc_sio1007.h>
> >>>> +
> >>>> +static inline u8 sio1007_read(int port, int reg)
> >>>> +{
> >>>> +       outb(reg, port);
> >>>> +
> >>>> +       return inb(port + 1);
> >>>> +}
> >>>> +
> >>>> +static inline void sio1007_write(int port, int reg, int val)
> >>>> +{
> >>>> +       outb(reg, port);
> >>>> +       outb(val, port + 1);
> >>>> +}
> >>>> +
> >>>> +static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set)
> >>>> +{
> >>>> +       sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);
> >>>> +}
> >>>> +
> >>>> +void sio1007_enable_serial(int port, int num, int iobase, int irq)
> >>>> +{
> >>>> +       if (num < 0 || num > SIO1007_UART_NUM)
> >>>> +               return;
> >>>> +
> >>>> +       /* enter configuration state */
> >>>> +       outb(0x55, port);
> >>>> +
> >>>> +       /* power on serial port and set up its i/o base & irq */
> >>>> +       if (!num) {
> >>>> +               sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);
> >>>> +               sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);
> >>>> +               sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);
> >>>> +       } else {
> >>>> +               sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);
> >>>> +               sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);
> >>>> +               sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);
> >>>> +       }
> >>>> +
> >>>> +       /* exit configuration state */
> >>>> +       outb(0xaa, port);
> >>>> +}
> >>>> +
> >>>> +void sio1007_enable_runtime(int port, int iobase)
> >>>> +{
> >>>> +       /* enter configuration state */
> >>>> +       outb(0x55, port);
> >>>> +
> >>>> +       /* set i/o base for the runtime register block */
> >>>> +       sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);
> >>>> +       sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);
> >>>> +       /* turn on address decoding for this block */
> >>>> +       sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);
> >>>> +
> >>>> +       /* exit configuration state */
> >>>> +       outb(0xaa, port);
> >>>> +}
> >>>> +
> >>>> +void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type)
> >>>> +{
> >>>> +       int reg = GPIO0_DIR;
> >>>> +
> >>>> +       if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
> >>>> +               return;
> >>>> +       if (gpio >= GPIO_NUM_PER_GROUP) {
> >>>> +               reg = GPIO1_DIR;
> >>>> +               gpio -= GPIO_NUM_PER_GROUP;
> >>>> +       }
> >>>> +
> >>>> +       /* enter configuration state */
> >>>> +       outb(0x55, port);
> >>>> +
> >>>> +       /* set gpio pin direction, polority and type */
> >>>> +       sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);
> >>>> +       sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);
> >>>> +       sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);
> >>>> +
> >>>> +       /* exit configuration state */
> >>>> +       outb(0xaa, port);
> >>>> +}
> >>>> +
> >>>> +int sio1007_gpio_get_value(int port, int gpio)
> >>>> +{
> >>>> +       int reg = GPIO0_DATA;
> >>>> +       int val;
> >>>> +
> >>>> +       if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
> >>>> +               return -EINVAL;
> >>>> +       if (gpio >= GPIO_NUM_PER_GROUP) {
> >>>> +               reg = GPIO1_DATA;
> >>>> +               gpio -= GPIO_NUM_PER_GROUP;
> >>>> +       }
> >>>> +
> >>>> +       val = inb(port + reg);
> >>>> +       if (val & (1 << gpio))
> >>>> +               return 1;
> >>>> +       else
> >>>> +               return 0;
> >>>> +}
> >>>> +
> >>>> +void sio1007_gpio_set_value(int port, int gpio, int val)
> >>>> +{
> >>>> +       int reg = GPIO0_DATA;
> >>>> +       u8 data;
> >>>> +
> >>>> +       if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
> >>>> +               return;
> >>>> +       if (gpio >= GPIO_NUM_PER_GROUP) {
> >>>> +               reg = GPIO1_DATA;
> >>>> +               gpio -= GPIO_NUM_PER_GROUP;
> >>>> +       }
> >>>> +
> >>>> +       data = inb(port + reg);
> >>>> +       data &= ~(1 << gpio);
> >>>> +       data |= (val << gpio);
> >>>> +       outb(data, port + reg);
> >>>> +}
> >>>
> >>> This should be modeled as a GPIO driver in the GPIO uclass.
> >>>
> >>>> diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h
> >>>> new file mode 100644
> >>>> index 0000000..eff57a7
> >>>> --- /dev/null
> >>>> +++ b/include/smsc_sio1007.h
> >>>> @@ -0,0 +1,115 @@
> >>>> +/*
> >>>> + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
> >>>> + *
> >>>> + * SPDX-License-Identifier:    GPL-2.0+
> >>>> + */
> >>>> +
> >>>> +#ifndef _SMSC_SIO1007_H_
> >>>> +#define _SMSC_SIO1007_H_
> >>>> +
> >>>> +/*
> >>>> + * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
> >>>> + * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
> >>>> + * SYSOPT0 and SYSOPT1 determines one of the following addresses.
> >>>> + */
> >>>> +#define SIO1007_IOPORT0                0x002e
> >>>> +#define SIO1007_IOPORT1                0x004e
> >>>> +#define SIO1007_IOPORT2                0x162e
> >>>> +#define SIO1007_IOPORT3                0x164e
> >>>> +
> >>>> +/* SIO1007 registers */
> >>>> +
> >>>> +#define DEV_POWER_CTRL         0x02
> >>>> +#define UART1_POWER_ON         (1 << 3)
> >>>> +#define UART2_POWER_ON         (1 << 7)
> >>>> +
> >>>> +#define UART1_IOBASE           0x24
> >>>> +#define UART2_IOBASE           0x25
> >>>> +#define UART_IRQ               0x28
> >>>> +
> >>>> +#define RTR_IOBASE_HIGH                0x21
> >>>> +#define RTR_IOBASE_LOW         0x30
> >>>> +
> >>>> +#define GPIO0_DIR              0x31
> >>>> +#define GPIO1_DIR              0x35
> >>>> +#define GPIO_DIR_INPUT         0
> >>>> +#define GPIO_DIR_OUTPUT                1
> >>>> +
> >>>> +#define GPIO0_POL              0x32
> >>>> +#define GPIO1_POL              0x36
> >>>> +#define GPIO_POL_NO_INVERT     0
> >>>> +#define GPIO_POL_INVERT                1
> >>>> +
> >>>> +#define GPIO0_TYPE             0x33
> >>>> +#define GPIO1_TYPE             0x37
> >>>> +#define GPIO_TYPE_PUSH_PULL    0
> >>>> +#define GPIO_TYPE_OPEN_DRAIN   1
> >>>> +
> >>>> +#define DEV_ACTIVATE           0x3a
> >>>> +#define RTR_EN                 (1 << 1)
> >>>> +
> >>>> +/* Runtime register offset */
> >>>> +
> >>>> +#define GPIO0_DATA             0xc
> >>>> +#define GPIO1_DATA             0xe
> >>>> +
> >>>> +/* Number of serial ports supported */
> >>>> +#define SIO1007_UART_NUM       2
> >>>> +
> >>>> +/* Number of gpio pins supported */
> >>>> +#define GPIO_NUM_PER_GROUP     8
> >>>> +#define GPIO_GROUP_NUM         2
> >>>> +#define SIO1007_GPIO_NUM       (GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
> >>>> +
> >>>> +/**
> >>>> + * Configure the I/O port address of the specified serial device and
> >>>> + * enable the serial device.
> >>>> + *
> >>>> + * @port:      SIO1007 I/O port address
> >>>> + * @num:       serial device number (0 or 1)
> >>>> + * @iobase:    processor I/O port address to assign to this serial device
> >>>> + * @irq:       processor IRQ number to assign to this serial device
> >>>> + */
> >>>> +void sio1007_enable_serial(int port, int num, int iobase, int irq);
> >>>
> >>> I wonder if we need a parent device which provides access to these
> >>> features, and then a GPIO child device?
> >>
> >> I was thinking we create a superio uclass for this, but I found it's
> >> not generic enough to abstract the ops for this uclass, if we take a
> >> look at the existing SMSC LPC47M and this new one. Given these
> >> routines will only need to be called just once during boot up, I
> >> decided not to use driver model on this type of device.
> >>
> >
> > But won't we want to use the 'gpio' command to access these GPIOs?
> >
>
> I don't see value of accessing them after boot. Also as you can see,
> these superio chipsets are really not good candidates to model. To
> operate on a specific GPIO pin, we need access two IO ports which
> looks quite weird, but unfortunately that is how the chipset was
> designed :(

I'm not sure why the access method matters, and I don't understand why
a GPIO would only be used on boot. But clearly you do, so I'm OK with
it.

>
> [snip]
>
> Regards,
> Bin

Regards,
Simon

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP
  2015-12-21  2:33     ` Bin Meng
@ 2016-02-06  4:29       ` Bin Meng
  2016-02-19 20:56         ` Simon Glass
  0 siblings, 1 reply; 39+ messages in thread
From: Bin Meng @ 2016-02-06  4:29 UTC (permalink / raw)
  To: u-boot

Hi Simon,

On Mon, Dec 21, 2015 at 10:33 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Sat, Dec 19, 2015 at 10:51 AM, Simon Glass <sjg@chromium.org> wrote:
>> Hi Bin,
>>
>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> ---
>>>
>>>  include/fdtdec.h | 1 +
>>>  lib/fdtdec.c     | 1 +
>>>  2 files changed, 2 insertions(+)
>>>
>>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>>> index 7fe657d..c515a3c 100644
>>> --- a/include/fdtdec.h
>>> +++ b/include/fdtdec.h
>>> @@ -169,6 +169,7 @@ enum fdt_compat_id {
>>>         COMPAT_ALTERA_SOCFPGA_DWMMC,    /* SoCFPGA DWMMC controller */
>>>         COMPAT_INTEL_BAYTRAIL_FSP,      /* Intel Bay Trail FSP */
>>>         COMPAT_INTEL_BAYTRAIL_FSP_MDP,  /* Intel FSP memory-down params */
>>> +       COMPAT_INTEL_IVYBRIDGE_FSP,     /* Intel Ivy Bridge FSP */
>>>
>>>         COMPAT_COUNT,
>>>  };
>>> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
>>> index 82d0090..002594d 100644
>>> --- a/lib/fdtdec.c
>>> +++ b/lib/fdtdec.c
>>> @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
>>>         COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
>>>         COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
>>>         COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
>>> +       COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
>>>  };
>>>
>>>  const char *fdtdec_get_compatible(enum fdt_compat_id id)
>>> --
>>> 1.8.2.1
>>>
>>
>> Acked-by: Simon Glass <sjg@chromium.org>
>> Tested on link (ivybridge non-FSP)
>> Tested-by: Simon Glass <sjg@chromium.org>
>>
>> We should create an FSP uclass I think.
>
> Maybe, I will add this in my todo list for next release.
>

I looked into the FSP uclass today. Looks if want to do this, we have
to move x86_fsp_init() call to a much later phase, ie: after
initf_dm() is called. I am afraid this does not bring us a bigger
benefits. What do you think?

Regards,
Bin

^ permalink raw reply	[flat|nested] 39+ messages in thread

* [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP
  2016-02-06  4:29       ` Bin Meng
@ 2016-02-19 20:56         ` Simon Glass
  0 siblings, 0 replies; 39+ messages in thread
From: Simon Glass @ 2016-02-19 20:56 UTC (permalink / raw)
  To: u-boot

Hi Bin,

On 5 February 2016 at 21:29, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Mon, Dec 21, 2015 at 10:33 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Sat, Dec 19, 2015 at 10:51 AM, Simon Glass <sjg@chromium.org> wrote:
>>> Hi Bin,
>>>
>>> On 11 December 2015 at 03:55, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>> Use "intel,ivybridge-fsp" for Intel IvyBridge FSP compatible string.
>>>>
>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>>> ---
>>>>
>>>>  include/fdtdec.h | 1 +
>>>>  lib/fdtdec.c     | 1 +
>>>>  2 files changed, 2 insertions(+)
>>>>
>>>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>>>> index 7fe657d..c515a3c 100644
>>>> --- a/include/fdtdec.h
>>>> +++ b/include/fdtdec.h
>>>> @@ -169,6 +169,7 @@ enum fdt_compat_id {
>>>>         COMPAT_ALTERA_SOCFPGA_DWMMC,    /* SoCFPGA DWMMC controller */
>>>>         COMPAT_INTEL_BAYTRAIL_FSP,      /* Intel Bay Trail FSP */
>>>>         COMPAT_INTEL_BAYTRAIL_FSP_MDP,  /* Intel FSP memory-down params */
>>>> +       COMPAT_INTEL_IVYBRIDGE_FSP,     /* Intel Ivy Bridge FSP */
>>>>
>>>>         COMPAT_COUNT,
>>>>  };
>>>> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
>>>> index 82d0090..002594d 100644
>>>> --- a/lib/fdtdec.c
>>>> +++ b/lib/fdtdec.c
>>>> @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
>>>>         COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
>>>>         COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
>>>>         COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
>>>> +       COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
>>>>  };
>>>>
>>>>  const char *fdtdec_get_compatible(enum fdt_compat_id id)
>>>> --
>>>> 1.8.2.1
>>>>
>>>
>>> Acked-by: Simon Glass <sjg@chromium.org>
>>> Tested on link (ivybridge non-FSP)
>>> Tested-by: Simon Glass <sjg@chromium.org>
>>>
>>> We should create an FSP uclass I think.
>>
>> Maybe, I will add this in my todo list for next release.
>>
>
> I looked into the FSP uclass today. Looks if want to do this, we have
> to move x86_fsp_init() call to a much later phase, ie: after
> initf_dm() is called. I am afraid this does not bring us a bigger
> benefits. What do you think?

Yes I suspect you are right. But we do want eventually move all this
compat stuff into drivers. I'm not sure sure of the best approach yet.
Let's keep an eye on it.

Regards,
Simon

^ permalink raw reply	[flat|nested] 39+ messages in thread

end of thread, other threads:[~2016-02-19 20:56 UTC | newest]

Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-12-11 10:55 [U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support Bin Meng
2015-12-11 10:55 ` [U-Boot] [PATCH 01/10] fdtdec: Add compatible string for Intel IvyBridge FSP Bin Meng
2015-12-19  2:51   ` Simon Glass
2015-12-21  2:33     ` Bin Meng
2016-02-06  4:29       ` Bin Meng
2016-02-19 20:56         ` Simon Glass
2015-12-21  7:50     ` Bin Meng
2015-12-11 10:55 ` [U-Boot] [PATCH 02/10] x86: ivybridge: Add FSP support Bin Meng
2015-12-19  2:52   ` Simon Glass
2015-12-21  2:27     ` Bin Meng
2015-12-23 16:44       ` Simon Glass
2015-12-23 22:48         ` Bin Meng
2015-12-11 10:55 ` [U-Boot] [PATCH 03/10] tools: microcode-tool: Support parsing header file with a license block Bin Meng
2015-12-19  2:52   ` Simon Glass
2015-12-21  7:50     ` Bin Meng
2015-12-11 10:55 ` [U-Boot] [PATCH 04/10] x86: ivybridge: Add microcode blobs for all the steppings Bin Meng
2015-12-19  2:52   ` Simon Glass
2015-12-21  7:50     ` Bin Meng
2015-12-11 10:55 ` [U-Boot] [PATCH 05/10] superio: Add SMSC SIO1007 driver Bin Meng
2015-12-19  2:52   ` Simon Glass
2015-12-21  2:42     ` Bin Meng
2016-01-06  0:24       ` Simon Glass
2016-01-26  8:29         ` Bin Meng
2016-01-26 17:03           ` Simon Glass
2015-12-11 10:55 ` [U-Boot] [PATCH 06/10] x86: ivybridge: Do not require HAVE_INTEL_ME Bin Meng
2015-12-19  2:52   ` Simon Glass
2015-12-21  7:50     ` Bin Meng
2015-12-11 10:55 ` [U-Boot] [PATCH 07/10] x86: fsp: Make sure HOB list is not overwritten by U-Boot Bin Meng
2015-12-19  2:52   ` Simon Glass
2015-12-21  2:36     ` Bin Meng
2015-12-11 10:55 ` [U-Boot] [PATCH 08/10] x86: fsp: Always use hex numbers in the hob command output Bin Meng
2015-12-19  2:52   ` Simon Glass
2015-12-21  7:50     ` Bin Meng
2015-12-11 10:55 ` [U-Boot] [PATCH 09/10] x86: ivybridge: Add macros for LPC decode ranges Bin Meng
2015-12-19  2:52   ` Simon Glass
2015-12-21  7:50     ` Bin Meng
2015-12-11 10:55 ` [U-Boot] [PATCH 10/10] x86: Add Intel Cougar Canyon 2 board Bin Meng
2015-12-19  2:52   ` Simon Glass
2015-12-21  2:34     ` Bin Meng

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