From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37307) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zs3YG-0004Ds-Hj for qemu-devel@nongnu.org; Fri, 30 Oct 2015 02:52:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zs3YF-0002fd-7Y for qemu-devel@nongnu.org; Fri, 30 Oct 2015 02:52:40 -0400 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]:36381) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zs3YE-0002fZ-U5 for qemu-devel@nongnu.org; Fri, 30 Oct 2015 02:52:39 -0400 Received: by wmec75 with SMTP id c75so4572399wme.1 for ; Thu, 29 Oct 2015 23:52:38 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: Date: Thu, 29 Oct 2015 23:52:38 -0700 Message-ID: From: Peter Crosthwaite Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v1 00/15] data-driven device registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alistair Francis , Peter Maydell Cc: Edgar Iglesias , Edgar Iglesias , "qemu-devel@nongnu.org Developers" , =?UTF-8?Q?Andreas_F=C3=A4rber?= Ping^3 This has been on list for a very long time without 3rd party review. Can I send a PULL? Regards, Peter On Wed, Oct 14, 2015 at 11:42 AM, Alistair Francis wrote: > Ping^2 > > On Thu, Aug 27, 2015 at 2:47 PM, Alistair Francis > wrote: >> Ping! >> >> On Wed, Jul 29, 2015 at 1:24 PM, Alistair Francis >> wrote: >>> From Peter: >>> Hi All. This is a new scheme I've come up with handling device registers in a >>> data driven way. My motivation for this is to factor out a lot of the access >>> checking that seems to be replicated in every device. See P1 commit message for >>> further discussion. >>> >>> P1 is the main patch, adds the register definition functionality >>> P2-3,6 add helpers that glue the register API to the Memory API >>> P4 Defines a set of macros that minimise register and field definitions >>> P5 is QOMfication >>> P7 is a trivial >>> P10-13 Work up to GPIO support >>> P8,9,14 add new devices (the Xilinx Zynq devcfg & ZynqMP SLCR) that use this >>> scheme. >>> P15: Connect the ZynqMP SLCR device >>> >>> This Zynq devcfg device was particularly finnicky with per-bit restrictions. >>> I'm also looking for a higher-than-usual modelling fidelity >>> on the register space, with semantics defined for random reserved bits >>> in-between otherwise consistent fields. >>> >>> Here's an example of the qemu_log output for the devcfg device. This is produced >>> by now generic sharable code: >>> >>> /machine/unattached/device[44]:Addr 0x000008:CFG: write of value 00000508 >>> /machine/unattached/device[44]:Addr 0x000080:MCTRL: write of value 00800010 >>> /machine/unattached/device[44]:Addr 0x000010:INT_MASK: write of value ffffffff >>> /machine/unattached/device[44]:Addr 00000000:CTRL: write of value 0c00607f >>> >>> And an example of a rogue guest banging on a bad bit: >>> >>> /machine/unattached/device[44]:Addr 0x000014:STATUS bits 0x000001 may not be \ >>> written to 1 >>> >>> A future feature I am interested in is implementing TCG optimisation of >>> side-effectless registers. The register API allows clear definition of >>> what registers have txn side effects and which ones don't. You could even >>> go a step further and translate such side-effectless accesses based on the >>> data pointer for the register. >>> >>> Changes since RFC: >>> - Connect the ZynqMP IOU SLCR device >>> - Rebase >>> >>> Changed from RFC v4: >>> Rebased >>> Added QOMification >>> Added GPIO support >>> Refactored Devcfg device to use FIELD/REG/EX macros. >>> Update style of devcfg device >>> Added init_block help. >>> Changed from v3: >>> Rebased >>> Added reserved bits. >>> Cleaner separation of decode and access components (Patch 3) >>> Changed from v2: >>> Fixed for hw/ re-orginisation (Paolo review) >>> Simplified and optimized (PMM and Gerd review) >>> Changed from v1: >>> Added ONES macro patch >>> Dropped bogus former patch 1 (PMM review) >>> Addressed Blue, Gerd and MST comments. >>> Simplified to be more Memory API compatible. >>> Added Memory API helpers. >>> Please see discussion already on list and commit msgs for more detail. >>> >>> >>> Alistair Francis (1): >>> xlnx-zynqmp: Connect the ZynqMP IOU SLCR >>> >>> Peter Crosthwaite (14): >>> register: Add Register API >>> register: Add Memory API glue >>> register: Add support for decoding information >>> register: Define REG and FIELD macros >>> register: QOMify >>> register: Add block initialise helper >>> bitops: Add ONES macro >>> dma: Add Xilinx Zynq devcfg device model >>> xilinx_zynq: add devcfg to machine model >>> qdev: Define qdev_get_gpio_out >>> qdev: Add qdev_pass_all_gpios API >>> irq: Add opaque setter routine >>> register: Add GPIO API >>> misc: Introduce ZynqMP IOU SLCR >>> >>> default-configs/arm-softmmu.mak | 1 + >>> hw/arm/xilinx_zynq.c | 8 + >>> hw/arm/xlnx-zynqmp.c | 15 ++ >>> hw/core/Makefile.objs | 1 + >>> hw/core/irq.c | 5 + >>> hw/core/qdev.c | 21 ++ >>> hw/core/register.c | 390 ++++++++++++++++++++++++++++++ >>> hw/dma/Makefile.objs | 1 + >>> hw/dma/xlnx-zynq-devcfg.c | 406 ++++++++++++++++++++++++++++++++ >>> hw/misc/Makefile.objs | 1 + >>> hw/misc/xlnx-zynqmp-iou-slcr.c | 113 +++++++++ >>> include/hw/arm/xlnx-zynqmp.h | 2 + >>> include/hw/dma/xlnx-zynq-devcfg.h | 62 +++++ >>> include/hw/irq.h | 2 + >>> include/hw/misc/xlnx-zynqmp-iou-slcr.h | 47 ++++ >>> include/hw/qdev-core.h | 3 + >>> include/hw/register.h | 274 +++++++++++++++++++++ >>> include/qemu/bitops.h | 2 + >>> 18 files changed, 1354 insertions(+), 0 deletions(-) >>> create mode 100644 hw/core/register.c >>> create mode 100644 hw/dma/xlnx-zynq-devcfg.c >>> create mode 100644 hw/misc/xlnx-zynqmp-iou-slcr.c >>> create mode 100644 include/hw/dma/xlnx-zynq-devcfg.h >>> create mode 100644 include/hw/misc/xlnx-zynqmp-iou-slcr.h >>> create mode 100644 include/hw/register.h >>> >>>