From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rajeshwari Birje Date: Wed, 13 Nov 2013 11:34:08 +0530 Subject: [U-Boot] [PATCH 05/10 V6] Exynos5420: Add support for 5420 in pinmux and gpio In-Reply-To: References: <1383031393-6093-1-git-send-email-rajeshwari.s@samsung.com> <1383031393-6093-6-git-send-email-rajeshwari.s@samsung.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Minkyu Kang, Thank you for comments. On Wed, Nov 13, 2013 at 8:31 AM, Minkyu Kang wrote: > Dear Rajeshwari S Shinde, > > > On 29 October 2013 16:23, Rajeshwari S Shinde wrote: > >> Adds code in pinmux and gpio framework to support Exynos5420. >> >> Signed-off-by: Naveen Krishna Chatradhi >> Signed-off-by: Akshay Saraswat >> Signed-off-by: Rajeshwari S Shinde >> Acked-by: Simon Glass >> --- >> Changes in V2: >> - None >> Changes in V3: >> - None >> Changes in V4: >> - Added correct calculation of gpio based addresses. >> Changes in V5: >> - None >> Changes in V6: >> - None >> arch/arm/cpu/armv7/exynos/pinmux.c | 241 >> +++++++++++++++++++++++++++++- >> arch/arm/include/asm/arch-exynos/gpio.h | 143 ++++++++++++++++-- >> arch/arm/include/asm/arch-exynos/periph.h | 3 + >> 3 files changed, 372 insertions(+), 15 deletions(-) >> >> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c >> b/arch/arm/cpu/armv7/exynos/pinmux.c >> index 8002bce..417ecae 100644 >> --- a/arch/arm/cpu/armv7/exynos/pinmux.c >> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c >> @@ -46,6 +46,41 @@ static void exynos5_uart_config(int peripheral) >> } >> } >> >> +static void exynos5420_uart_config(int peripheral) >> +{ >> + struct exynos5420_gpio_part1 *gpio1 = >> + (struct exynos5420_gpio_part1 >> *)samsung_get_base_gpio_part1(); >> + struct s5p_gpio_bank *bank; >> + int i, start, count; >> + >> + switch (peripheral) { >> + case PERIPH_ID_UART0: >> + bank = &gpio1->a0; >> + start = 0; >> + count = 4; >> + break; >> + case PERIPH_ID_UART1: >> + bank = &gpio1->a0; >> + start = 4; >> + count = 4; >> + break; >> + case PERIPH_ID_UART2: >> + bank = &gpio1->a1; >> + start = 0; >> + count = 4; >> + break; >> + case PERIPH_ID_UART3: >> + bank = &gpio1->a1; >> + start = 4; >> + count = 2; >> + break; > > + } >> > > please add blank line. will correct this > > >> + for (i = start; i < start + count; i++) { >> + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); >> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); >> + } >> +} >> + >> static int exynos5_mmc_config(int peripheral, int flags) >> { >> struct exynos5_gpio_part1 *gpio1 = >> @@ -101,6 +136,70 @@ static int exynos5_mmc_config(int peripheral, int >> flags) >> return 0; >> } >> >> +static int exynos5420_mmc_config(int peripheral, int flags) >> +{ >> + struct exynos5420_gpio_part3 *gpio3 = >> + (struct exynos5420_gpio_part3 >> *)samsung_get_base_gpio_part3(); >> + struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL; >> + int i, start = 0, gpio_func = 0; >> > > I think we don' have to set to 0 to start and gpio_func. Will remove gpio_func, but if I dont set start to 0 I get following error: pinmux.c: In function ?exynos_pinmux_config?: pinmux.c:173:20: warning: ?start? may be used uninitialized in this function [-Wmaybe-uninitialized] pinmux.c:145:9: note: ?start? was declared here > > >> + >> + switch (peripheral) { >> + case PERIPH_ID_SDMMC0: >> + bank = &gpio3->c0; >> + bank_ext = &gpio3->c3; >> + start = 0; >> + gpio_func = GPIO_FUNC(0x2); >> + break; >> + case PERIPH_ID_SDMMC1: >> + bank = &gpio3->c1; >> + bank_ext = &gpio3->d1; >> + start = 4; >> + gpio_func = GPIO_FUNC(0x2); >> + break; >> + case PERIPH_ID_SDMMC2: >> + bank = &gpio3->c2; >> + bank_ext = NULL; >> + gpio_func = GPIO_FUNC(0x2); >> + break; > > + } >> > > please add blank line. Will correct this > > >> + if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { >> + debug("SDMMC device %d does not support 8bit mode", >> + peripheral); >> + return -1; >> + } >> > > please add blank line. Will correct this > > >> + if (flags & PINMUX_FLAG_8BIT_MODE) { >> + for (i = start; i <= (start + 3); i++) { >> + s5p_gpio_cfg_pin(bank_ext, i, gpio_func); >> > > gpio_func is always GPIO_FUNC(0x2). > I think gpio_func is unnecessary. will remove this > > >> + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); >> + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); >> + } >> + } >> > > please add blank line. Will correct this > > >> + for (i = 0; i < 3; i++) { >> + /* >> + * MMC0 is intended to be used for eMMC. The >> + * card detect pin is used as a VDDEN signal to >> + * power on the eMMC. The 5420 iROM makes >> + * this same assumption. >> + */ >> + if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) { >> + s5p_gpio_set_value(bank, i, 1); >> + s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT); >> + } else { >> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); >> + } >> + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); >> + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); >> + } >> + >> + for (i = 3; i <= 6; i++) { >> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); >> + s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); >> + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); >> + } >> + >> + return 0; >> +} >> + >> static void exynos5_sromc_config(int flags) >> { >> struct exynos5_gpio_part1 *gpio1 = >> @@ -216,6 +315,59 @@ static void exynos5_i2c_config(int peripheral, int >> flags) >> } >> } >> >> +static void exynos5420_i2c_config(int peripheral) >> +{ >> + struct exynos5420_gpio_part1 *gpio1 = >> + (struct exynos5420_gpio_part1 >> *)samsung_get_base_gpio_part1(); >> + >> + switch (peripheral) { >> + case PERIPH_ID_I2C0: >> + s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); >> + s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); >> + break; >> + case PERIPH_ID_I2C1: >> + s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); >> + s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); >> + break; >> + case PERIPH_ID_I2C2: >> + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); >> + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); >> + break; >> + case PERIPH_ID_I2C3: >> + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); >> + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); >> + break; >> + case PERIPH_ID_I2C4: >> + s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); >> + s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); >> + break; >> + case PERIPH_ID_I2C5: >> + s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); >> + s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); >> + break; >> + case PERIPH_ID_I2C6: >> + s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); >> + s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); >> + break; >> + case PERIPH_ID_I2C7: >> + s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); >> + s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); >> + break; >> + case PERIPH_ID_I2C8: >> + s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2)); >> + s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2)); >> + break; >> + case PERIPH_ID_I2C9: >> + s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2)); >> + s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2)); >> + break; >> + case PERIPH_ID_I2C10: >> + s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2)); >> + s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2)); >> + break; >> + } >> +} >> + >> static void exynos5_i2s_config(int peripheral) >> { >> int i; >> @@ -279,6 +431,49 @@ void exynos5_spi_config(int peripheral) >> } >> } >> >> +void exynos5420_spi_config(int peripheral) >> +{ >> + int cfg = 0, pin = 0, i; >> > > please don't set to 0 at here. > We should set some values at switch..case. Get the following warning: pinmux.c: In function ?exynos5420_spi_config?: pinmux.c:471:3: warning: ?pin? may be used uninitialized in this function [-Wmaybe-uninitialized] pinmux.c:472:20: warning: ?cfg? may be used uninitialized in this function [-Wmaybe-uninitialized] > >> + struct s5p_gpio_bank *bank = NULL; >> + struct exynos5420_gpio_part1 *gpio1 = >> + (struct exynos5420_gpio_part1 >> *)samsung_get_base_gpio_part1(); >> + struct exynos5420_gpio_part4 *gpio4 = >> + (struct exynos5420_gpio_part4 >> *)samsung_get_base_gpio_part4(); >> + >> + switch (peripheral) { >> + case PERIPH_ID_SPI0: >> + bank = &gpio1->a2; >> + cfg = GPIO_FUNC(0x2); >> + pin = 0; >> + break; >> + case PERIPH_ID_SPI1: >> + bank = &gpio1->a2; >> + cfg = GPIO_FUNC(0x2); >> + pin = 4; >> + break; >> + case PERIPH_ID_SPI2: >> + bank = &gpio1->b1; >> + cfg = GPIO_FUNC(0x5); >> + pin = 1; >> + break; >> + case PERIPH_ID_SPI3: >> + bank = &gpio4->f1; >> + cfg = GPIO_FUNC(0x2); >> + pin = 0; >> + break; >> + case PERIPH_ID_SPI4: >> + for (i = 0; i < 2; i++) { >> + s5p_gpio_cfg_pin(&gpio4->f0, i + 2, >> GPIO_FUNC(0x4)); >> + s5p_gpio_cfg_pin(&gpio4->e0, i + 4, >> GPIO_FUNC(0x4)); >> + } >> > > OK. I understood SPI4 is different with other SPIs. > but, it was another context. > just break and move it to out of this switch..case. > > >> + break; > > + } >> > > please add blank line. > > >> + if (peripheral != PERIPH_ID_SPI4) { >> + for (i = pin; i < pin + 4; i++) >> + s5p_gpio_cfg_pin(bank, i, cfg); >> + } >> +} >> + >> static int exynos5_pinmux_config(int peripheral, int flags) >> { >> switch (peripheral) { >> @@ -325,6 +520,48 @@ static int exynos5_pinmux_config(int peripheral, int >> flags) >> return 0; >> } >> >> +static int exynos5420_pinmux_config(int peripheral, int flags) >> +{ >> + switch (peripheral) { >> + case PERIPH_ID_UART0: >> + case PERIPH_ID_UART1: >> + case PERIPH_ID_UART2: >> + case PERIPH_ID_UART3: >> + exynos5420_uart_config(peripheral); >> + break; >> + case PERIPH_ID_SDMMC0: >> + case PERIPH_ID_SDMMC1: >> + case PERIPH_ID_SDMMC2: >> + case PERIPH_ID_SDMMC3: >> + return exynos5420_mmc_config(peripheral, flags); >> + case PERIPH_ID_SPI0: >> + case PERIPH_ID_SPI1: >> + case PERIPH_ID_SPI2: >> + case PERIPH_ID_SPI3: >> + case PERIPH_ID_SPI4: >> + exynos5420_spi_config(peripheral); >> + break; >> + case PERIPH_ID_I2C0: >> + case PERIPH_ID_I2C1: >> + case PERIPH_ID_I2C2: >> + case PERIPH_ID_I2C3: >> + case PERIPH_ID_I2C4: >> + case PERIPH_ID_I2C5: >> + case PERIPH_ID_I2C6: >> + case PERIPH_ID_I2C7: >> + case PERIPH_ID_I2C8: >> + case PERIPH_ID_I2C9: >> + case PERIPH_ID_I2C10: >> + exynos5420_i2c_config(peripheral); >> + break; >> + default: >> + debug("%s: invalid peripheral %d", __func__, peripheral); >> + return -1; >> + } >> + >> + return 0; >> +} >> + >> static void exynos4_i2c_config(int peripheral, int flags) >> { >> struct exynos4_gpio_part1 *gpio1 = >> @@ -474,7 +711,9 @@ static int exynos4_pinmux_config(int peripheral, int >> flags) >> >> int exynos_pinmux_config(int peripheral, int flags) >> { >> - if (cpu_is_exynos5()) { >> + if (proid_is_exynos5420()) { >> + return exynos5420_pinmux_config(peripheral, flags); >> + } else if (proid_is_exynos5250()) { >> > > please don't mix cpu_is.. and proid_is.. Will correct this. > > >> return exynos5_pinmux_config(peripheral, flags); >> } else if (cpu_is_exynos4()) { >> return exynos4_pinmux_config(peripheral, flags); >> diff --git a/arch/arm/include/asm/arch-exynos/gpio.h >> b/arch/arm/include/asm/arch-exynos/gpio.h >> index a1a7439..2a19852 100644 >> --- a/arch/arm/include/asm/arch-exynos/gpio.h >> +++ b/arch/arm/include/asm/arch-exynos/gpio.h >> @@ -127,6 +127,58 @@ struct exynos4x12_gpio_part4 { >> struct s5p_gpio_bank v4; >> }; >> >> +struct exynos5420_gpio_part1 { >> + struct s5p_gpio_bank a0; >> + struct s5p_gpio_bank a1; >> + struct s5p_gpio_bank a2; >> + struct s5p_gpio_bank b0; >> + struct s5p_gpio_bank b1; >> + struct s5p_gpio_bank b2; >> + struct s5p_gpio_bank b3; >> + struct s5p_gpio_bank b4; >> + struct s5p_gpio_bank h0; >> +}; >> + >> +struct exynos5420_gpio_part2 { >> + struct s5p_gpio_bank y7; /* 0x1340_0000 */ >> + struct s5p_gpio_bank res[0x5f]; /* */ >> + struct s5p_gpio_bank x0; /* 0x1340_0C00 */ >> + struct s5p_gpio_bank x1; /* 0x1340_0C20 */ >> + struct s5p_gpio_bank x2; /* 0x1340_0C40 */ >> + struct s5p_gpio_bank x3; /* 0x1340_0C60 */ >> +}; >> + >> +struct exynos5420_gpio_part3 { >> + struct s5p_gpio_bank c0; >> + struct s5p_gpio_bank c1; >> + struct s5p_gpio_bank c2; >> + struct s5p_gpio_bank c3; >> + struct s5p_gpio_bank c4; >> + struct s5p_gpio_bank d1; >> + struct s5p_gpio_bank y0; >> + struct s5p_gpio_bank y1; >> + struct s5p_gpio_bank y2; >> + struct s5p_gpio_bank y3; >> + struct s5p_gpio_bank y4; >> + struct s5p_gpio_bank y5; >> + struct s5p_gpio_bank y6; >> +}; >> + >> +struct exynos5420_gpio_part4 { >> + struct s5p_gpio_bank e0; /* 0x1400_0000 */ >> + struct s5p_gpio_bank e1; /* 0x1400_0020 */ >> + struct s5p_gpio_bank f0; /* 0x1400_0040 */ >> + struct s5p_gpio_bank f1; /* 0x1400_0060 */ >> + struct s5p_gpio_bank g0; /* 0x1400_0080 */ >> + struct s5p_gpio_bank g1; /* 0x1400_00A0 */ >> + struct s5p_gpio_bank g2; /* 0x1400_00C0 */ >> + struct s5p_gpio_bank j4; /* 0x1400_00E0 */ >> +}; >> + >> +struct exynos5420_gpio_part5 { >> + struct s5p_gpio_bank z0; /* 0x0386_0000 */ >> +}; >> + >> struct exynos5_gpio_part1 { >> struct s5p_gpio_bank a0; >> struct s5p_gpio_bank a1; >> @@ -259,16 +311,67 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, >> int gpio, int mode); >> - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ >> * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX) >> >> + >> +/* EXYNOS5420 */ >> +#define exynos5420_gpio_part1_get_nr(bank, pin) \ >> + ((((((unsigned int) &(((struct exynos5420_gpio_part1 *)\ >> + EXYNOS5420_GPIO_PART1_BASE)->bank)) \ >> + - EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ >> + * GPIO_PER_BANK) + pin) >> + >> +#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \ >> + / sizeof(struct s5p_gpio_bank)) * >> GPIO_PER_BANK) >> + >> +#define exynos5420_gpio_part2_get_nr(bank, pin) \ >> + (((((((unsigned int) &(((struct exynos5420_gpio_part2 *)\ >> + EXYNOS5420_GPIO_PART2_BASE)->bank)) \ >> + - EXYNOS5420_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ >> + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART1_MAX) >> + >> +#define EXYNOS5420_GPIO_PART2_MAX ((sizeof(struct exynos5420_gpio_part2) \ >> + / sizeof(struct s5p_gpio_bank)) * >> GPIO_PER_BANK) >> + >> +#define exynos5420_gpio_part3_get_nr(bank, pin) \ >> + (((((((unsigned int) &(((struct exynos5420_gpio_part3 *)\ >> + EXYNOS5420_GPIO_PART3_BASE)->bank)) \ >> + - EXYNOS5420_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ >> + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART2_MAX) >> + >> +#define EXYNOS5420_GPIO_PART3_MAX ((sizeof(struct exynos5420_gpio_part3) \ >> + / sizeof(struct s5p_gpio_bank)) * >> GPIO_PER_BANK) >> + >> +#define exynos5420_gpio_part4_get_nr(bank, pin) \ >> + (((((((unsigned int) &(((struct exynos5420_gpio_part4 *)\ >> + EXYNOS5420_GPIO_PART4_BASE)->bank)) \ >> + - EXYNOS5420_GPIO_PART4_BASE) / sizeof(struct s5p_gpio_bank)) \ >> + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART3_MAX) >> + >> +#define EXYNOS5420_GPIO_PART4_MAX ((sizeof(struct exynos5420_gpio_part4) \ >> + / sizeof(struct s5p_gpio_bank)) * >> GPIO_PER_BANK) >> + >> +#define EXYNOS5420_GPIO_PART5_MAX ((sizeof(struct exynos5420_gpio_part5) \ >> + / sizeof(struct s5p_gpio_bank)) * >> GPIO_PER_BANK) >> + >> static inline unsigned int s5p_gpio_base(int nr) >> { >> if (cpu_is_exynos5()) { >> - if (nr < EXYNOS5_GPIO_PART1_MAX) >> - return EXYNOS5_GPIO_PART1_BASE; >> - else if (nr < EXYNOS5_GPIO_PART2_MAX) >> - return EXYNOS5_GPIO_PART2_BASE; >> - else >> - return EXYNOS5_GPIO_PART3_BASE; >> - >> + if (proid_is_exynos5420()) { >> + if (nr < EXYNOS5420_GPIO_PART1_MAX) >> + return EXYNOS5420_GPIO_PART1_BASE; >> + else if (nr < EXYNOS5420_GPIO_PART2_MAX) >> + return EXYNOS5420_GPIO_PART2_BASE; >> + else if (nr < EXYNOS5420_GPIO_PART3_MAX) >> + return EXYNOS5420_GPIO_PART3_BASE; >> + else >> + return EXYNOS5420_GPIO_PART4_BASE; >> + } else { >> + if (nr < EXYNOS5_GPIO_PART1_MAX) >> + return EXYNOS5_GPIO_PART1_BASE; >> + else if (nr < EXYNOS5_GPIO_PART2_MAX) >> + return EXYNOS5_GPIO_PART2_BASE; >> + else >> + return EXYNOS5_GPIO_PART3_BASE; >> + } >> } else if (cpu_is_exynos4()) { >> if (nr < EXYNOS4_GPIO_PART1_MAX) >> return EXYNOS4_GPIO_PART1_BASE; >> @@ -282,13 +385,25 @@ static inline unsigned int s5p_gpio_base(int nr) >> static inline unsigned int s5p_gpio_part_max(int nr) >> { >> if (cpu_is_exynos5()) { >> - if (nr < EXYNOS5_GPIO_PART1_MAX) >> - return 0; >> - else if (nr < EXYNOS5_GPIO_PART2_MAX) >> - return EXYNOS5_GPIO_PART1_MAX; >> - else >> - return EXYNOS5_GPIO_PART2_MAX; >> - >> + if (proid_is_exynos5420()) { >> + if (nr < EXYNOS5420_GPIO_PART1_MAX) >> + return 0; >> + else if (nr < EXYNOS5420_GPIO_PART2_MAX) >> + return EXYNOS5420_GPIO_PART1_MAX; >> + else if (nr < EXYNOS5420_GPIO_PART3_MAX) >> + return EXYNOS5420_GPIO_PART2_MAX; >> + else if (nr < EXYNOS5420_GPIO_PART4_MAX) >> + return EXYNOS5420_GPIO_PART3_MAX; >> + else >> + return EXYNOS5420_GPIO_PART4_MAX; >> + } else { >> + if (nr < EXYNOS5_GPIO_PART1_MAX) >> + return 0; >> + else if (nr < EXYNOS5_GPIO_PART2_MAX) >> + return EXYNOS5_GPIO_PART1_MAX; >> + else >> + return EXYNOS5_GPIO_PART2_MAX; >> + } >> } else if (cpu_is_exynos4()) { >> if (proid_is_exynos4412()) { >> if (nr < EXYNOS4X12_GPIO_PART1_MAX) >> diff --git a/arch/arm/include/asm/arch-exynos/periph.h >> b/arch/arm/include/asm/arch-exynos/periph.h >> index 64bd8b7..30c7f18 100644 >> --- a/arch/arm/include/asm/arch-exynos/periph.h >> +++ b/arch/arm/include/asm/arch-exynos/periph.h >> @@ -34,6 +34,9 @@ enum periph_id { >> PERIPH_ID_SDMMC1, >> PERIPH_ID_SDMMC2, >> PERIPH_ID_SDMMC3, >> + PERIPH_ID_I2C8 = 87, >> + PERIPH_ID_I2C9, >> + PERIPH_ID_I2C10 = 203, >> PERIPH_ID_I2S0 = 98, >> PERIPH_ID_I2S1 = 99, >> >> -- >> 1.7.12.4 >> >> _______________________________________________ >> U-Boot mailing list >> U-Boot at lists.denx.de >> http://lists.denx.de/mailman/listinfo/u-boot >> > > Thanks, > Minkyu Kang. > -- > from. prom. > www.promsoft.net > > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > -- Regards, Rajeshwari Shinde