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(p200300faaf0bb200b8984a967c4b65c7.dip0.t-ipconnect.de. [2003:fa:af0b:b200:b898:4a96:7c4b:65c7]) by smtp.gmail.com with ESMTPSA id d7-20020a056402516700b004642b35f89esm2637827ede.9.2023.01.08.07.30.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 08 Jan 2023 07:30:24 -0800 (PST) Date: Sun, 08 Jan 2023 15:30:12 +0000 From: Bernhard Beschow To: Mark Cave-Ayland , qemu-devel@nongnu.org CC: Eduardo Habkost , qemu-block@nongnu.org, =?ISO-8859-1?Q?Herv=E9_Poussineau?= , Ani Sinha , Richard Henderson , Jiaxun Yang , Aurelien Jarno , "Michael S. Tsirkin" , =?ISO-8859-1?Q?Philippe_Mathieu-Daud=E9?= , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?ISO-8859-1?Q?Philippe_Mathieu-Daud=E9?= Subject: Re: [PATCH v5 13/31] hw/intc/i8259: Introduce i8259 proxy "isa-pic" In-Reply-To: <9724624c-4848-4308-4dc6-d77bfcc8fc0f@ilande.co.uk> References: <20230105143228.244965-1-shentey@gmail.com> <20230105143228.244965-14-shentey@gmail.com> <9724624c-4848-4308-4dc6-d77bfcc8fc0f@ilande.co.uk> Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=shentey@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Mark, Am 7=2E Januar 2023 23:45:39 UTC schrieb Mark Cave-Ayland : >On 05/01/2023 14:32, Bernhard Beschow wrote: > >> Having an i8259 proxy allows for ISA PICs to be created and wired up in >> southbridges=2E This is especially interesting for PIIX3 for two reason= s: >> First, the southbridge doesn't need to care about the virtualization >> technology used (KVM, TCG, Xen) due to in-IRQs (where devices get >> attached) and out-IRQs (which will trigger the IRQs of the respective >> virtualization technology) are separated=2E Second, since the in-IRQs a= re >> populated with fully initialized qemu_irq's, they can already be wired >> up inside PIIX3=2E >>=20 >> Cc: Mark Cave-Ayland >> Signed-off-by: Bernhard Beschow >> --- >> include/hw/intc/i8259=2Eh | 19 +++++++++++++++++++ >> hw/intc/i8259=2Ec | 27 +++++++++++++++++++++++++++ >> 2 files changed, 46 insertions(+) >>=20 >> diff --git a/include/hw/intc/i8259=2Eh b/include/hw/intc/i8259=2Eh >> index a0e34dd990=2E=2Ef666f5ee09 100644 >> --- a/include/hw/intc/i8259=2Eh >> +++ b/include/hw/intc/i8259=2Eh >> @@ -1,6 +1,25 @@ >> #ifndef HW_I8259_H >> #define HW_I8259_H >> +#include "qom/object=2Eh" >> +#include "hw/isa/isa=2Eh" >> +#include "qemu/typedefs=2Eh" >> + >> +#define TYPE_ISA_PIC "isa-pic" >> +OBJECT_DECLARE_SIMPLE_TYPE(ISAPICState, ISA_PIC) >> + >> +/* >> + * TYPE_ISA_PIC is currently a PIC proxy which allows for interrupt wi= ring in >> + * a virtualization technology agnostic way=2E It could be turned into= a proper >> + * GPIO-based ISA PIC in the future=2E >> + */ > >I would say that the last sentence isn't true, since when all PIC impleme= ntations have been converted to qdev the mechanism for choosing the PIC imp= lementation is currently unspecified=2E As an example once this has been do= ne "isa-pic" could be removed completely and the code in the following patc= h changed to something like: > > object_initialize_child(obj, "pic", &d->pic, kvm_enabled() ? TYPE_KV= M_I8259 : > TYPE_I8259); This wouldn't work for the Malta machine where TYPE_I8259 is used even in = the case of kvm_enabled()=2E Furthermore, the PC machine may instantiate ye= t another interrupt controller here in Xen mode=2E Hence my sentence in the= cover letter of making PIIX agnostic about the virtualization technology u= sed=2E Let's discuss future directions elsewhere for the sake of separation= of concerns ;) >Perhaps change the last sentence to something like: "It provides a tempor= ary bridge between older x86 code where qemu_irqs are passed around directl= y and devices that use qdev gpios=2E"? I'd omit the last sentence for now=2E >Other than that the implementation looks sensible to me, so: > >Reviewed-by: Mark Cave-Ayland Thanks! Best regards, Bernhard >> +struct ISAPICState { >> + DeviceState parent_obj; >> + >> + qemu_irq in_irqs[ISA_NUM_IRQS]; >> + qemu_irq out_irqs[ISA_NUM_IRQS]; >> +}; >> + >> /* i8259=2Ec */ >> extern PICCommonState *isa_pic; >> diff --git a/hw/intc/i8259=2Ec b/hw/intc/i8259=2Ec >> index 0261f087b2=2E=2Ee99d02136d 100644 >> --- a/hw/intc/i8259=2Ec >> +++ b/hw/intc/i8259=2Ec >> @@ -455,9 +455,36 @@ static const TypeInfo i8259_info =3D { >> =2Eclass_size =3D sizeof(PICClass), >> }; >> +static void isapic_set_irq(void *opaque, int irq, int level) >> +{ >> + ISAPICState *s =3D opaque; >> + >> + qemu_set_irq(s->out_irqs[irq], level); >> +} >> + >> +static void isapic_init(Object *obj) >> +{ >> + ISAPICState *s =3D ISA_PIC(obj); >> + >> + qdev_init_gpio_in(DEVICE(s), isapic_set_irq, ISA_NUM_IRQS); >> + qdev_init_gpio_out(DEVICE(s), s->out_irqs, ISA_NUM_IRQS); >> + >> + for (int i =3D 0; i < ISA_NUM_IRQS; ++i) { >> + s->in_irqs[i] =3D qdev_get_gpio_in(DEVICE(s), i); >> + } >> +} >> + >> +static const TypeInfo isapic_info =3D { >> + =2Ename =3D TYPE_ISA_PIC, >> + =2Eparent =3D TYPE_DEVICE, >> + =2Einstance_size =3D sizeof(ISAPICState), >> + =2Einstance_init =3D isapic_init, >> +}; >> + >> static void pic_register_types(void) >> { >> type_register_static(&i8259_info); >> + type_register_static(&isapic_info); >> } >> type_init(pic_register_types) > > >ATB, > >Mark=2E