From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39874) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wmuqu-00010l-AS for qemu-devel@nongnu.org; Tue, 20 May 2014 20:57:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wmuqq-0002yZ-J6 for qemu-devel@nongnu.org; Tue, 20 May 2014 20:57:52 -0400 Received: from mga01.intel.com ([192.55.52.88]:19181) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wmuqq-0002yU-EY for qemu-devel@nongnu.org; Tue, 20 May 2014 20:57:48 -0400 From: "Chen, Tiejun" Date: Wed, 21 May 2014 00:57:44 +0000 Message-ID: References: <1400237624-8505-1-git-send-email-tiejun.chen@intel.com> <1400237624-8505-9-git-send-email-tiejun.chen@intel.com> In-Reply-To: Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Qemu-devel] [v2][PATCH 8/8] xen, gfx passthrough: add opregion mapping List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Stefano Stabellini Cc: "peter.maydell@linaro.org" , "xen-devel@lists.xensource.com" , "mst@redhat.com" , "Kay, Allen M" , "qemu-devel@nongnu.org" , "Kelly.Zytaruk@amd.com" , "Zhang, Yang Z" , "anthony@codemonkey.ws" , "anthony.perard@citrix.com" > -----Original Message----- > From: Stefano Stabellini [mailto:stefano.stabellini@eu.citrix.com] > Sent: Tuesday, May 20, 2014 6:51 PM > To: Chen, Tiejun > Cc: Stefano Stabellini; anthony.perard@citrix.com; mst@redhat.com; > Kelly.Zytaruk@amd.com; qemu-devel@nongnu.org; > xen-devel@lists.xensource.com; peter.maydell@linaro.org; > anthony@codemonkey.ws; Kay, Allen M; Zhang, Yang Z > Subject: RE: [v2][PATCH 8/8] xen, gfx passthrough: add opregion mapping >=20 [snip] > > > > > > > > + if (xen_pt_emu_reg_grps[i].grp_id =3D=3D PCI_INTEL_OPREGIO= N) { > > > > + reg_grp_offset =3D PCI_INTEL_OPREGION; > > > > + } > > > > + > > > > But for this pass through scenario, we have to set 0xfc manually since = we > need to trap 0xfc completely in that comment: > > > > + /* > > + ** By default we will trap up to 0x40 in the cfg space. > > + ** If an intel device is pass through we need to trap 0xfc, > > + ** therefore the size should be 0xff. > > + */ >=20 > OK. Can you please keep this comment in your patch? Thanks! Sure. Thanks Tiejun From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Chen, Tiejun" Subject: Re: [v2][PATCH 8/8] xen, gfx passthrough: add opregion mapping Date: Wed, 21 May 2014 00:57:44 +0000 Message-ID: References: <1400237624-8505-1-git-send-email-tiejun.chen@intel.com> <1400237624-8505-9-git-send-email-tiejun.chen@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+gceq-qemu-devel=gmane.org@nongnu.org Sender: qemu-devel-bounces+gceq-qemu-devel=gmane.org@nongnu.org To: Stefano Stabellini Cc: "peter.maydell@linaro.org" , "xen-devel@lists.xensource.com" , "mst@redhat.com" , "Kay, Allen M" , "qemu-devel@nongnu.org" , "Kelly.Zytaruk@amd.com" , "Zhang, Yang Z" , "anthony@codemonkey.ws" , "anthony.perard@citrix.com" List-Id: xen-devel@lists.xenproject.org > -----Original Message----- > From: Stefano Stabellini [mailto:stefano.stabellini@eu.citrix.com] > Sent: Tuesday, May 20, 2014 6:51 PM > To: Chen, Tiejun > Cc: Stefano Stabellini; anthony.perard@citrix.com; mst@redhat.com; > Kelly.Zytaruk@amd.com; qemu-devel@nongnu.org; > xen-devel@lists.xensource.com; peter.maydell@linaro.org; > anthony@codemonkey.ws; Kay, Allen M; Zhang, Yang Z > Subject: RE: [v2][PATCH 8/8] xen, gfx passthrough: add opregion mapping >=20 [snip] > > > > > > > > + if (xen_pt_emu_reg_grps[i].grp_id =3D=3D PCI_INTEL_OPREGIO= N) { > > > > + reg_grp_offset =3D PCI_INTEL_OPREGION; > > > > + } > > > > + > > > > But for this pass through scenario, we have to set 0xfc manually since = we > need to trap 0xfc completely in that comment: > > > > + /* > > + ** By default we will trap up to 0x40 in the cfg space. > > + ** If an intel device is pass through we need to trap 0xfc, > > + ** therefore the size should be 0xff. > > + */ >=20 > OK. Can you please keep this comment in your patch? Thanks! Sure. Thanks Tiejun