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Miller" , Jakub Kicinski , "Maxime Coquelin" , "Ong, Boon Leong" , Wong Vee Khee , "Wong, Vee Khee" , "Tan, Tee Min" , "Sit, Michael Wei Hong" , "netdev@vger.kernel.org" , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH net-next V1 3/4] net: stmmac: Reconfigure the PHY WOL settings in stmmac_resume() Thread-Topic: [PATCH net-next V1 3/4] net: stmmac: Reconfigure the PHY WOL settings in stmmac_resume() Thread-Index: AQHXZoJFBtZ0uXgSn0S7qboFjm+Joqseb0UAgALh+bCAAK/dgIAA5rbAgABIGwCAAagL0IAAHuMAgAQZSbA= Date: Mon, 28 Jun 2021 07:54:14 +0000 Message-ID: References: <20210621094536.387442-1-pei.lee.ling@intel.com> <20210621094536.387442-4-pei.lee.ling@intel.com> <20210625164834.GY22278@shell.armlinux.org.uk> In-Reply-To: <20210625164834.GY22278@shell.armlinux.org.uk> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: armlinux.org.uk; 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x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?Scs+9Vttx0usQitsHPlmCaixxtXOaSms6cwaGDkzi7uH/DUParMdNA5xloFO?= =?us-ascii?Q?zo9jWjlEKRyXF8DmI2apqms+BdpLZcakd/hG4LQR7dM44La6zxEqa0kLwXJZ?= =?us-ascii?Q?T0tWDAP28CCfmja4c2lUszfWINa7xGtB8WMdOOMioCChznZApxHh4/IyXphh?= =?us-ascii?Q?aV1bz+5s9UWroTlfsq+ejeiNhYTa1zxAjBS3vATTKcvK6QL6mJAedJJVw01a?= =?us-ascii?Q?zNDihjk0HFT7VnB2BAIHHTzoLdhz0Cwx/30b8AY8n3qAHtHSOoKqFczS7GlY?= =?us-ascii?Q?Auz66QSUCbjhJNPp9niIm6WnVoJGQxCWdXSx8oz8vRE3dlRT4+1ih/YSOIHj?= =?us-ascii?Q?dsOorR9wDI3+Z9S3ZqhZdycu8Zg+FOKvVR2IbjFvgnLb3rrshdFepNXZajNm?= =?us-ascii?Q?jJR0rMxAeiOF5/u3ZJrWslSPvMYT5cDNBmm23NlquV2wIHGDyxe284G0Q3y5?= =?us-ascii?Q?MWjAbtmI5OtLlMYCIFWtvlAAkh0t5zf23eQWgij2D4M3GEIMngaH1TpmaZ/A?= =?us-ascii?Q?UPjRc1Pd3Xd0DZ6n8+R6zU8xFizQbOplOWSP0XKpIE6cdQA+GLQ+tf8EcyH7?= =?us-ascii?Q?gYIXNaGm23NqQ/r3OWYDbF+E4Z8kHnpZgS30HGDc35s30Z2dqsLAXQ8G7p6h?= =?us-ascii?Q?TPSfTvpGIRiQENGuDcriAvdg68jjSWCz63B2nSo61TBkHT6OkrjnCKKmEOeY?= =?us-ascii?Q?UxF4kRRA3mm7PwCZDFDgJZcYL7RhU1SWMrkSx5sU6Qo5t7fk8xva+wRk5/D7?= =?us-ascii?Q?VuFslHJFTI4D4e/LFOdF4V7g8/2Y+5NW55mW42/UsG97QCnMAPT+MpUZtGFx?= =?us-ascii?Q?D5HfdrFrfMFYSw+wGcBpY4SSE8iqCu36ZusPMbfa1D9gqBoaC1DUch4CJCPO?= =?us-ascii?Q?XFyt8f1f+JY8IGWzff4mUiH1HSAvhpe/cIUrxDcVKoAmlJ6kMbfYdejps54r?= =?us-ascii?Q?QlCodQ5gNAMUhulnL2Va7ky8rznUcDnI65T6t6eLIjm8pP7XIDYBYuuKRySD?= =?us-ascii?Q?Zwl2td08pEPksgtXyqVVAoafscdA9ALfrKPDfJlGWBf/tavS5OxIEceq/14g?= =?us-ascii?Q?+BuBdhocbvmrhtx4SfZX9pW0nXJVoqIC1akoTn8nx20+I+YMLRRAZXyVkuEp?= =?us-ascii?Q?NYVYushzMnwY8BMghI9IakGj3MI9aEBcfnh7JTJFFgp9GtlGtVExvbI73koG?= =?us-ascii?Q?UCEClKxfJqazD+QKtpfwgPLlDwXX74TYVO7nOYL1YIJ/Aauzr7JjYNzuKYNS?= =?us-ascii?Q?EBefHkW747+R03g/DFRLgz6zbGKrkFzBk3Z0D54XuX0AEYt49G95VPurLN8r?= =?us-ascii?Q?FaPsA2ghrFfr5+mg5OVu98dD?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CH0PR11MB5380.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3e9a922c-42db-4485-2e8d-08d93a09ec94 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Jun 2021 07:54:14.6353 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 0lvQd89vQovFTjMcS0Uzc7uYlWsxWG4xA8QczRdvOZxLSCurpw3817dn6mkS0mq28MaFAdi93/hIMJnIU/PZlQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR11MB4472 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > > > No, the interrupt will not be discarded. If the PHY is in > > > > interrupt mode, the interrupt handler will triggers and ISR will > > > > clear the WOL > > > status bit. > > > > The condition here is when the PHY is in polling mode, the PHY > > > > driver does not have any other mechanism to clear the WOL interrupt > status bit. > > > > Hence, we need to go through the PHY set_wol() again. > > > > > > I would say you have a broken setup. If you are explicitly using the > > > interrupt as a wakeup source, you need to be servicing the > > > interrupt. You cannot use polled mode. > > > > Sorry for the confusion. But I would like to clarify the I should use > > the term of "WOL event status" rather than "WOL interrupt status". > > For interrupt mode, clearing the "WOL interrupt status" register will > > auto clear the "WOL event status". > > For polling mode, the phy driver can manually clear the "WOL event > > status" by setting 1 to "Clear WOL Status" bit. >=20 > If WOL raises an interrupt signal from the PHY, but the PHY interrupt > signal is not wired, how does the wakeup happen? What is the PHY interrup= t > wired to? The PHY WOL event signal is wired directly to the PMC. The PMC will detect= =20 the triggered WOL event signal and wakeup the system. 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Mon, 28 Jun 2021 07:54:14 +0000 From: "Voon, Weifeng" To: Russell King CC: Andrew Lunn , "Ling, Pei Lee" , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S . Miller" , Jakub Kicinski , "Maxime Coquelin" , "Ong, Boon Leong" , Wong Vee Khee , "Wong, Vee Khee" , "Tan, Tee Min" , "Sit, Michael Wei Hong" , "netdev@vger.kernel.org" , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH net-next V1 3/4] net: stmmac: Reconfigure the PHY WOL settings in stmmac_resume() Thread-Topic: [PATCH net-next V1 3/4] net: stmmac: Reconfigure the PHY WOL settings in stmmac_resume() Thread-Index: AQHXZoJFBtZ0uXgSn0S7qboFjm+Joqseb0UAgALh+bCAAK/dgIAA5rbAgABIGwCAAagL0IAAHuMAgAQZSbA= Date: Mon, 28 Jun 2021 07:54:14 +0000 Message-ID: References: <20210621094536.387442-1-pei.lee.ling@intel.com> <20210621094536.387442-4-pei.lee.ling@intel.com> <20210625164834.GY22278@shell.armlinux.org.uk> In-Reply-To: <20210625164834.GY22278@shell.armlinux.org.uk> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: armlinux.org.uk; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > > > > No, the interrupt will not be discarded. If the PHY is in > > > > interrupt mode, the interrupt handler will triggers and ISR will > > > > clear the WOL > > > status bit. > > > > The condition here is when the PHY is in polling mode, the PHY > > > > driver does not have any other mechanism to clear the WOL interrupt > status bit. > > > > Hence, we need to go through the PHY set_wol() again. > > > > > > I would say you have a broken setup. If you are explicitly using the > > > interrupt as a wakeup source, you need to be servicing the > > > interrupt. You cannot use polled mode. > > > > Sorry for the confusion. But I would like to clarify the I should use > > the term of "WOL event status" rather than "WOL interrupt status". > > For interrupt mode, clearing the "WOL interrupt status" register will > > auto clear the "WOL event status". > > For polling mode, the phy driver can manually clear the "WOL event > > status" by setting 1 to "Clear WOL Status" bit. > > If WOL raises an interrupt signal from the PHY, but the PHY interrupt > signal is not wired, how does the wakeup happen? What is the PHY interrupt > wired to? The PHY WOL event signal is wired directly to the PMC. The PMC will detect the triggered WOL event signal and wakeup the system. Weifeng _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel