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charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Official Use Only - General] Thanks for noticing, will fix it in a separate patch since I already merged= this. -- Regards, Jay ________________________________ From: Chen, Guchun Sent: Thursday, June 9, 2022 9:28 PM To: Pillai, Aurabindo ; Olsak, Marek ; amd-gfx@lists.freedesktop.org Cc: Li, Sun peng (Leo) ; Siqueira, Rodrigo ; Li, Roman ; Qiao, Ken ;= Pillai, Aurabindo ; Deucher, Alexander ; Wentland, Harry Subject: RE: [PATCH] drm/amd/display: ignore modifiers when checking for fo= rmat support + return true; + break; Possibly a coding style problem, 'break' after 'return' looks redundant. Regards, Guchun -----Original Message----- From: amd-gfx On Behalf Of Aurabind= o Pillai Sent: Thursday, June 9, 2022 10:27 PM To: Olsak, Marek ; amd-gfx@lists.freedesktop.org Cc: Li, Sun peng (Leo) ; Siqueira, Rodrigo ; Li, Roman ; Qiao, Ken ;= Pillai, Aurabindo ; Deucher, Alexander ; Wentland, Harry Subject: [PATCH] drm/amd/display: ignore modifiers when checking for format= support [Why&How] There are cases where swizzle modes are set but modifiers arent. For such a= userspace, we need not check modifiers while checking compatibilty in the = drm hook for checking plane format. Ignore checking modifiers but check the DCN generation for the supported sw= izzle mode. Signed-off-by: Aurabindo Pillai --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 51 +++++++++++++++++-- 1 file changed, 46 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2023baf41b7e..1322df491736 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4938,6 +4938,7 @@ static bool dm_plane_format_mod_supported(struct drm_= plane *plane, { struct amdgpu_device *adev =3D drm_to_adev(plane->dev); const struct drm_format_info *info =3D drm_format_info(format); + struct hw_asic_id asic_id =3D adev->dm.dc->ctx->asic_id; int i; enum dm_micro_swizzle microtile =3D modifier_gfx9_swizzle_mode(mod= ifier) & 3; @@ -4955,13 +4956,53 @@ static bool dm_plane_format_mod_support= ed(struct drm_plane *plane, return true; } - /* Check that the modifier is on the list of the plane's supported = modifiers. */ - for (i =3D 0; i < plane->modifier_count; i++) { - if (modifier =3D=3D plane->modifiers[i]) + /* check if swizzle mode is supported by this version of DCN */ + switch (asic_id.chip_family) { + case FAMILY_SI: + case FAMILY_CI: + case FAMILY_KV: + case FAMILY_CZ: + case FAMILY_VI: + /* AI and earlier asics does not have modifier supp= ort */ + return false; + break; + case FAMILY_AI: + case FAMILY_RV: + case FAMILY_NV: + case FAMILY_VGH: + case FAMILY_YELLOW_CARP: + case AMDGPU_FAMILY_GC_10_3_6: + case AMDGPU_FAMILY_GC_10_3_7: + switch (AMD_FMT_MOD_GET(TILE, modifier)) { + case AMD_FMT_MOD_TILE_GFX9_64K_R_X: + case AMD_FMT_MOD_TILE_GFX9_64K_D_X: + case AMD_FMT_MOD_TILE_GFX9_64K_S_X: + case AMD_FMT_MOD_TILE_GFX9_64K_D: + return true; + break; + default: + return false; + break; + } + break; + case AMDGPU_FAMILY_GC_11_0_0: + switch (AMD_FMT_MOD_GET(TILE, modifier)) { + case AMD_FMT_MOD_TILE_GFX11_256K_R_X: + case AMD_FMT_MOD_TILE_GFX9_64K_R_X: + case AMD_FMT_MOD_TILE_GFX9_64K_D_X: + case AMD_FMT_MOD_TILE_GFX9_64K_S_X: + case AMD_FMT_MOD_TILE_GFX9_64K_D: + return true; + break; + default: + return false; + break; + } + break; + default: + ASSERT(0); /* Unknown asic */ break; } - if (i =3D=3D plane->modifier_count) - return false; /* * For D swizzle the canonical modifier depends on the bpp, so che= ck -- 2.36.1 --_000_CH0PR12MB5284F6875A12FF0CFB0AEC778BA69CH0PR12MB5284namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

[AMD Official Use Only - General]


Thanks for noticing, will fix it in a separate patch since I already merged= this.

--

Regards,
Jay
From: Chen, Guchun <Guch= un.Chen@amd.com>
Sent: Thursday, June 9, 2022 9:28 PM
To: Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Olsak, Marek= <Marek.Olsak@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lis= ts.freedesktop.org>
Cc: Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Siqueira, Rodrigo= <Rodrigo.Siqueira@amd.com>; Li, Roman <Roman.Li@amd.com>; Qiao= , Ken <Ken.Qiao@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.= com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>
Subject: RE: [PATCH] drm/amd/display: ignore modifiers when checking= for format support
 
+        &= nbsp;           &nbs= p;            &= nbsp;     return true;
+            &n= bsp;            = ;            &n= bsp; break;

Possibly a coding style problem, 'break' after 'return' looks redundant.
Regards,
Guchun

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Au= rabindo Pillai
Sent: Thursday, June 9, 2022 10:27 PM
To: Olsak, Marek <Marek.Olsak@amd.com>; amd-gfx@lists.freedesktop.org=
Cc: Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Siqueira, Rodrigo <Ro= drigo.Siqueira@amd.com>; Li, Roman <Roman.Li@amd.com>; Qiao, Ken &= lt;Ken.Qiao@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>= ; Deucher, Alexander <Alexander.Deucher@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>
Subject: [PATCH] drm/amd/display: ignore modifiers when checking for format= support

[Why&How]
There are cases where swizzle modes are set but modifiers arent. For such a= userspace, we need not check modifiers while checking compatibilty in the = drm hook for checking plane format.

Ignore checking modifiers but check the DCN generation for the supported sw= izzle mode.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 51 +++++++++++++++++-= -
 1 file changed, 46 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 2023baf41b7e..1322df491736 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4938,6 +4938,7 @@ static bool dm_plane_format_mod_supported(struct drm_= plane *plane,  {
         struct amdgpu_device *adev= =3D drm_to_adev(plane->dev);
         const struct drm_format_in= fo *info =3D drm_format_info(format);
+       struct hw_asic_id asic_id =3D adev-&g= t;dm.dc->ctx->asic_id;
         int i;
 
         enum dm_micro_swizzle micr= otile =3D modifier_gfx9_swizzle_mode(modifier) & 3; @@ -4955,13 +4956,5= 3 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane,
            &nb= sp;    return true;
         }
 
-       /* Check that the modifier is on the = list of the plane's supported modifiers. */
-       for (i =3D 0; i < plane->modifi= er_count; i++) {
-            &n= bsp;  if (modifier =3D=3D plane->modifiers[i])
+       /* check if swizzle mode is supported= by this version of DCN */
+       switch (asic_id.chip_family) {
+            &n= bsp;  case FAMILY_SI:
+            &n= bsp;  case FAMILY_CI:
+            &n= bsp;  case FAMILY_KV:
+            &n= bsp;  case FAMILY_CZ:
+            &n= bsp;  case FAMILY_VI:
+            &n= bsp;          /* AI and earlie= r asics does not have modifier support */
+            &n= bsp;          return false; +            &n= bsp;          break;
+            &n= bsp;  case FAMILY_AI:
+            &n= bsp;  case FAMILY_RV:
+            &n= bsp;  case FAMILY_NV:
+            &n= bsp;  case FAMILY_VGH:
+            &n= bsp;  case FAMILY_YELLOW_CARP:
+            &n= bsp;  case AMDGPU_FAMILY_GC_10_3_6:
+            &n= bsp;  case AMDGPU_FAMILY_GC_10_3_7:
+            &n= bsp;          switch (AMD_FMT_= MOD_GET(TILE, modifier)) {
+            &n= bsp;            = ;      case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
+            &n= bsp;            = ;      case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
+            &n= bsp;            = ;      case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
+            &n= bsp;            = ;      case AMD_FMT_MOD_TILE_GFX9_64K_D:
+            &n= bsp;            = ;            &n= bsp; return true;
+            &n= bsp;            = ;            &n= bsp; break;
+            &n= bsp;            = ;      default:
+            &n= bsp;            = ;            &n= bsp; return false;
+            &n= bsp;            = ;            &n= bsp; break;
+            &n= bsp;          }
+            &n= bsp;          break;
+            &n= bsp;  case AMDGPU_FAMILY_GC_11_0_0:
+            &n= bsp;          switch (AMD_FMT_= MOD_GET(TILE, modifier)) {
+            &n= bsp;            = ;      case AMD_FMT_MOD_TILE_GFX11_256K_R_X:
+            &n= bsp;            = ;      case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
+            &n= bsp;            = ;      case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
+            &n= bsp;            = ;      case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
+            &n= bsp;            = ;      case AMD_FMT_MOD_TILE_GFX9_64K_D:
+            &n= bsp;            = ;            &n= bsp; return true;
+            &n= bsp;            = ;            &n= bsp; break;
+            &n= bsp;            = ;      default:
+            &n= bsp;            = ;            &n= bsp; return false;
+            &n= bsp;            = ;            &n= bsp; break;
+            &n= bsp;          }
+            &n= bsp;          break;
+            &n= bsp;  default:
+            &n= bsp;          ASSERT(0); /* Un= known asic */
            &nb= sp;            break= ;
         }
-       if (i =3D=3D plane->modifier_count= )
-            &n= bsp;  return false;
 
         /*
          * For D swizzle the = canonical modifier depends on the bpp, so check
--
2.36.1

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