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boundary="===============0732257761==" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" --===============0732257761== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_CH0PR12MB5348DB50C9C32FB21586F41C973E9CH0PR12MB5348namp_" --_000_CH0PR12MB5348DB50C9C32FB21586F41C973E9CH0PR12MB5348namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable [Public] May be just call it power_limit or power_cap similar to hwmon. The various = limits correspond to hwmon power[1-*]_cap and levels correspond to min/ max= etc. Thanks, Lijo From: Powell, Darren Sent: Tuesday, June 1, 2021 4:50 AM To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit function s= ignature [Public] >< > The limits are not limited to sample window. There are limits like APU= only limit, platform limit and totally obscure ones like PPT0/PPT1 etc. >It's better that the new enum takes care of those as well in case there is= a need to make them available through sysfs. I think you mean something more like this? + enum pp_power_constraints +{ + PP_PWR_CONSTRAINT_DEFAULT, + PP_PWR_CONSTRAINT_FASTWINDOW, +}; + ________________________________ From: Lazar, Lijo > Sent: Monday, May 31, 2021 2:04 AM To: Powell, Darren >; a= md-gfx@lists.freedesktop.org > Subject: RE: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit function s= ignature [Public] -----Original Message----- From: Powell, Darren > Sent: Saturday, May 29, 2021 4:36 AM To: amd-gfx@lists.freedesktop.org Cc: Powell, Darren > Subject: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit function signa= ture add two new powerplay enums (limit_level, sample_window) add enums to smu= _get_power_limit signature remove input bitfield stuffing of output variab= le limit update calls to smu_get_power_limit * Test AMDGPU_PCI_ADDR=3D`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMD= GPU_HWMON=3D`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -= f 10` HWMON_DIR=3D/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" ; \ echo "=3D=3D=3D power1 cap =3D=3D=3D" ; cat $HWMON_DIR/power1_cap ; = \ echo "=3D=3D=3D power1 cap max =3D=3D=3D" ; cat $HWMON_DIR/power1_cap_max = ; \ echo "=3D=3D=3D power1 cap def =3D=3D=3D" ; cat $HWMON_DIR/power1_cap_defa= ult Signed-off-by: Darren Powell > --- .../gpu/drm/amd/include/kgd_pp_interface.h | 14 ++++++++ drivers/gpu/drm/amd/pm/amdgpu_pm.c | 18 +++++----- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 3 +- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 34 +++++++++++++++++-- 4 files changed, 57 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/d= rm/amd/include/kgd_pp_interface.h index b1cd52a9d684..ddbf802ea8ad 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -192,6 +192,20 @@ enum pp_df_cstate { DF_CSTATE_ALLOW, }; +enum pp_power_limit_level +{ + PP_PWR_LIMIT_MIN =3D -1, + PP_PWR_LIMIT_CURRENT, + PP_PWR_LIMIT_DEFAULT, + PP_PWR_LIMIT_MAX, +}; + + enum pp_power_sample_window +{ + PP_PWR_WINDOW_DEFAULT, + PP_PWR_WINDOW_FAST, +}; + < > The limits are not limited to sample window. There are limits like APU = only limit, platform limit and totally obscure ones like PPT0/PPT1 etc. It's better that the new enum takes care of those as well in case there is = a need to make them available through sysfs. Thanks, Lijo #define PP_GROUP_MASK 0xF0000000 #define PP_GROUP_SHIFT 28 diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/am= dgpu_pm.c index 13da377888d2..f7b45803431d 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -2717,8 +2717,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct= device *dev, { struct amdgpu_device *adev =3D dev_get_drvdata(dev); const struct amd_pm_funcs *pp_funcs =3D adev->powerplay.pp_funcs; - int limit_type =3D to_sensor_dev_attr(attr)->index; - uint32_t limit =3D limit_type << 24; + enum pp_power_sample_window sample_window =3D to_sensor_dev_attr(at= tr)->index; + uint32_t limit; uint32_t max_limit =3D 0; ssize_t size; int r; @@ -2735,7 +2735,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct= device *dev, } if (is_support_sw_smu(adev)) { - smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX); + smu_get_power_limit(&adev->smu, &limit, PP_PWR_LIMIT_MAX, +sample_window); size =3D snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000)= ; } else if (pp_funcs && pp_funcs->get_power_limit) { pp_funcs->get_power_limit(adev->powerplay.pp_handle, @@ -2757,8 +2757,8 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct dev= ice *dev, { struct amdgpu_device *adev =3D dev_get_drvdata(dev); const struct amd_pm_funcs *pp_funcs =3D adev->powerplay.pp_funcs; - int limit_type =3D to_sensor_dev_attr(attr)->index; - uint32_t limit =3D limit_type << 24; + enum pp_power_sample_window sample_window =3D to_sensor_dev_attr(at= tr)->index; + uint32_t limit; ssize_t size; int r; @@ -2774,7 +2774,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct dev= ice *dev, } if (is_support_sw_smu(adev)) { - smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRE= NT); + smu_get_power_limit(&adev->smu, &limit, PP_PWR_LIMIT_CURREN= T, +sample_window); size =3D snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000)= ; } else if (pp_funcs && pp_funcs->get_power_limit) { pp_funcs->get_power_limit(adev->powerplay.pp_handle, @@ -2796,8 +2796,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(st= ruct device *dev, { struct amdgpu_device *adev =3D dev_get_drvdata(dev); const struct amd_pm_funcs *pp_funcs =3D adev->powerplay.pp_funcs; - int limit_type =3D to_sensor_dev_attr(attr)->index; - uint32_t limit =3D limit_type << 24; + enum pp_power_sample_window sample_window =3D to_sensor_dev_attr(at= tr)->index; + uint32_t limit; ssize_t size; int r; @@ -2813,7 +2813,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(st= ruct device *dev, } if (is_support_sw_smu(adev)) { - smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_DEFAU= LT); + smu_get_power_limit(&adev->smu, &limit, PP_PWR_LIMIT_DEFAUL= T, +sample_window); size =3D snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000)= ; } else if (pp_funcs && pp_funcs->get_power_limit) { pp_funcs->get_power_limit(adev->powerplay.pp_handle, diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/= pm/inc/amdgpu_smu.h index 523f9d2982e9..b97b960c2eac 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h @@ -1262,7 +1262,8 @@ enum smu_cmn2asic_mapping_type { #if !defined(SWSMU_= CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYE= R_L4) int smu_get_power_limit(struct smu_context *smu, uint32_t *limit, - enum smu_ppt_limit_level limit_level); + enum pp_power_limit_level pp_limit_level, + enum pp_power_sample_window sample_window); bool smu_mode1_reset_is_support(struct smu_context *smu); bool smu_mode2_= reset_is_support(struct smu_context *smu); diff --git a/drivers/gpu/drm/amd= /pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 8aff67a667fa..44c1baa2748d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2168,14 +2168,44 @@ static int smu_set_fan_speed_rpm(void *handle, uint= 32_t speed) int smu_get_power_limit(struct smu_context *smu, uint32_t *limit, - enum smu_ppt_limit_level limit_level) + enum pp_power_limit_level pp_limit_level, + enum pp_power_sample_window sample_window) { - uint32_t limit_type =3D *limit >> 24; + enum smu_ppt_limit_level limit_level; + uint32_t limit_type; int ret =3D 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) return -EOPNOTSUPP; + switch(sample_window) { + case PP_PWR_WINDOW_DEFAULT: + limit_type =3D SMU_DEFAULT_PPT_LIMIT; + break; + case PP_PWR_WINDOW_FAST: + limit_type =3D SMU_FAST_PPT_LIMIT; + break; + default: + return -EOPNOTSUPP; + break; + } + + switch(pp_limit_level){ + case PP_PWR_LIMIT_CURRENT: + limit_level =3D SMU_PPT_LIMIT_CURRENT; + break; + case PP_PWR_LIMIT_DEFAULT: + limit_level =3D SMU_PPT_LIMIT_DEFAULT; + break; + case PP_PWR_LIMIT_MAX: + limit_level =3D SMU_PPT_LIMIT_MAX; + break; + case PP_PWR_LIMIT_MIN: + default: + return -EOPNOTSUPP; + break; + } + mutex_lock(&smu->mutex); if (limit_type !=3D SMU_DEFAULT_PPT_LIMIT) { -- 2.25.1 --_000_CH0PR12MB5348DB50C9C32FB21586F41C973E9CH0PR12MB5348namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

[Public]

 

May be just call it power_limit or power_cap similar= to hwmon. The various limits correspond to hwmon power[1-*]_cap and levels= correspond to min/ max etc.

 

Thanks,

Lijo

 

From: Powell, Darren <Darren.Powell@amd.co= m>
Sent: Tuesday, June 1, 2021 4:50 AM
To: Lazar, Lijo <Lijo.Lazar@amd.com>; amd-gfx@lists.freedeskto= p.org
Subject: Re: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit fun= ction signature

 

[Public]

 


>< > The limits are not limited t= o sample window. There are limits like APU only limit, platform limit and t= otally obscure ones like PPT0/PPT1 etc.
>It's better that the new enum takes ca= re of those as well in case there is a need to make them available through = sysfs.

&n= bsp;

I think= you mean something more like this?

+ enum pp_power_constraints
+{
+       PP_P= WR_CONSTRAINT_DEFAULT,
+       PP_P= WR_CONSTRAINT_FASTWINDOW,
+};
+

&n= bsp;

&n= bsp;

From: Lazar, Lijo <Lijo.Lazar@amd.com>
Sent: Monday, May 31, 2021 2:04 AM
To: Powell, Darren <Darr= en.Powell@amd.com>; amd-gfx@lists.freedesktop.= org <amd-gfx@lists.= freedesktop.org>
Subject: RE: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit fun= ction signature

 

[Public]



-----Original Message-----
From: Powell, Darren <Darren.Po= well@amd.com>
Sent: Saturday, May 29, 2021 4:36 AM
To: amd-gfx@lists.freedesk= top.org
Cc: Powell, Darren <Darren.Powe= ll@amd.com>
Subject: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit function signa= ture

 add two new powerplay enums (limit_level, sample_window)  add en= ums to smu_get_power_limit signature  remove input bitfield stuffing o= f output variable limit  update calls to smu_get_power_limit

* Test
 AMDGPU_PCI_ADDR=3D`lspci -nn | grep "VGA\|Display" | cut -d= " " -f 1`  AMDGPU_HWMON=3D`ls -la /sys/class/hwmon | grep $= AMDGPU_PCI_ADDR | cut -d " " -f 10`  HWMON_DIR=3D/sys/class/= hwmon/${AMDGPU_HWMON}

 lspci -nn | grep "VGA\|Display" ; \
 echo "=3D=3D=3D power1 cap =3D=3D=3D" ; cat $HWMON_DIR/powe= r1_cap ;           \
 echo "=3D=3D=3D power1 cap max =3D=3D=3D" ; cat $HWMON_DIR/= power1_cap_max ;   \
 echo "=3D=3D=3D power1 cap def =3D=3D=3D" ; cat $HWMON_DIR/= power1_cap_default

Signed-off-by: Darren Powell <d= arren.powell@amd.com>
---
 .../gpu/drm/amd/include/kgd_pp_interface.h    | 14 +++= +++++
 drivers/gpu/drm/amd/pm/amdgpu_pm.c      = ;      | 18 +++++-----
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h     =   |  3 +-
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c     | 3= 4 +++++++++++++++++--
 4 files changed, 57 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/d= rm/amd/include/kgd_pp_interface.h
index b1cd52a9d684..ddbf802ea8ad 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -192,6 +192,20 @@ enum pp_df_cstate {
         DF_CSTATE_ALLOW,
 };
 
+enum pp_power_limit_level
+{
+       PP_PWR_LIMIT_MIN =3D -1,
+       PP_PWR_LIMIT_CURRENT,
+       PP_PWR_LIMIT_DEFAULT,
+       PP_PWR_LIMIT_MAX,
+};
+
+ enum pp_power_sample_window
+{
+       PP_PWR_WINDOW_DEFAULT,
+       PP_PWR_WINDOW_FAST,
+};
+

< > The limits are not limited to sample window. There are limits lik= e APU only limit, platform limit and totally obscure ones like PPT0/PPT1 et= c.
It's better that the new enum takes care of those as well in case there is = a need to make them available through sysfs.

Thanks,
Lijo

 #define PP_GROUP_MASK        0xF00= 00000
 #define PP_GROUP_SHIFT       28
 
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/am= dgpu_pm.c
index 13da377888d2..f7b45803431d 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2717,8 +2717,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct= device *dev,  {
         struct amdgpu_device *adev= =3D dev_get_drvdata(dev);
         const struct amd_pm_funcs = *pp_funcs =3D adev->powerplay.pp_funcs;
-       int limit_type =3D to_sensor_dev_attr= (attr)->index;
-       uint32_t limit =3D limit_type <<= ; 24;
+       enum pp_power_sample_window sample_wi= ndow =3D to_sensor_dev_attr(attr)->index;
+       uint32_t limit;
         uint32_t max_limit =3D 0;<= br>          ssize_t size;
         int r;
@@ -2735,7 +2735,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct= device *dev,
         }
 
         if (is_support_sw_smu(adev= )) {
-            &n= bsp;  smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT= _MAX);
+            &n= bsp;  smu_get_power_limit(&adev->smu, &limit, PP_PWR_LIMIT_= MAX,
+sample_window);
            &nb= sp;    size =3D snprintf(buf, PAGE_SIZE, "%u\n", l= imit * 1000000);
         } else if (pp_funcs &&= amp; pp_funcs->get_power_limit) {
            &nb= sp;    pp_funcs->get_power_limit(adev->powerplay.pp_ha= ndle,
@@ -2757,8 +2757,8 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct dev= ice *dev,  {
         struct amdgpu_device *adev= =3D dev_get_drvdata(dev);
         const struct amd_pm_funcs = *pp_funcs =3D adev->powerplay.pp_funcs;
-       int limit_type =3D to_sensor_dev_attr= (attr)->index;
-       uint32_t limit =3D limit_type <<= ; 24;
+       enum pp_power_sample_window sample_wi= ndow =3D to_sensor_dev_attr(attr)->index;
+       uint32_t limit;
         ssize_t size;
         int r;
 
@@ -2774,7 +2774,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct dev= ice *dev,
         }
 
         if (is_support_sw_smu(adev= )) {
-            &n= bsp;  smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT= _CURRENT);
+            &n= bsp;  smu_get_power_limit(&adev->smu, &limit, PP_PWR_LIMIT_= CURRENT,
+sample_window);
            &nb= sp;    size =3D snprintf(buf, PAGE_SIZE, "%u\n", l= imit * 1000000);
         } else if (pp_funcs &&= amp; pp_funcs->get_power_limit) {
            &nb= sp;    pp_funcs->get_power_limit(adev->powerplay.pp_ha= ndle,
@@ -2796,8 +2796,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(st= ruct device *dev,  {
         struct amdgpu_device *adev= =3D dev_get_drvdata(dev);
         const struct amd_pm_funcs = *pp_funcs =3D adev->powerplay.pp_funcs;
-       int limit_type =3D to_sensor_dev_attr= (attr)->index;
-       uint32_t limit =3D limit_type <<= ; 24;
+       enum pp_power_sample_window sample_wi= ndow =3D to_sensor_dev_attr(attr)->index;
+       uint32_t limit;
         ssize_t size;
         int r;
 
@@ -2813,7 +2813,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(st= ruct device *dev,
         }
 
         if (is_support_sw_smu(adev= )) {
-            &n= bsp;  smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT= _DEFAULT);
+            &n= bsp;  smu_get_power_limit(&adev->smu, &limit, PP_PWR_LIMIT_= DEFAULT,
+sample_window);
            &nb= sp;    size =3D snprintf(buf, PAGE_SIZE, "%u\n", l= imit * 1000000);
         } else if (pp_funcs &&= amp; pp_funcs->get_power_limit) {
            &nb= sp;    pp_funcs->get_power_limit(adev->powerplay.pp_ha= ndle,
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/= pm/inc/amdgpu_smu.h
index 523f9d2982e9..b97b960c2eac 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1262,7 +1262,8 @@ enum smu_cmn2asic_mapping_type {  #if !defined(S= WSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !de= fined(SWSMU_CODE_LAYER_L4)  int smu_get_power_limit(struct smu_context= *smu,
            &nb= sp;            uint3= 2_t *limit,
-            &n= bsp;          enum smu_ppt_lim= it_level limit_level);
+            &n= bsp;          enum pp_power_li= mit_level pp_limit_level,
+            &n= bsp;          enum pp_power_sa= mple_window sample_window);
 
 bool smu_mode1_reset_is_support(struct smu_context *smu);  bool = smu_mode2_reset_is_support(struct smu_context *smu); diff --git a/drivers/g= pu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.= c
index 8aff67a667fa..44c1baa2748d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2168,14 +2168,44 @@ static int smu_set_fan_speed_rpm(void *handle, uint= 32_t speed)
 
 int smu_get_power_limit(struct smu_context *smu,
            &nb= sp;            uint3= 2_t *limit,
-            &n= bsp;          enum smu_ppt_lim= it_level limit_level)
+            &n= bsp;          enum pp_power_li= mit_level pp_limit_level,
+            &n= bsp;          enum pp_power_sa= mple_window sample_window)
 {
-       uint32_t limit_type =3D *limit >&g= t; 24;
+       enum smu_ppt_limit_level limit_level;=
+       uint32_t limit_type;
         int ret =3D 0;
 
         if (!smu->pm_enabled ||= !smu->adev->pm.dpm_enabled)
            &nb= sp;    return -EOPNOTSUPP;
 
+       switch(sample_window) {
+       case PP_PWR_WINDOW_DEFAULT:
+            &n= bsp;  limit_type =3D SMU_DEFAULT_PPT_LIMIT;
+            &n= bsp;  break;
+       case PP_PWR_WINDOW_FAST:
+            &n= bsp;  limit_type =3D SMU_FAST_PPT_LIMIT;
+            &n= bsp;  break;
+       default:
+            &n= bsp;  return -EOPNOTSUPP;
+            &n= bsp;  break;
+       }
+
+       switch(pp_limit_level){
+       case PP_PWR_LIMIT_CURRENT:
+            &n= bsp;  limit_level =3D SMU_PPT_LIMIT_CURRENT;
+            &n= bsp;  break;
+       case PP_PWR_LIMIT_DEFAULT:
+            &n= bsp;  limit_level =3D SMU_PPT_LIMIT_DEFAULT;
+            &n= bsp;  break;
+       case PP_PWR_LIMIT_MAX:
+            &n= bsp;  limit_level =3D SMU_PPT_LIMIT_MAX;
+            &n= bsp;  break;
+       case PP_PWR_LIMIT_MIN:
+       default:
+            &n= bsp;  return -EOPNOTSUPP;
+            &n= bsp;  break;
+       }
+
         mutex_lock(&smu->mu= tex);
 
         if (limit_type !=3D SMU_DE= FAULT_PPT_LIMIT) {
--
2.25.1

--_000_CH0PR12MB5348DB50C9C32FB21586F41C973E9CH0PR12MB5348namp_-- --===============0732257761== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx --===============0732257761==--