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[62.163.246.182]) by smtp.gmail.com with ESMTPSA id bn14-20020a170906c0ce00b006c5ef0494besm6945946ejb.86.2022.03.21.07.21.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Mar 2022 07:21:57 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 21 Mar 2022 15:21:56 +0100 Message-Id: Cc: , <~postmarketos/upstreaming@lists.sr.ht>, , "Andy Gross" , "Linus Walleij" , "AngeloGioacchino Del Regno" , "Konrad Dybcio" , , Subject: Re: [PATCH v2 4/6] pinctrl: qcom: sm6350: fix order of UFS & SDC pins From: "Luca Weiss" To: "Bjorn Andersson" References: <20220321133318.99406-1-luca.weiss@fairphone.com> <20220321133318.99406-5-luca.weiss@fairphone.com> In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Bjorn, On Mon Mar 21, 2022 at 3:15 PM CET, Bjorn Andersson wrote: > On Mon 21 Mar 08:33 CDT 2022, Luca Weiss wrote: > > > In other places the SDC and UFS pins have been swapped but this was > > missed in the PINCTRL_PIN definitions. Fix that. > >=20 > > Fixes: 7d74b55afd27 ("pinctrl: qcom: Add SM6350 pinctrl driver") > > Signed-off-by: Luca Weiss > > Your proposed change looks good, but when I look at 7d74b55afd27 it > already has these entries in the correct order. > > Can you please confirm that this is still applicable. Or help me see > what I am missing. There are 3 times where number and description should match. For this UFS pin on sm6350 only 2/3 match. 2x the number is 156, 1x it's 163 $ grep -i ufs_reset drivers/pinctrl/qcom/pinctrl-sm6350.c PINCTRL_PIN(163, "UFS_RESET"), static const unsigned int ufs_reset_pins[] =3D { 156 }; [156] =3D UFS_RESET(ufs_reset, 0xae000), Does that help? Regards Luca > > Regards, > Bjorn > > > --- > > Changes in v2: > > - nothing > >=20 > > drivers/pinctrl/qcom/pinctrl-sm6350.c | 16 ++++++++-------- > > 1 file changed, 8 insertions(+), 8 deletions(-) > >=20 > > diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350.c b/drivers/pinctrl/qc= om/pinctrl-sm6350.c > > index 4d37b817b232..a91a86628f2f 100644 > > --- a/drivers/pinctrl/qcom/pinctrl-sm6350.c > > +++ b/drivers/pinctrl/qcom/pinctrl-sm6350.c > > @@ -264,14 +264,14 @@ static const struct pinctrl_pin_desc sm6350_pins[= ] =3D { > > PINCTRL_PIN(153, "GPIO_153"), > > PINCTRL_PIN(154, "GPIO_154"), > > PINCTRL_PIN(155, "GPIO_155"), > > - PINCTRL_PIN(156, "SDC1_RCLK"), > > - PINCTRL_PIN(157, "SDC1_CLK"), > > - PINCTRL_PIN(158, "SDC1_CMD"), > > - PINCTRL_PIN(159, "SDC1_DATA"), > > - PINCTRL_PIN(160, "SDC2_CLK"), > > - PINCTRL_PIN(161, "SDC2_CMD"), > > - PINCTRL_PIN(162, "SDC2_DATA"), > > - PINCTRL_PIN(163, "UFS_RESET"), > > + PINCTRL_PIN(156, "UFS_RESET"), > > + PINCTRL_PIN(157, "SDC1_RCLK"), > > + PINCTRL_PIN(158, "SDC1_CLK"), > > + PINCTRL_PIN(159, "SDC1_CMD"), > > + PINCTRL_PIN(160, "SDC1_DATA"), > > + PINCTRL_PIN(161, "SDC2_CLK"), > > + PINCTRL_PIN(162, "SDC2_CMD"), > > + PINCTRL_PIN(163, "SDC2_DATA"), > > }; > > =20 > > #define DECLARE_MSM_GPIO_PINS(pin) \ > > --=20 > > 2.35.1 > >=20