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	boundary="_73385e28-778d-4164-bf0e-3af1b91969e4_"
From: Chen Gang <xili_gchen_5257@hotmail.com>
Date: Sun, 8 Nov 2015 13:47:33 +0800
In-Reply-To: <COL130-W26C8810524FA22F97ACDECB9160@phx.gbl>
References: <COL130-W26C8810524FA22F97ACDECB9160@phx.gbl>
MIME-Version: 1.0
Subject: [Qemu-devel] [PATCH 4/4] target-tilegx: Let fpu implementation code
 can be built and used
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To: "rth@twiddle.net" <rth@twiddle.net>, Peter Maydell <peter.maydell@linaro.org>, Chris Metcalf <cmetcalf@ezchip.com>
Cc: qemu-devel <qemu-devel@nongnu.org>

--_73385e28-778d-4164-bf0e-3af1b91969e4_
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>>From 8fab455a5ac5508d06cc69f778e926ad098fbe5b Mon Sep 17 00:00:00 2001=0A=
From: Chen Gang <gang.chen.5i5j@gmail.com>=0A=
Date: Sun=2C 8 Nov 2015 09:11:36 +0800=0A=
Subject: [PATCH 4/4] target-tilegx: Let fpu implementation code can be buil=
t=0A=
=A0and used=0A=
=0A=
It passes gcc testsuite: it can get the same result as the original fpu=0A=
implementation have done.=0A=
=0A=
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>=0A=
---=0A=
=A0target-tilegx/Makefile.objs | =A03 +-=0A=
=A0target-tilegx/cpu.h =A0 =A0 =A0 =A0 | =A02 ++=0A=
=A0target-tilegx/helper.h =A0 =A0 =A0| 12 ++++++++=0A=
=A0target-tilegx/translate.c =A0 | 68 +++++++++++++++++++++++++++++++++++++=
++------=0A=
=A04 files changed=2C 75 insertions(+)=2C 10 deletions(-)=0A=
=0A=
diff --git a/target-tilegx/Makefile.objs b/target-tilegx/Makefile.objs=0A=
index 0db778f..c2cf2f1 100644=0A=
--- a/target-tilegx/Makefile.objs=0A=
+++ b/target-tilegx/Makefile.objs=0A=
@@ -1 +1=2C2 @@=0A=
-obj-y +=3D cpu.o translate.o helper.o simd_helper.o=0A=
+obj-y +=3D cpu.o translate.o helper.o simd_helper.o \=0A=
+		fsingle_helper.o fdouble_helper.o=0A=
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h=0A=
index 03df107..445a606 100644=0A=
--- a/target-tilegx/cpu.h=0A=
+++ b/target-tilegx/cpu.h=0A=
@@ -88=2C6 +88=2C8 @@ typedef struct CPUTLGState {=0A=
=A0 =A0 =A0uint64_t spregs[TILEGX_SPR_COUNT]=3B /* Special used registers b=
y outside */=0A=
=A0 =A0 =A0uint64_t pc=3B =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* Cu=
rrent pc */=0A=
=A0=0A=
+ =A0 =A0float_status fp_status=3B =A0 =A0 =A0 =A0 =A0 =A0/* floating point=
 status */=0A=
+=0A=
=A0#if defined(CONFIG_USER_ONLY)=0A=
=A0 =A0 =A0uint64_t excaddr=3B =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* except=
ion address */=0A=
=A0 =A0 =A0uint64_t atomic_srca=3B =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Arguments =
to atomic "exceptions" */=0A=
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h=0A=
index 9281d0f..b785bf2 100644=0A=
--- a/target-tilegx/helper.h=0A=
+++ b/target-tilegx/helper.h=0A=
@@ -24=2C3 +24=2C15 @@ DEF_HELPER_FLAGS_2(v1shrs=2C TCG_CALL_NO_RWG_SE=2C i=
64=2C i64=2C i64)=0A=
=A0DEF_HELPER_FLAGS_2(v2shl=2C TCG_CALL_NO_RWG_SE=2C i64=2C i64=2C i64)=0A=
=A0DEF_HELPER_FLAGS_2(v2shru=2C TCG_CALL_NO_RWG_SE=2C i64=2C i64=2C i64)=0A=
=A0DEF_HELPER_FLAGS_2(v2shrs=2C TCG_CALL_NO_RWG_SE=2C i64=2C i64=2C i64)=0A=
+=0A=
+DEF_HELPER_3(fsingle_add1=2C i64=2C env=2C i64=2C i64)=0A=
+DEF_HELPER_3(fsingle_sub1=2C i64=2C env=2C i64=2C i64)=0A=
+DEF_HELPER_3(fsingle_mul1=2C i64=2C env=2C i64=2C i64)=0A=
+DEF_HELPER_2(fsingle_pack2=2C i64=2C env=2C i64)=0A=
+DEF_HELPER_3(fdouble_unpack_min=2C i64=2C env=2C i64=2C i64)=0A=
+DEF_HELPER_3(fdouble_unpack_max=2C i64=2C env=2C i64=2C i64)=0A=
+DEF_HELPER_3(fdouble_add_flags=2C i64=2C env=2C i64=2C i64)=0A=
+DEF_HELPER_3(fdouble_sub_flags=2C i64=2C env=2C i64=2C i64)=0A=
+DEF_HELPER_4(fdouble_addsub=2C i64=2C env=2C i64=2C i64=2C i64)=0A=
+DEF_HELPER_3(fdouble_mul_flags=2C i64=2C env=2C i64=2C i64)=0A=
+DEF_HELPER_4(fdouble_pack2=2C i64=2C env=2C i64=2C i64=2C i64)=0A=
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c=0A=
index b8ca401..4d74b1d 100644=0A=
--- a/target-tilegx/translate.c=0A=
+++ b/target-tilegx/translate.c=0A=
@@ -597=2C6 +597=2C11 @@ static TileExcp gen_rr_opcode(DisasContext *dc=2C =
unsigned opext=2C=0A=
=A0 =A0 =A0 =A0 =A0}=0A=
=A0 =A0 =A0 =A0 =A0qemu_log_mask(CPU_LOG_TB_IN_ASM=2C "%s %s"=2C mnemonic=
=2C reg_names[srca])=3B=0A=
=A0 =A0 =A0 =A0 =A0return ret=3B=0A=
+=0A=
+ =A0 =A0case OE_RR_X0(FSINGLE_PACK1):=0A=
+ =A0 =A0case OE_RR_Y0(FSINGLE_PACK1):=0A=
+ =A0 =A0 =A0 =A0mnemonic =3D "fsingle_pack1"=3B=0A=
+ =A0 =A0 =A0 =A0goto done2=3B=0A=
=A0 =A0 =A0}=0A=
=A0=0A=
=A0 =A0 =A0tdest =3D dest_gr(dc=2C dest)=3B=0A=
@@ -613=2C9 +618=2C6 @@ static TileExcp gen_rr_opcode(DisasContext *dc=2C u=
nsigned opext=2C=0A=
=A0 =A0 =A0 =A0 =A0gen_helper_cnttz(tdest=2C tsrca)=3B=0A=
=A0 =A0 =A0 =A0 =A0mnemonic =3D "cnttz"=3B=0A=
=A0 =A0 =A0 =A0 =A0break=3B=0A=
- =A0 =A0case OE_RR_X0(FSINGLE_PACK1):=0A=
- =A0 =A0case OE_RR_Y0(FSINGLE_PACK1):=0A=
- =A0 =A0 =A0 =A0return TILEGX_EXCP_OPCODE_UNIMPLEMENTED=3B=0A=
=A0 =A0 =A0case OE_RR_X1(LD1S):=0A=
=A0 =A0 =A0 =A0 =A0memop =3D MO_SB=3B=0A=
=A0 =A0 =A0 =A0 =A0mnemonic =3D "ld1s"=3B /* prefetch_l1_fault */=0A=
@@ -734=2C6 +736=2C7 @@ static TileExcp gen_rr_opcode(DisasContext *dc=2C u=
nsigned opext=2C=0A=
=A0 =A0 =A0 =A0 =A0return TILEGX_EXCP_OPCODE_UNKNOWN=3B=0A=
=A0 =A0 =A0}=0A=
=A0=0A=
+done2:=0A=
=A0 =A0 =A0qemu_log_mask(CPU_LOG_TB_IN_ASM=2C "%s %s=2C %s"=2C mnemonic=2C=
=0A=
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg_names[dest]=2C reg_names[srca])=
=3B=0A=
=A0 =A0 =A0return ret=3B=0A=
@@ -742=2C13 +745=2C21 @@ static TileExcp gen_rr_opcode(DisasContext *dc=2C=
 unsigned opext=2C=0A=
=A0static TileExcp gen_rrr_opcode(DisasContext *dc=2C unsigned opext=2C=0A=
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 unsigned de=
st=2C unsigned srca=2C unsigned srcb)=0A=
=A0{=0A=
- =A0 =A0TCGv tdest =3D dest_gr(dc=2C dest)=3B=0A=
- =A0 =A0TCGv tsrca =3D load_gr(dc=2C srca)=3B=0A=
- =A0 =A0TCGv tsrcb =3D load_gr(dc=2C srcb)=3B=0A=
+ =A0 =A0TCGv tdest=2C tsrca=2C tsrcb=3B=0A=
=A0 =A0 =A0TCGv t0=3B=0A=
=A0 =A0 =A0const char *mnemonic=3B=0A=
=A0=0A=
=A0 =A0 =A0switch (opext) {=0A=
+ =A0 =A0case OE_RRR(FSINGLE_ADDSUB2=2C 0=2C X0):=0A=
+ =A0 =A0 =A0 =A0mnemonic =3D "fsingle_addsub2"=3B=0A=
+ =A0 =A0 =A0 =A0goto done2=3B=0A=
+ =A0 =A0}=0A=
+=0A=
+ =A0 =A0tdest =3D dest_gr(dc=2C dest)=3B=0A=
+ =A0 =A0tsrca =3D load_gr(dc=2C srca)=3B=0A=
+ =A0 =A0tsrcb =3D load_gr(dc=2C srcb)=3B=0A=
+=0A=
+ =A0 =A0switch (opext) {=0A=
=A0 =A0 =A0case OE_RRR(ADDXSC=2C 0=2C X0):=0A=
=A0 =A0 =A0case OE_RRR(ADDXSC=2C 0=2C X1):=0A=
=A0 =A0 =A0 =A0 =A0gen_saturate_op(tdest=2C tsrca=2C tsrcb=2C tcg_gen_add_t=
l)=3B=0A=
@@ -906=2C14 +917=2C39 @@ static TileExcp gen_rrr_opcode(DisasContext *dc=
=2C unsigned opext=2C=0A=
=A0 =A0 =A0 =A0 =A0mnemonic =3D "exch"=3B=0A=
=A0 =A0 =A0 =A0 =A0break=3B=0A=
=A0 =A0 =A0case OE_RRR(FDOUBLE_ADDSUB=2C 0=2C X0):=0A=
+ =A0 =A0 =A0 =A0gen_helper_fdouble_addsub(tdest=2C cpu_env=2C=0A=
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0load_g=
r(dc=2C dest)=2Ctsrca=2C tsrcb)=3B=0A=
+ =A0 =A0 =A0 =A0mnemonic =3D "fdouble_addsub"=3B=0A=
+ =A0 =A0 =A0 =A0break=3B=0A=
=A0 =A0 =A0case OE_RRR(FDOUBLE_ADD_FLAGS=2C 0=2C X0):=0A=
+ =A0 =A0 =A0 =A0gen_helper_fdouble_add_flags(tdest=2C cpu_env=2C tsrca=2C =
tsrcb)=3B=0A=
+ =A0 =A0 =A0 =A0mnemonic =3D "fdouble_add_flags"=3B=0A=
+ =A0 =A0 =A0 =A0break=3B=0A=
=A0 =A0 =A0case OE_RRR(FDOUBLE_MUL_FLAGS=2C 0=2C X0):=0A=
+ =A0 =A0 =A0 =A0gen_helper_fdouble_mul_flags(tdest=2C cpu_env=2C tsrca=2C =
tsrcb)=3B=0A=
+ =A0 =A0 =A0 =A0mnemonic =3D "fdouble_mul_flags"=3B=0A=
+ =A0 =A0 =A0 =A0break=3B=0A=
=A0 =A0 =A0case OE_RRR(FDOUBLE_PACK1=2C 0=2C X0):=0A=
+ =A0 =A0 =A0 =A0tcg_gen_mov_i64(tdest=2C tsrcb)=3B=0A=
+ =A0 =A0 =A0 =A0mnemonic =3D "fdouble_pack1"=3B=0A=
+ =A0 =A0 =A0 =A0break=3B=0A=
=A0 =A0 =A0case OE_RRR(FDOUBLE_PACK2=2C 0=2C X0):=0A=
+ =A0 =A0 =A0 =A0gen_helper_fdouble_pack2(tdest=2C cpu_env=2C=0A=
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 load_gr(d=
c=2C dest)=2C tsrca=2C tsrcb)=3B=0A=
+ =A0 =A0 =A0 =A0mnemonic =3D "fdouble_pack2"=3B=0A=
+ =A0 =A0 =A0 =A0break=3B=0A=
=A0 =A0 =A0case OE_RRR(FDOUBLE_SUB_FLAGS=2C 0=2C X0):=0A=
+ =A0 =A0 =A0 =A0gen_helper_fdouble_sub_flags(tdest=2C cpu_env=2C tsrca=2C =
tsrcb)=3B=0A=
+ =A0 =A0 =A0 =A0mnemonic =3D "fdouble_sub_flags"=3B=0A=
+ =A0 =A0 =A0 =A0break=3B=0A=
=A0 =A0 =A0case OE_RRR(FDOUBLE_UNPACK_MAX=2C 0=2C X0):=0A=
+ =A0 =A0 =A0 =A0gen_helper_fdouble_unpack_max(tdest=2C cpu_env=2C tsrca=2C=
 tsrcb)=3B=0A=
+ =A0 =A0 =A0 =A0mnemonic =3D "fdouble_unpack_max"=3B=0A=
+ =A0 =A0 =A0 =A0break=3B=0A=
=A0 =A0 =A0case OE_RRR(FDOUBLE_UNPACK_MIN=2C 0=2C X0):=0A=
- =A0 =A0 =A0 =A0return TILEGX_EXCP_OPCODE_UNIMPLEMENTED=3B=0A=
+ =A0 =A0 =A0 =A0gen_helper_fdouble_unpack_min(tdest=2C cpu_env=2C tsrca=2C=
 tsrcb)=3B=0A=
+ =A0 =A0 =A0 =A0mnemonic =3D "fdouble_unpack_min"=3B=0A=
+ =A0 =A0 =A0 =A0break=3B=0A=
=A0 =A0 =A0case OE_RRR(FETCHADD4=2C 0=2C X1):=0A=
=A0 =A0 =A0 =A0 =A0gen_atomic_excp(dc=2C dest=2C tdest=2C tsrca=2C tsrcb=2C=
=0A=
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0TILEGX_EXCP_OPCODE_FETCH=
ADD4)=3B=0A=
@@ -955=2C12 +991=2C25 @@ static TileExcp gen_rrr_opcode(DisasContext *dc=
=2C unsigned opext=2C=0A=
=A0 =A0 =A0 =A0 =A0mnemonic =3D "fetchor"=3B=0A=
=A0 =A0 =A0 =A0 =A0break=3B=0A=
=A0 =A0 =A0case OE_RRR(FSINGLE_ADD1=2C 0=2C X0):=0A=
- =A0 =A0case OE_RRR(FSINGLE_ADDSUB2=2C 0=2C X0):=0A=
+ =A0 =A0 =A0 =A0gen_helper_fsingle_add1(tdest=2C cpu_env=2C tsrca=2C tsrcb=
)=3B=0A=
+ =A0 =A0 =A0 =A0mnemonic =3D "fsingle_add1"=3B=0A=
+ =A0 =A0 =A0 =A0break=3B=0A=
=A0 =A0 =A0case OE_RRR(FSINGLE_MUL1=2C 0=2C X0):=0A=
+ =A0 =A0 =A0 =A0gen_helper_fsingle_mul1(tdest=2C cpu_env=2C tsrca=2C tsrcb=
)=3B=0A=
+ =A0 =A0 =A0 =A0mnemonic =3D "fsingle_mul1"=3B=0A=
+ =A0 =A0 =A0 =A0break=3B=0A=
=A0 =A0 =A0case OE_RRR(FSINGLE_MUL2=2C 0=2C X0):=0A=
+ =A0 =A0 =A0 =A0tcg_gen_mov_i64(tdest=2C tsrca)=3B=0A=
+ =A0 =A0 =A0 =A0mnemonic =3D "fsingle_mul2"=3B=0A=
+ =A0 =A0 =A0 =A0break=3B=0A=
=A0 =A0 =A0case OE_RRR(FSINGLE_PACK2=2C 0=2C X0):=0A=
+ =A0 =A0 =A0 =A0gen_helper_fsingle_pack2(tdest=2C cpu_env=2C tsrca)=3B=0A=
+ =A0 =A0 =A0 =A0mnemonic =3D "fsingle_pack2"=3B=0A=
+ =A0 =A0 =A0 =A0break=3B=0A=
=A0 =A0 =A0case OE_RRR(FSINGLE_SUB1=2C 0=2C X0):=0A=
- =A0 =A0 =A0 =A0return TILEGX_EXCP_OPCODE_UNIMPLEMENTED=3B=0A=
+ =A0 =A0 =A0 =A0gen_helper_fsingle_sub1(tdest=2C cpu_env=2C tsrca=2C tsrcb=
)=3B=0A=
+ =A0 =A0 =A0 =A0mnemonic =3D "fsingle_sub1"=3B=0A=
+ =A0 =A0 =A0 =A0break=3B=0A=
=A0 =A0 =A0case OE_RRR(MNZ=2C 0=2C X0):=0A=
=A0 =A0 =A0case OE_RRR(MNZ=2C 0=2C X1):=0A=
=A0 =A0 =A0case OE_RRR(MNZ=2C 4=2C Y0):=0A=
@@ -1464=2C6 +1513=2C7 @@ static TileExcp gen_rrr_opcode(DisasContext *dc=
=2C unsigned opext=2C=0A=
=A0 =A0 =A0 =A0 =A0return TILEGX_EXCP_OPCODE_UNKNOWN=3B=0A=
=A0 =A0 =A0}=0A=
=A0=0A=
+done2:=0A=
=A0 =A0 =A0qemu_log_mask(CPU_LOG_TB_IN_ASM=2C "%s %s=2C %s=2C %s"=2C mnemon=
ic=2C=0A=
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg_names[dest]=2C reg_names[srca]=
=2C reg_names[srcb])=3B=0A=
=A0 =A0 =A0return TILEGX_EXCP_NONE=3B=0A=
--=A0=0A=
1.9.3=0A=
=0A=
 		 	   		  =

--_73385e28-778d-4164-bf0e-3af1b91969e4_
Content-Type: application/octet-stream
Content-Transfer-Encoding: base64
Content-Disposition: attachment;
	filename="0004-target-tilegx-Let-fpu-implementation-code-can-be-bui.patch"

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