From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38562) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZvIoB-00073G-OF for qemu-devel@nongnu.org; Sun, 08 Nov 2015 00:46:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZvIo8-0000Kz-Ch for qemu-devel@nongnu.org; Sun, 08 Nov 2015 00:46:31 -0500 Received: from col004-omc2s8.hotmail.com ([65.55.34.82]:55560) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZvIo7-0000Kv-TR for qemu-devel@nongnu.org; Sun, 08 Nov 2015 00:46:28 -0500 Message-ID: Content-Type: multipart/mixed; boundary="_9d578a43-f8ff-4f18-90d5-7665caefb7c6_" From: Chen Gang Date: Sun, 8 Nov 2015 13:46:26 +0800 In-Reply-To: References: MIME-Version: 1.0 Subject: [Qemu-devel] [PATCH 3/4] target-tilegx: Implement fpu fdouble floating point List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "rth@twiddle.net" , Peter Maydell , Chris Metcalf Cc: qemu-devel --_9d578a43-f8ff-4f18-90d5-7665caefb7c6_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable >>From c467db1c0a5f4c6560b8bdddd2115732aa718c4b Mon Sep 17 00:00:00 2001=0A= From: Chen Gang =0A= Date: Sun=2C 8 Nov 2015 09:10:17 +0800=0A= Subject: [PATCH 3/4] target-tilegx: Implement fpu fdouble floating point=0A= =A0instructions=0A= =0A= Signed-off-by: Chen Gang =0A= ---=0A= =A0target-tilegx/fdouble_helper.c | 290 +++++++++++++++++++++++++++++++++++= ++++++=0A= =A01 file changed=2C 290 insertions(+)=0A= =A0create mode 100644 target-tilegx/fdouble_helper.c=0A= =0A= diff --git a/target-tilegx/fdouble_helper.c b/target-tilegx/fdouble_helper.= c=0A= new file mode 100644=0A= index 0000000..7ba0583=0A= --- /dev/null=0A= +++ b/target-tilegx/fdouble_helper.c=0A= @@ -0=2C0 +1=2C290 @@=0A= +/*=0A= + * QEMU TILE-Gx helpers=0A= + *=0A= + * =A0Copyright (c) 2015 Chen Gang=0A= + *=0A= + * This library is free software=3B you can redistribute it and/or=0A= + * modify it under the terms of the GNU Lesser General Public=0A= + * License as published by the Free Software Foundation=3B either=0A= + * version 2.1 of the License=2C or (at your option) any later version.=0A= + *=0A= + * This library is distributed in the hope that it will be useful=2C=0A= + * but WITHOUT ANY WARRANTY=3B without even the implied warranty of=0A= + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =A0See the GNU=0A= + * Lesser General Public License for more details.=0A= + *=0A= + * You should have received a copy of the GNU Lesser General Public=0A= + * License along with this library=3B if not=2C see=0A= + * =0A= + */=0A= +=0A= +#include "cpu.h"=0A= +#include "qemu-common.h"=0A= +#include "exec/helper-proto.h"=0A= +#include "fpu/softfloat.h"=0A= +=0A= +#include "fpu.h"=0A= +=0A= +#define TILEGX_F_MAN_HBIT =A0 =A0 =A0 =A0(1ULL << 59)=0A= +=0A= +#pragma pack(push=2C 1)=0A= +typedef union F64Fmt {=0A= + =A0 =A0float64 d=3B=0A= + =A0 =A0struct {=0A= +#if defined(HOST_WORDS_BIGENDIAN)=0A= + =A0 =A0 =A0 =A0uint64_t sign : 1=3B=0A= + =A0 =A0 =A0 =A0uint64_t exp =A0: 11=3B=0A= + =A0 =A0 =A0 =A0uint64_t frac : 52=3B=0A= +#else=0A= + =A0 =A0 =A0 =A0uint64_t frac : 52=3B=0A= + =A0 =A0 =A0 =A0uint64_t exp =A0: 11=3B=0A= + =A0 =A0 =A0 =A0uint64_t sign : 1=3B=0A= +#endif=0A= + =A0 =A0} bits=3B=0A= +} F64Fmt=3B=0A= +#pragma pack(pop)=0A= +=0A= +static uint64_t fr_to_man(F64Fmt v)=0A= +{=0A= + =A0 =A0uint64_t val =3D (uint64_t)v.bits.frac << 7=3B=0A= +=0A= + =A0 =A0if (v.bits.exp)=0A= + =A0 =A0 =A0 =A0val |=3D TILEGX_F_MAN_HBIT=3B=0A= +=0A= + =A0 =A0return val=3B=0A= +}=0A= +=0A= +uint64_t helper_fdouble_unpack_min(CPUTLGState *env=2C=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 uint6= 4_t srca=2C uint64_t srcb)=0A= +{=0A= + =A0 =A0F64Fmt va=2C vb=3B=0A= + =A0 =A0TileGXFPDFmtV v=3B=0A= +=0A= + =A0 =A0va.d =3D make_float64(srca)=3B=0A= + =A0 =A0vb.d =3D make_float64(srcb)=3B=0A= + =A0 =A0v.ll =3D 0=3B /* also cause v.fmt.overflow =3D 0 */=0A= +=0A= + =A0 =A0if (float64_is_any_nan(srca) || float64_is_any_nan(srcb)=0A= + =A0 =A0 =A0 =A0|| float64_is_infinity(srca) || float64_is_infinity(srcb))= =0A= + =A0 =A0 =A0 =A0=3B=0A= + =A0 =A0else if (va.bits.exp> vb.bits.exp) {=0A= + =A0 =A0 =A0 =A0if (va.bits.exp - vb.bits.exp < 64)=0A= + =A0 =A0 =A0 =A0 =A0 =A0v.fmt.mantissa =3D fr_to_man(vb)>> (va.bits.exp - = vb.bits.exp)=3B=0A= + =A0 =A0} else if (va.bits.exp < vb.bits.exp) {=0A= + =A0 =A0 =A0 =A0if (vb.bits.exp - va.bits.exp < 64)=0A= + =A0 =A0 =A0 =A0 =A0 =A0v.fmt.mantissa =3D fr_to_man(va)>> (vb.bits.exp - = va.bits.exp)=3B=0A= + =A0 =A0} else if (va.bits.frac> vb.bits.frac)=0A= + =A0 =A0 =A0 =A0v.fmt.mantissa =3D fr_to_man(vb)=3B=0A= + =A0 =A0else=0A= + =A0 =A0 =A0 =A0v.fmt.mantissa =3D fr_to_man(va)=3B=0A= +=0A= + =A0 =A0return v.ll=3B=0A= +}=0A= +=0A= +uint64_t helper_fdouble_unpack_max(CPUTLGState *env=2C=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 uint6= 4_t srca=2C uint64_t srcb)=0A= +{=0A= + =A0 =A0F64Fmt va=2C vb=3B=0A= + =A0 =A0TileGXFPDFmtV v=3B=0A= +=0A= + =A0 =A0va.d =3D make_float64(srca)=3B=0A= + =A0 =A0vb.d =3D make_float64(srcb)=3B=0A= + =A0 =A0v.ll =3D 0=3B /* also cause v.fmt.overflow =3D 0 */=0A= +=0A= + =A0 =A0if (float64_is_any_nan(srca) || float64_is_any_nan(srcb)=0A= + =A0 =A0 =A0 =A0|| float64_is_infinity(srca) || float64_is_infinity(srcb))= =0A= + =A0 =A0 =A0 =A0=3B=0A= + =A0 =A0else if (va.bits.exp> vb.bits.exp)=0A= + =A0 =A0 =A0 =A0v.fmt.mantissa =3D fr_to_man(va)=3B=0A= + =A0 =A0else if (va.bits.exp < vb.bits.exp)=0A= + =A0 =A0 =A0 =A0v.fmt.mantissa =3D fr_to_man(vb)=3B=0A= + =A0 =A0else if (va.bits.frac> vb.bits.frac)=0A= + =A0 =A0 =A0 =A0v.fmt.mantissa =3D fr_to_man(va)=3B=0A= + =A0 =A0else=0A= + =A0 =A0 =A0 =A0v.fmt.mantissa =3D fr_to_man(vb)=3B=0A= +=0A= + =A0 =A0return v.ll=3B=0A= +}=0A= +=0A= +uint64_t helper_fdouble_addsub(CPUTLGState *env=2C=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 uint64_t dest= =2C uint64_t srca=2C uint64_t srcb)=0A= +{=0A= + =A0 =A0TileGXFPDFmtF flags=3B=0A= + =A0 =A0TileGXFPDFmtV v=3B=0A= +=0A= + =A0 =A0flags.ll =3D srcb=3B=0A= + =A0 =A0if (flags.fmt.calc =3D=3D TILEGX_F_CALC_ADD) {=0A= + =A0 =A0 =A0 =A0v.ll =3D dest + srca=3B /* maybe set addsub overflow bit *= /=0A= + =A0 =A0} else=0A= + =A0 =A0 =A0 =A0v.ll =3D dest - srca=3B=0A= +=0A= + =A0 =A0return v.ll=3B=0A= +}=0A= +=0A= +/* absolute-add/mul may cause add/mul carry or overflow */=0A= +static bool proc_oflow(TileGXFPDFmtF *flags=2C TileGXFPDFmtV *v=2C uint64_= t *srcb)=0A= +{=0A= + =A0 =A0if (v->fmt.overflow) {=0A= + =A0 =A0 =A0 =A0flags->fmt.vexp++=3B=0A= + =A0 =A0 =A0 =A0*srcb>>=3D 1=3B=0A= + =A0 =A0 =A0 =A0*srcb |=3D (uint64_t)v->ll << 63=3B=0A= + =A0 =A0 =A0 =A0v->ll>>=3D 1=3B=0A= + =A0 =A0 =A0 =A0v->fmt.overflow =3D 0=3B=0A= + =A0 =A0}=0A= + =A0 =A0return flags->fmt.vexp> TILEGX_F_EXP_DMAX=3B=0A= +}=0A= +=0A= +uint64_t helper_fdouble_pack2(CPUTLGState *env=2C=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0uint64_t dest= =2C uint64_t srca=2C uint64_t srcb)=0A= +{=0A= + =A0 =A0TileGXFPDFmtF flags=3B=0A= + =A0 =A0TileGXFPDFmtV v=3B=0A= + =A0 =A0F64Fmt d=3B=0A= +=0A= + =A0 =A0flags.ll =3D dest=3B=0A= + =A0 =A0v.ll =3D srca=3B=0A= +=0A= + =A0 =A0d.d =3D 0=3B=0A= + =A0 =A0d.bits.sign =3D flags.fmt.sign=3B=0A= +=0A= + =A0 =A0/*=0A= + =A0 =A0 * fdouble_add_flags=2C fdouble_sub_flags=2C or fdouble_mul_flags = have=0A= + =A0 =A0 * processed exceptions. So need not process fp_status=2C again.= =0A= + =A0 =A0 */=0A= +=0A= + =A0 =A0if (flags.fmt.nan)=0A= + =A0 =A0 =A0 =A0return float64_val(float64_default_nan)=3B=0A= + =A0 =A0else if (flags.fmt.inf)=0A= + =A0 =A0 =A0 =A0return float64_val(d.d |=3D float64_infinity)=3B=0A= +=0A= + =A0 =A0/* absolute-mul needs left shift 4 + 1 bytes to match the real man= tissa */=0A= + =A0 =A0if (flags.fmt.calc =3D=3D TILEGX_F_CALC_MUL) {=0A= + =A0 =A0 =A0 =A0v.ll <<=3D 5=3B=0A= + =A0 =A0 =A0 =A0v.ll |=3D srcb>> 59=3B=0A= + =A0 =A0 =A0 =A0srcb <<=3D 5=3B=0A= + =A0 =A0}=0A= +=0A= + =A0 =A0if (flags.fmt.vexp & TILEGX_F_EXP_DUF) /* must check underflow=2C = firstly */=0A= + =A0 =A0 =A0 =A0return float64_val(d.d)=3B=0A= +=0A= + =A0 =A0if (proc_oflow(&flags=2C &v=2C &srcb))=0A= + =A0 =A0 =A0 =A0return float64_val(d.d |=3D float64_infinity)=3B=0A= +=0A= + =A0 =A0while (!(v.fmt.mantissa & TILEGX_F_MAN_HBIT) && (v.fmt.mantissa | = srcb)) {=0A= + =A0 =A0 =A0 =A0flags.fmt.vexp--=3B=0A= + =A0 =A0 =A0 =A0v.fmt.mantissa <<=3D 1=3B=0A= + =A0 =A0 =A0 =A0v.fmt.mantissa |=3D srcb>> 63=3B=0A= + =A0 =A0 =A0 =A0srcb <<=3D 1=3B=0A= + =A0 =A0}=0A= +=0A= + =A0 =A0/* check underflow=2C again=2C after format */=0A= + =A0 =A0if ((flags.fmt.vexp & TILEGX_F_EXP_DUF) || !v.fmt.mantissa)=0A= + =A0 =A0 =A0 =A0return float64_val(d.d)=3B=0A= +=0A= + =A0 =A0if (flags.fmt.sign)=0A= + =A0 =A0 =A0 =A0d.d =3D int64_to_float64(0 - (int64_t)v.fmt.mantissa=2C &e= nv->fp_status)=3B=0A= + =A0 =A0else=0A= + =A0 =A0 =A0 =A0d.d =3D uint64_to_float64((uint64_t)v.fmt.mantissa=2C &env= ->fp_status)=3B=0A= +=0A= + =A0 =A0if (d.bits.exp =3D=3D 59 + TILEGX_F_EXP_DZERO)=0A= + =A0 =A0 =A0 =A0d.bits.exp =3D flags.fmt.vexp=3B=0A= + =A0 =A0else { =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* f= or carry and overflow again */=0A= + =A0 =A0 =A0 =A0d.bits.exp =3D flags.fmt.vexp + 1=3B=0A= + =A0 =A0 =A0 =A0if (d.bits.exp =3D=3D TILEGX_F_EXP_DMAX)=0A= + =A0 =A0 =A0 =A0 =A0 =A0d.d =3D float64_infinity=3B=0A= + =A0 =A0}=0A= +=0A= + =A0 =A0d.bits.sign =3D flags.fmt.sign=3B=0A= +=0A= + =A0 =A0return float64_val(d.d)=3B=0A= +}=0A= +=0A= +static void ana_bits(float_status *fp_status=2C=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 float64 fsrca=2C float64 fsrcb=2C= TileGXFPDFmtF *dfmt)=0A= +{=0A= + =A0 =A0if (float64_eq(fsrca=2C fsrcb=2C fp_status)) {=0A= + =A0 =A0 =A0 =A0dfmt->fmt.eq =3D 1=3B=0A= + =A0 =A0} else {=0A= + =A0 =A0 =A0 =A0dfmt->fmt.neq =3D 1=3B=0A= + =A0 =A0}=0A= +=0A= + =A0 =A0if (float64_lt(fsrca=2C fsrcb=2C fp_status)) {=0A= + =A0 =A0 =A0 =A0dfmt->fmt.lt =3D 1=3B=0A= + =A0 =A0}=0A= + =A0 =A0if (float64_le(fsrca=2C fsrcb=2C fp_status)) {=0A= + =A0 =A0 =A0 =A0dfmt->fmt.le =3D 1=3B=0A= + =A0 =A0}=0A= +=0A= + =A0 =A0if (float64_lt(fsrcb=2C fsrca=2C fp_status)) {=0A= + =A0 =A0 =A0 =A0dfmt->fmt.gt =3D 1=3B=0A= + =A0 =A0}=0A= + =A0 =A0if (float64_le(fsrcb=2C fsrca=2C fp_status)) {=0A= + =A0 =A0 =A0 =A0dfmt->fmt.ge =3D 1=3B=0A= + =A0 =A0}=0A= +=0A= + =A0 =A0if (float64_unordered(fsrca=2C fsrcb=2C fp_status)) {=0A= + =A0 =A0 =A0 =A0dfmt->fmt.unordered =3D 1=3B=0A= + =A0 =A0}=0A= +}=0A= +=0A= +static uint64_t main_calc(float_status *fp_status=2C=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0float64 fsrca=2C float= 64 fsrcb=2C=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0float64 (*calc)(float6= 4=2C float64=2C float_status *))=0A= +{=0A= + =A0 =A0F64Fmt va=2C vb=2C vf=3B=0A= + =A0 =A0TileGXFPDFmtF flags=3B=0A= +=0A= + =A0 =A0flags.ll =3D 0=3B=0A= + =A0 =A0ana_bits(fp_status=2C fsrca=2C fsrcb=2C &flags)=3B=0A= +=0A= + =A0 =A0vf.d =3D calc(fsrca=2C fsrcb=2C fp_status)=3B /* also check except= ions */=0A= + =A0 =A0flags.fmt.sign =3D vf.bits.sign=3B=0A= +=0A= + =A0 =A0va.d =3D fsrca=3B=0A= + =A0 =A0vb.d =3D fsrcb=3B=0A= + =A0 =A0if (float64_is_any_nan(vf.d))=0A= + =A0 =A0 =A0 =A0flags.fmt.nan =3D 1=3B=0A= + =A0 =A0else if (float64_is_infinity(vf.d))=0A= + =A0 =A0 =A0 =A0flags.fmt.inf =3D 1=3B=0A= + =A0 =A0else if (calc =3D=3D float64_add) {=0A= + =A0 =A0 =A0 =A0flags.fmt.vexp =3D (va.bits.exp> vb.bits.exp)=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ? va.bits.exp : v= b.bits.exp=3B=0A= + =A0 =A0 =A0 =A0flags.fmt.calc =3D (va.bits.sign =3D=3D vb.bits.sign)=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ? TILEGX_F_CALC_A= DD : TILEGX_F_CALC_SUB=3B=0A= +=0A= + =A0 =A0} else if (calc =3D=3D float64_sub) {=0A= + =A0 =A0 =A0 =A0flags.fmt.vexp =3D (va.bits.exp> vb.bits.exp)=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ? va.bits.exp : v= b.bits.exp=3B=0A= + =A0 =A0 =A0 =A0flags.fmt.calc =3D (va.bits.sign !=3D vb.bits.sign)=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ? TILEGX_F_CALC_A= DD : TILEGX_F_CALC_SUB=3B=0A= +=0A= + =A0 =A0} else {=0A= + =A0 =A0 =A0 =A0flags.fmt.vexp =3D (int64_t)(va.bits.exp - TILEGX_F_EXP_DZ= ERO)=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 + (in= t64_t)(vb.bits.exp - TILEGX_F_EXP_DZERO)=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 + TIL= EGX_F_EXP_DZERO=3B=0A= + =A0 =A0 =A0 =A0flags.fmt.calc =3D TILEGX_F_CALC_MUL=3B=0A= + =A0 =A0}=0A= +=0A= + =A0 =A0return flags.ll=3B=0A= +}=0A= +=0A= +uint64_t helper_fdouble_add_flags(CPUTLGState *env=2C=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0uint64= _t srca=2C uint64_t srcb)=0A= +{=0A= + =A0 =A0return main_calc(&env->fp_status=2C=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 make_float64(srca)=2C make_float6= 4(srcb)=2C float64_add)=3B=0A= +}=0A= +=0A= +uint64_t helper_fdouble_sub_flags(CPUTLGState *env=2C=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0uint64= _t srca=2C uint64_t srcb)=0A= +{=0A= + =A0 =A0return main_calc(&env->fp_status=2C=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 make_float64(srca)=2C make_float6= 4(srcb)=2C float64_sub)=3B=0A= +}=0A= +=0A= +uint64_t helper_fdouble_mul_flags(CPUTLGState *env=2C=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0uint64= _t srca=2C uint64_t srcb)=0A= +{=0A= + =A0 =A0return main_calc(&env->fp_status=2C=0A= + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 make_float64(srca)=2C make_float6= 4(srcb)=2C float64_mul)=3B=0A= +}=0A= --=A0=0A= 1.9.3=0A= =0A= = --_9d578a43-f8ff-4f18-90d5-7665caefb7c6_ Content-Type: application/octet-stream Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="0003-target-tilegx-Implement-fpu-fdouble-floating-point-i.patch" RnJvbSBjNDY3ZGIxYzBhNWY0YzY1NjBiOGJkZGRkMjExNTczMmFhNzE4YzRiIE1vbiBTZXAgMTcg MDA6MDA6MDAgMjAwMQpGcm9tOiBDaGVuIEdhbmcgPGdhbmcuY2hlbi41aTVqQGdtYWlsLmNvbT4K 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