From: Luis Fernando Fujita Pires <luis.pires@eldorado.org.br>
To: Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "f4bug@amsat.org" <f4bug@amsat.org>,
"qemu-ppc@nongnu.org" <qemu-ppc@nongnu.org>,
"lagarcia@br.ibm.com" <lagarcia@br.ibm.com>,
Bruno Piazera Larsen <bruno.larsen@eldorado.org.br>,
Matheus Kowalczuk Ferst <matheus.ferst@eldorado.org.br>,
"david@gibson.dropbear.id.au" <david@gibson.dropbear.id.au>
Subject: RE: [PATCH v3 25/30] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI
Date: Fri, 30 Apr 2021 11:23:29 +0000 [thread overview]
Message-ID: <CP2PR80MB3668052FF0C559D6D092B0C7DA5E9@CP2PR80MB3668.lamprd80.prod.outlook.com> (raw)
In-Reply-To: <20210430011543.1017113-26-richard.henderson@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
> +&D rt ra si
> +@D ...... rt:5 ra:5 si:s16 &D
> +
> +# If a prefix is allowed, decode with default values.
> +&PLS_D rt ra si:int64_t r:bool
> +@PLS_D ...... rt:5 ra:5 si:s16 &PLS_D r=0
> +
> +### Fixed-Point Arithmetic Instructions
> +
> +ADDI 001110 ..... ..... ................ @PLS_D
> +ADDIS 001111 ..... ..... ................ @D
> diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index
> 9fc45d0614..f4272df724 100644
> --- a/target/ppc/insn64.decode
> +++ b/target/ppc/insn64.decode
> @@ -16,3 +16,18 @@
> # You should have received a copy of the GNU Lesser General Public # License
> along with this library; if not, see <http://www.gnu.org/licenses/>.
> #
> +
> +# Many all of these instruction names would be prefixed by "P", # but
> +we share code with the non-prefixed instruction.
> +
> +# Format MLS:D and 8LS:D
> +&PLS_D rt ra si:int64_t r:bool !extern
> +%pls_si 32:s18 0:16
> +@PLS_D ...... .. ... r:1 .. .................. \
> + ...... rt:5 ra:5 ................ \
> + &PLS_D si=%pls_si
> +
> +### Fixed-Point Arithmetic Instructions
> +
> +ADDI 000001 10 0--.-- .................. \
> + 001110 ..... ..... ................ @PLS_D
I think we should reconsider using the same .decode file for both 32- and 64-bit instructions, to avoid duplicating argument set definitions, and to keep the prefixed instructions close to their non-prefixed counterparts. For ADDI/PADDI, something along the lines of:
&PLS_D rt ra si:int64_t r:bool
%pls_si 32:s18 0:16
@PLS_D ...... .. ... r:1 .. .................. \
...... rt:5 ra:5 ................ \
&PLS_D si=%pls_si
@PLS_D_32 ...... rt:5 ra:5 si:s16 &PLS_D r=0
PADDI 000001 10 0--.-- .................. \
001110 ..... ..... ................ @PLS_D
ADDI 001110 ..... ..... ................ @PLS_D_32
ADDIS 001111 ..... ..... ................ @D
That's where I was going with the original patch, using the varinsnwidth support from decodetree.py.
And, in order to share the trans_PADDI/ADDI implementation, maybe add something to decodetree.py to allow us to specify that an instruction shares the trans_XX() implementation from another one, such as:
ADDI 001110 ..... ..... ................ @PLS_D_32 !impl=PADDI
This way, we could (and would need to, in fact) keep the 'P' in the prefixed instruction names, but at the same time avoid having extra trans_XX functions just calling another one without any additional code.
For the load functions, we would then have:
%ds_si 2:s14 !function=times_4
@PLS_DS_32 ...... rt:5 ra:5 .............. .. &PLS_D si=%ds_si r=0
&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
PLBZ 000001 10 0--.-- .................. \
100010 ..... ..... ................ @PLS_D
LBZ 100010 ..... ..... ................ @PLS_D_32 !impl=PLBZ
LBZU 100011 ..... ..... ................ @PLS_D_32
LBZX 011111 ..... ..... ..... 0001010111 - @X
LBZUX 011111 ..... ..... ..... 0001110111 - @X
PLHZ 000001 10 0--.-- .................. \
101000 ..... ..... ................ @PLS_D
LHZ 101000 ..... ..... ................ @PLS_D_32 !impl=PLHZ
LHZU 101001 ..... ..... ................ @PLS_D_32
LHZX 011111 ..... ..... ..... 0100010111 - @X
LHZUX 011111 ..... ..... ..... 0100110111 - @X
PLHA 000001 10 0--.-- .................. \
101010 ..... ..... ................ @PLS_D
LHA 101010 ..... ..... ................ @PLS_D_32 !impl=PLHA
LHAU 101011 ..... ..... ................ @PLS_D_32
LHAX 011111 ..... ..... ..... 0101010111 - @X
LHAXU 011111 ..... ..... ..... 0101110111 - @X
PLWZ 000001 10 0--.-- .................. \
100000 ..... ..... ................ @PLS_D
LWZ 100000 ..... ..... ................ @PLS_D_32 !impl=PLWZ
LWZU 100001 ..... ..... ................ @PLS_D_32
LWZX 011111 ..... ..... ..... 0000010111 - @X
LWZUX 011111 ..... ..... ..... 0000110111 - @X
PLWA 000001 00 0--.-- .................. \
101001 ..... ..... ................ @PLS_D
LWA 111010 ..... ..... ..............10 @PLS_DS_32 !impl=PLWA
LWAX 011111 ..... ..... ..... 0101010101 - @X
LWAUX 011111 ..... ..... ..... 0101110101 - @X
PLD 000001 00 0--.-- .................. \
111001 ..... ..... ................ @PLS_D
LD 111010 ..... ..... ..............00 @PLS_DS_32 !impl=PLD
LDU 111010 ..... ..... ..............01 @PLS_DS_32
LDX 011111 ..... ..... ..... 0000010101 - @X
LDUX 011111 ..... ..... ..... 0000110101 - @X
--
Luis
next prev parent reply other threads:[~2021-04-30 12:28 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-30 1:15 [PATCH v3 00/30] Base for adding PowerPC 64-bit instructions Richard Henderson
2021-04-30 1:15 ` [PATCH v3 01/30] decodetree: Introduce whex and whexC helpers Richard Henderson
2021-04-30 13:01 ` Luis Fernando Fujita Pires
2021-05-03 22:32 ` Philippe Mathieu-Daudé
2021-04-30 1:15 ` [PATCH v3 02/30] decodetree: More use of f-strings Richard Henderson
2021-04-30 13:01 ` Luis Fernando Fujita Pires
2021-05-03 22:33 ` Philippe Mathieu-Daudé
2021-04-30 1:15 ` [PATCH v3 03/30] decodetree: Add support for 64-bit instructions Richard Henderson
2021-04-30 13:03 ` Luis Fernando Fujita Pires
2021-04-30 1:15 ` [PATCH v3 04/30] decodetree: Extend argument set syntax to allow types Richard Henderson
2021-04-30 13:29 ` Luis Fernando Fujita Pires
2021-04-30 1:15 ` [PATCH v3 05/30] target/ppc: Add cia field to DisasContext Richard Henderson
2021-04-30 20:08 ` Bruno Piazera Larsen
2021-04-30 20:35 ` Luis Fernando Fujita Pires
2021-04-30 1:15 ` [PATCH v3 06/30] target/ppc: Split out decode_legacy Richard Henderson
2021-04-30 20:36 ` Luis Fernando Fujita Pires
2021-04-30 1:15 ` [PATCH v3 07/30] target/ppc: Move DISAS_NORETURN setting into gen_exception* Richard Henderson
2021-05-03 12:58 ` Luis Fernando Fujita Pires
2021-04-30 1:15 ` [PATCH v3 08/30] target/ppc: Remove special case for POWERPC_SYSCALL Richard Henderson
2021-05-03 12:59 ` Luis Fernando Fujita Pires
2021-04-30 1:15 ` [PATCH v3 09/30] target/ppc: Remove special case for POWERPC_EXCP_TRAP Richard Henderson
2021-05-03 13:00 ` Luis Fernando Fujita Pires
2021-04-30 1:15 ` [PATCH v3 10/30] target/ppc: Simplify gen_debug_exception Richard Henderson
2021-04-30 1:15 ` [PATCH v3 11/30] target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE} Richard Henderson
2021-04-30 1:15 ` [PATCH v3 12/30] target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT Richard Henderson
2021-04-30 1:15 ` [PATCH v3 13/30] target/ppc: Remove unnecessary gen_io_end calls Richard Henderson
2021-04-30 1:15 ` [PATCH v3 14/30] target/ppc: Introduce gen_icount_io_start Richard Henderson
2021-04-30 1:15 ` [PATCH v3 15/30] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE Richard Henderson
2021-04-30 1:15 ` [PATCH v3 16/30] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN Richard Henderson
2021-04-30 1:15 ` [PATCH v3 17/30] target/ppc: Remove DisasContext.exception Richard Henderson
2021-04-30 13:00 ` Matheus K. Ferst
2021-04-30 1:15 ` [PATCH v3 18/30] target/ppc: Move single-step check to ppc_tr_tb_stop Richard Henderson
2021-04-30 1:15 ` [PATCH v3 19/30] target/ppc: Tidy exception vs exit_tb Richard Henderson
2021-04-30 1:15 ` [PATCH v3 20/30] target/ppc: Mark helper_raise_exception* as noreturn Richard Henderson
2021-05-03 22:36 ` Philippe Mathieu-Daudé
2021-04-30 1:15 ` [PATCH v3 21/30] target/ppc: Use translator_loop_temp_check Richard Henderson
2021-04-30 1:15 ` [PATCH v3 22/30] target/ppc: Introduce macros to check isa extensions Richard Henderson
2021-05-03 22:37 ` Philippe Mathieu-Daudé
2021-04-30 1:15 ` [PATCH v3 23/30] target/ppc: Add infrastructure for prefixed insns Richard Henderson
2021-04-30 1:15 ` [PATCH v3 24/30] target/ppc: Move page crossing check to ppc_tr_translate_insn Richard Henderson
2021-04-30 1:26 ` Richard Henderson
2021-04-30 1:15 ` [PATCH v3 25/30] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI Richard Henderson
2021-04-30 11:23 ` Luis Fernando Fujita Pires [this message]
2021-04-30 14:23 ` Richard Henderson
2021-04-30 18:45 ` Luis Fernando Fujita Pires
2021-04-30 19:11 ` Richard Henderson
2021-04-30 20:32 ` Luis Fernando Fujita Pires
2021-04-30 22:29 ` Richard Henderson
2021-04-30 14:05 ` Matheus K. Ferst
2021-04-30 14:31 ` Richard Henderson
2021-04-30 18:02 ` Matheus K. Ferst
2021-04-30 18:43 ` Richard Henderson
2021-04-30 23:29 ` Matheus K. Ferst
2021-04-30 1:15 ` [PATCH v3 26/30] target/ppc: Implement PNOP Richard Henderson
2021-05-03 22:41 ` Philippe Mathieu-Daudé
2021-04-30 1:15 ` [PATCH v3 27/30] target/ppc: Move D/DS/X-form integer loads to decodetree Richard Henderson
2021-04-30 23:54 ` Matheus K. Ferst
2021-05-01 0:50 ` Richard Henderson
2021-05-03 12:28 ` Matheus K. Ferst
2021-04-30 1:15 ` [PATCH v3 28/30] target/ppc: Implement prefixed integer load instructions Richard Henderson
2021-04-30 1:15 ` [PATCH v3 29/30] target/ppc: Move D/DS/X-form integer stores to decodetree Richard Henderson
2021-04-30 1:15 ` [PATCH v3 30/30] target/ppc: Implement prefixed integer store instructions Richard Henderson
2021-04-30 1:48 ` [PATCH v3 00/30] Base for adding PowerPC 64-bit instructions no-reply
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