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charset=UTF-8 Date: Mon, 15 May 2023 18:26:00 +1000 Message-Id: Cc: , Subject: Re: [PATCH 6/6] target/ppc: Implement HEIR SPR From: "Nicholas Piggin" To: "Harsh Prateek Bora" X-Mailer: aerc 0.14.0 References: <20230323022237.1807512-1-npiggin@gmail.com> <20230323022237.1807512-6-npiggin@gmail.com> In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=npiggin@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue May 9, 2023 at 7:51 PM AEST, Harsh Prateek Bora wrote: > On Thu, Mar 23, 2023 at 12:22:37PM +1000, Nicholas Piggin wrote: > > The hypervisor emulation assistance interrupt modifies HEIR to > > contain the value of the instruction which caused the exception. > >=20 > > Signed-off-by: Nicholas Piggin > > --- > > target/ppc/cpu.h | 1 + > > target/ppc/cpu_init.c | 23 +++++++++++++++++++++++ > > target/ppc/excp_helper.c | 12 +++++++++++- > > 3 files changed, 35 insertions(+), 1 deletion(-) > >=20 > > > > > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > > index 2e0321ab69..d206903562 100644 > > --- a/target/ppc/excp_helper.c > > +++ b/target/ppc/excp_helper.c > > @@ -1614,13 +1614,23 @@ static void powerpc_excp_books(PowerPCCPU *cpu,= int excp) > > case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception = */ > > case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception = */ > > case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt = */ > > - case POWERPC_EXCP_HV_EMU: > > case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization = */ > > srr0 =3D SPR_HSRR0; > > srr1 =3D SPR_HSRR1; > > new_msr |=3D (target_ulong)MSR_HVB; > > new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); > > break; > > + case POWERPC_EXCP_HV_EMU: > > + env->spr[SPR_HEIR] =3D insn; > > + if (is_prefix_excp(env, insn)) { > > + uint32_t insn2 =3D ppc_ldl_code(env, env->nip + 4); > > + env->spr[SPR_HEIR] |=3D (uint64_t)insn2 << 32; > > + } > > + srr0 =3D SPR_HSRR0; > > + srr1 =3D SPR_HSRR1; > > + new_msr |=3D (target_ulong)MSR_HVB; > > + new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); > > + break; > > Since there is a common code, this could be better written like: > case POWERPC_EXCP_HV_EMU: > env->spr[SPR_HEIR] =3D insn; > if (is_prefix_excp(env, insn)) { > uint32_t insn2 =3D ppc_ldl_code(env, env->nip + 4); > env->spr[SPR_HEIR] |=3D (uint64_t)insn2 << 32; > } > /* fall through below common code for EXCP_HVIRT */ > case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization = */ > srr0 =3D SPR_HSRR0; > srr1 =3D SPR_HSRR1; > new_msr |=3D (target_ulong)MSR_HVB; > new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); > break; That would be wrong for the other HSRR fallthroughs above it. Thanks, Nick