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[14.203.144.223]) by smtp.gmail.com with ESMTPSA id p14-20020a170902e74e00b001b39e866324sm9056875plf.306.2023.06.14.19.18.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Jun 2023 19:18:18 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 15 Jun 2023 12:18:13 +1000 Message-Id: Subject: Re: [PATCH 0/4] ppc/pnv: Add chiptod and core timebase state machine models From: "Nicholas Piggin" To: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Cc: , "Daniel Henrique Barboza" , "Frederic Barrat" , "Michael Neuling" X-Mailer: aerc 0.14.0 References: <20230603233612.125879-1-npiggin@gmail.com> In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed Jun 14, 2023 at 6:54 PM AEST, C=C3=A9dric Le Goater wrote: > On 6/14/23 07:14, Nicholas Piggin wrote: > > On Tue Jun 6, 2023 at 11:59 PM AEST, C=C3=A9dric Le Goater wrote: > >> On 6/4/23 01:36, Nicholas Piggin wrote: > >>> This adds support for chiptod and core timebase state machine models = in > >>> the powernv POWER9 and POWER10 models. > >>> > >>> This does not actually change the time or the value in TB registers > >>> (because they are alrady synced in QEMU), but it does go through the > >>> motions. It is enough to be able to run skiboot's chiptod initialisat= ion > >>> code that synchronises core timebases (after a patch to prevent skibo= ot > >>> skipping chiptod for QEMU, posted to skiboot mailing list). > >>> > >>> Sorry there was some delay since the last posting. There is a bit mor= e > >>> interest in this recently but feedback and comments from RFC was not > >>> forgotten and is much appreciated. > >>> > >>> https://lists.gnu.org/archive/html/qemu-ppc/2022-08/msg00324.html > >>> > >>> I think I accounted for everything except moving register defines to = the > >>> .h file. I'm on the fence about that but if they are only used in the= .c > >>> file I think it's okay to keep them there for now. I cut out a lot of > >>> unused ones so it's not so cluttered now. > >>> > >>> Lots of other changes and fixes since that RFC. Notably: > >>> - Register names changed to match the workbook names instead of skibo= ot. > >>> - TFMR moved to timebase_helper.c from misc_helper.c > >>> - More comprehensive model and error checking, particularly of TFMR. > >>> - POWER10 with multi-chip support. > >>> - chiptod and core timebase linked via specific state instead of TFMR= . > >> > >> > >> The chiptod units are not exposed to the OS, it is all handled at FW > >> level AFAIK. Could the OPAL people provide some feedback on the low le= vel > >> models ? > >=20 > > Well, no takers so far. I guess I'm a OPAL people :) > >> I did some of the P10 chiptod addressing in skiboot, at least. This > > patch does work with the skiboot chiptod driver at least. > > cool, with 2 chips ? Yes it worked with 2 chips. > > I would eventually like to add in the ability to actually change the > > TB with it, and inject errors and generate HMIs because that's an area > > that seem to be a bit lacking (most of such testing seemed to be done > > on real hardware using special time facility corruption injection). > > The MCE injection was a nice addon > > https://lore.kernel.org/qemu-devel/20200325144147.221875-1-npiggin@gma= il.com/ > https://lore.kernel.org/qemu-devel/20211013214042.618918-1-clg@kaod.or= g/ > > I hope it will get more attention if you resend. Will take another look. > > But yes for now it is a bit difficult to verify it does much useful > > aside from booting skiboot (+ patch to enable chiptod on QEMU I posted > > recently). > > It's difficult to review PATCH 4 without some good knowledge of HW. I kno= w > you do but you can not review your own patches ! That said, the impact is > limited to PowerNV machines, I guess we are fine. Yeah. I appreciate all the review so far. It's pretty complicated even with the workbook. I might be able to add a simpler and higher-level description of the basic init sequence and states. You would still have to trust me, but it might make it easier to see what's going on. Thanks, Nick