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[14.203.144.223]) by smtp.gmail.com with ESMTPSA id g17-20020a631111000000b0054ff36967f7sm376546pgl.54.2023.06.14.19.51.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Jun 2023 19:51:22 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 15 Jun 2023 12:51:17 +1000 Message-Id: Cc: , "Daniel Henrique Barboza" , Subject: Re: [PATCH v4 1/6] target/ppc: Fix instruction loading endianness in alignment interrupt From: "Nicholas Piggin" To: "Anushree Mathur" , X-Mailer: aerc 0.14.0 References: <20230530132543.385138-2-npiggin@gmail.com> <0bbbffa7-d66c-66f2-f660-321e4f8aa026@linux.vnet.ibm.com> In-Reply-To: <0bbbffa7-d66c-66f2-f660-321e4f8aa026@linux.vnet.ibm.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::72f; envelope-from=npiggin@gmail.com; helo=mail-qk1-x72f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed Jun 14, 2023 at 3:51 PM AEST, Anushree Mathur wrote: > > On 5/30/23 18:55, Nicholas Piggin wrote: > > powerpc ifetch endianness depends on MSR[LE] so it has to byteswap > > after cpu_ldl_code(). This corrects DSISR bits in alignment > > interrupts when running in little endian mode. > > > > Reviewed-by: Fabiano Rosas > > Signed-off-by: Nicholas Piggin > > --- > > target/ppc/excp_helper.c | 22 +++++++++++++++++++++- > > 1 file changed, 21 insertions(+), 1 deletion(-) > > > > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > > index c13f2afa04..0274617b4a 100644 > > --- a/target/ppc/excp_helper.c > > +++ b/target/ppc/excp_helper.c > > @@ -133,6 +133,26 @@ static void dump_hcall(CPUPPCState *env) > > env->nip); > > } > > =20 > > +#ifdef CONFIG_TCG > > +/* Return true iff byteswap is needed in a scalar memop */ > > +static inline bool need_byteswap(CPUArchState *env) > > +{ > > + /* SOFTMMU builds TARGET_BIG_ENDIAN. Need to swap when MSR[LE] is = set */ > > + return !!(env->msr & ((target_ulong)1 << MSR_LE)); > > +} > > + > > +static uint32_t ppc_ldl_code(CPUArchState *env, abi_ptr addr) > > This hunk fails to compile with configure --disable-tcg I don't see how since it's inside CONFIG_TCG. Seems to work here. You don't have an old version of the patch applied? What configure options exactly? Thanks, Nick