From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
	id S1752963AbbDGGo5 (ORCPT <rfc822;w@1wt.eu>);
	Tue, 7 Apr 2015 02:44:57 -0400
Received: from mail-by2on0121.outbound.protection.outlook.com ([207.46.100.121]:42604
	"EHLO na01-by2-obe.outbound.protection.outlook.com"
	rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP
	id S1750940AbbDGGox (ORCPT <rfc822;linux-kernel@vger.kernel.org>);
	Tue, 7 Apr 2015 02:44:53 -0400
From: "Jianwei.Wang@freescale.com" <Jianwei.Wang@freescale.com>
To: Stefan Agner <stefan@agner.ch>
CC: Scott Wood <scottwood@freescale.com>,
        "airlied@linux.ie" <airlied@linux.ie>,
        "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        Xiubo Li <lixiubo@cmss.chinamobile.com>,
        "Huan Wang" <alison.wang@freescale.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "Jason.Jin@freescale.com" <Jason.Jin@freescale.com>,
        "linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>
Subject: RE: [PATCH v3 1/4] drm/layerscape: Add Freescale DCU DRM driver
Thread-Topic: [PATCH v3 1/4] drm/layerscape: Add Freescale DCU DRM driver
Thread-Index: AQHQZ4dhLlMGc0aId0KmAuRhdwc1jp02UCUAgAqHxpA=
Date: Tue, 7 Apr 2015 06:44:47 +0000
Message-ID: <CY1PR0301MB12268B3F7505EFB85D874B499FFD0@CY1PR0301MB1226.namprd03.prod.outlook.com>
References: <1427348225-40731-1-git-send-email-b52261@freescale.com>
 <a248211878c93298700ca1e39ab1812b@agner.ch>
In-Reply-To: <a248211878c93298700ca1e39ab1812b@agner.ch>
Accept-Language: zh-CN, en-US
Content-Language: en-US
X-MS-Has-Attach: 
X-MS-TNEF-Correlator: 
x-originating-ip: [192.158.241.86]
authentication-results: agner.ch; dkim=none (message not signed)
 header.d=none;
x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR0301MB0874;
x-forefront-antispam-report: BMV:1;SFV:NSPM;SFS:(10019020)(6009001)(377424004)(24454002)(51704005)(76104003)(52034003)(106116001)(66066001)(5890100001)(19580405001)(19580395003)(33656002)(87936001)(2656002)(110136001)(76576001)(86362001)(575784001)(46102003)(99286002)(50986999)(54356999)(76176999)(74316001)(122556002)(2950100001)(92566002)(77156002)(62966003)(102836002)(2900100001)(217873001)(579004)(559001);DIR:OUT;SFP:1102;SCL:1;SRVR:CY1PR0301MB0874;H:CY1PR0301MB1226.namprd03.prod.outlook.com;FPR:;SPF:None;MLV:sfv;LANG:en;
x-microsoft-antispam-prvs: <CY1PR0301MB087417664C854F45427598879FFD0@CY1PR0301MB0874.namprd03.prod.outlook.com>
x-exchange-antispam-report-test: UriScan:;
x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(601004)(5002010)(5005006);SRVR:CY1PR0301MB0874;BCL:0;PCL:0;RULEID:;SRVR:CY1PR0301MB0874;
x-forefront-prvs: 0539EEBD11
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
X-OriginatorOrg: freescale.com
X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Apr 2015 06:44:48.0381
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 710a03f5-10f6-4d38-9ff4-a80b81da590d
X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0301MB0874
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
Content-Transfer-Encoding: 8bit
X-MIME-Autoconverted: from base64 to 8bit by nfs id t376j831028889

Hi Stefan,

Thank you for your review and testing on Vybrid F610 device. This driver 
just implement the basic functions and it only support the exported 
framebuffer access. Some DRM interfaces are not implemented now. So your 
test result is normal. I will implement these interfaces with patches soon 
afterwards. I don't plan to add new features for the initial version driver,
otherwise it will be a long term for this version.

I tested on ls1021a using TFT panel, there are no flickers on the screen
when inserting a USB HID device. I will do more test if time permits.

By the way, could please give me some guidance on how X-Server use DRM 
Interface directly? Do you have some papers or webpage about this?

My reply below...

> 
> Hi Jianwei,
> 
> The driver worked on a Vybrid VF610 device using the exported
> framebuffer. However, when using X-Server through the DRM interface
> directly (by using the modesetting driver) I get just a black screen so
> far, still investigating the reason. What user-space interfaces did you
> test?
> 
> When using the FB device and insert a USB HID device, I get some
> flickers on the screen. I didn't had those on the dcufb driver, did you
> notice something like this too? Probably related to the resolution, I'm
> using VGA resolution.
> 
> Some comments below.
> 
> 
> On 2015-03-26 06:37, Jianwei Wang wrote:
> > This patch add support for Two Dimensional Animation and Compositing
> > Engine (2D-ACE) on the Freescale SoCs.
> >
> > 2D-ACE is a Freescale display controller. 2D-ACE describes
> > the functionality of the module extremely well its name is a value
> > that cannot be used as a token in programming languages.
> > Instead the valid token "DCU" is used to tag the register names and
> > function names.
> >
> > The Display Controller Unit (DCU) module is a system master that
> > fetches graphics stored in internal or external memory and displays
> > them on a TFT LCD panel. A wide range of panel sizes is supported
> > and the timing of the interface signals is highly configurable.
> > Graphics are read directly from memory and then blended in real-time,
> > which allows for dynamic content creation with minimal CPU
> > intervention.
> >
> > The features:
> > (1) Full RGB888 output to TFT LCD panel.
> > (2) For the current LCD panel, WQVGA "480x272" is supported.
> > (3) Blending of each pixel using up to 4 source layers
> > dependent on size of panel.
> 
> modetest only shows one layer currently...

Yes, only one plane and one framebuffer were created now, others
maybe create as user requirement or create all when initializing,
I'm not sure now. This describe the hardware feature

> 
> > (4) Each graphic layer can be placed with one pixel resolution
> > in either axis.
> > (5) Each graphic layer support RGB565 and RGB888 direct colors
> > without alpha channel
> > and BGRA8888 direct colors with an alpha channel.
> 
> The array fsl_dcu_drm_plane_formats below shows more formats, does this
> commit log needs updating?
> 

I agree with your suggestion, I will update this commit log

> > (6) Each graphic layer support alpha blending with 8-bit
> > resolution.
> >
> > This is a simplified version, only one primary plane, one
> > framebuffer created for fbdev, one crtc, one connector for
> > TFT LCD panel, an encoder.
> >
> > Signed-off-by: Alison Wang <b18965@freescale.com>
> > Signed-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com>
> > Signed-off-by: Jianwei Wang <b52261@freescale.com>
> > ---
> >
> > Changed in V3:
> >
> > - Test driver on Vybrid board and add compatible string
> > - Remove unused functions
> > - set default crtc for encoder
> > - replace legacy functions with atomic help functions
> > - Set the unique name of the DRM device
> > - Implement irq handle function for vblank interrupt
> >
> > Changed in v2:
> > - Add atomic support
> > - Modify bindings file
> > - Rename node for compatibility
> > - Move platform related code out for compatibility
> >
> >  .../devicetree/bindings/drm/fsl/fsl,dcu.txt        |  50 ++++
> >  drivers/gpu/drm/Kconfig                            |   2 +
> >  drivers/gpu/drm/Makefile                           |   1 +
> >  drivers/gpu/drm/fsl/Kconfig                        |  17 ++
> >  drivers/gpu/drm/fsl/Makefile                       |   8 +
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_connector.c        | 193 ++++++++++++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_connector.h        |  30 ++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.c             | 165 ++++++++++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.h             |  26 ++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c              | 331
> +++++++++++++++++++++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_drv.h              | 210 +++++++++++++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_fbdev.c            |  26 ++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_kms.c              |  42 +++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_kms.h              |  17 ++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_plane.c            | 192 ++++++++++++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_plane.h            |  23 ++
> >  16 files changed, 1333 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/drm/fsl/fsl,dcu.txt
> >  create mode 100644 drivers/gpu/drm/fsl/Kconfig
> >  create mode 100644 drivers/gpu/drm/fsl/Makefile
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_connector.c
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_connector.h
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.c
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.h
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_drv.h
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_fbdev.c
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_kms.c
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_kms.h
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_plane.c
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_plane.h
> >
> > diff --git a/Documentation/devicetree/bindings/drm/fsl/fsl,dcu.txt
> > b/Documentation/devicetree/bindings/drm/fsl/fsl,dcu.txt
> > new file mode 100644
> > index 0000000..bdc7d5b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/drm/fsl/fsl,dcu.txt
> > @@ -0,0 +1,50 @@
> > +Device Tree bindings for Freescale DCU DRM Driver
> > +
> > +Required properties:
> > +- compatible:           Should be one of
> > +	* "fsl,ls1021a-dcu".
> > +	* "fsl,vf610-dcu".
> 
> In the Vybrid reference manual, that IP is denoted as "DCU4". Any reason
> why you left out the DCU version? Is this different for LS1021a? On the
> other hand, with the SoC in the name, the IP should be specified clear
> enough.
> 

In the LS1021A reference manual, no DCU version related words. I asked
previous DCU owner, she told me that LS1021A use DCU5 and she also point
out that the same DCU version there may be differences between different 
SoCs. So I named compatible string with SoC name.

> > +- reg:                  Address and length of the register set for dcu.
> > +- clocks:               From common clock binding: handle to dcu clock.
> > +- clock-names:          From common clock binding: Shall be "dcu".
> > +- display:              The phandle to display node.
> > +
> > +Required properties:
> > +- bits-per-pixel:       <16> for RGB565,
> > +			<24> for RGB888,
> > +			<32> for RGB8888.
> > +
> > +Required timing node for dispplay sub-node:
> > +- display-timings:      Refer to binding doc display-timing.txt for
> details.
> > +
> > +Examples:
> > +dcu: dcu@2ce0000 {
> > +	compatible = "fsl,ls1021a-dcu";
> > +	reg = <0x0 0x2ce0000 0x0 0x10000>;
> > +	clocks = <&platform_clk 0>;
> > +	clock-names = "dcu";
> > +	big-endian;
> > +	display = <&display>;
> > +
> > +	display: display@0 {
> > +		bits-per-pixel = <24>;
> > +
> > +		display-timings {
> > +			native-mode = <&timing0>;
> > +			timing0: nl4827hc19 {
> > +				clock-frequency = <10870000>;
> > +				hactive = <480>;
> > +				vactive = <272>;
> > +				hback-porch = <2>;
> > +				hfront-porch = <2>;
> > +				vback-porch = <1>;
> > +				vfront-porch = <1>;
> > +				hsync-len = <41>;
> > +				vsync-len = <2>;
> > +				hsync-active = <1>;
> > +				vsync-active = <1>;
> > +			};
> > +		};
> > +	};
> > +};
> > +
> > diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
> > index 151a050..a6957aa 100644
> > --- a/drivers/gpu/drm/Kconfig
> > +++ b/drivers/gpu/drm/Kconfig
> > @@ -199,6 +199,8 @@ source "drivers/gpu/drm/bochs/Kconfig"
> >
> >  source "drivers/gpu/drm/msm/Kconfig"
> >
> > +source "drivers/gpu/drm/fsl/Kconfig"
> > +
> >  source "drivers/gpu/drm/tegra/Kconfig"
> >
> >  source "drivers/gpu/drm/panel/Kconfig"
> > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> > index 2c239b9..ab5b9ef 100644
> > --- a/drivers/gpu/drm/Makefile
> > +++ b/drivers/gpu/drm/Makefile
> > @@ -56,6 +56,7 @@ obj-$(CONFIG_DRM_UDL) += udl/
> >  obj-$(CONFIG_DRM_AST) += ast/
> >  obj-$(CONFIG_DRM_ARMADA) += armada/
> >  obj-$(CONFIG_DRM_ATMEL_HLCDC)	+= atmel-hlcdc/
> > +obj-$(CONFIG_DRM_FSL_DCU) += fsl/
> 
> Hm, I'm wondering whether it would be a good idea to store that driver
> under fsl-dcu/... Any opinion?
> 

I think it is good advice, I'll think about this

> >  obj-$(CONFIG_DRM_RCAR_DU) += rcar-du/
> >  obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
> >  obj-$(CONFIG_DRM_OMAP)	+= omapdrm/
> > diff --git a/drivers/gpu/drm/fsl/Kconfig b/drivers/gpu/drm/fsl/Kconfig
> > new file mode 100644
> > index 0000000..e4f8df0
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/Kconfig
> > @@ -0,0 +1,17 @@
> > +config DRM_FSL_DCU
> > +	tristate "DRM Support for Freescale DCU"
> > +	depends on DRM && OF && ARM
> > +	select DRM_KMS_HELPER
> > +	select DRM_KMS_CMA_HELPER
> > +	select VIDEOMODE_HELPERS
> > +	select BACKLIGHT_CLASS_DEVICE
> > +	select BACKLIGHT_LCD_SUPPORT
> > +	select REGMAP_MMIO
> > +	select DRM_KMS_FB_HELPER
> > +	select FB_SYS_FILLRECT
> > +	select FB_SYS_COPYAREA
> > +	select FB_SYS_IMAGEBLIT
> > +	select FB_SYS_FOPS
> > +	help
> > +	  Choose this option if you have an Freescale DCU chipset.
> > +	  If M is selected the module will be called fsl-dcu-drm.
> > diff --git a/drivers/gpu/drm/fsl/Makefile b/drivers/gpu/drm/fsl/Makefile
> > new file mode 100644
> > index 0000000..5f74aee
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/Makefile
> > @@ -0,0 +1,8 @@
> > +fsl-dcu-drm-y := fsl_dcu_drm_drv.o \
> > +	       fsl_dcu_drm_kms.o \
> > +	       fsl_dcu_drm_connector.o \
> > +	       fsl_dcu_drm_plane.o \
> > +	       fsl_dcu_drm_crtc.o \
> > +	       fsl_dcu_drm_fbdev.o \
> > +
> > +obj-$(CONFIG_DRM_FSL_DCU)	+= fsl-dcu-drm.o
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_connector.c
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_connector.c
> > new file mode 100644
> > index 0000000..4610647
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_connector.c
> > @@ -0,0 +1,193 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#include <linux/backlight.h>
> > +
> > +#include <drm/drmP.h>
> > +#include <drm/drm_atomic_helper.h>
> > +#include <video/of_display_timing.h>
> > +
> > +#include "fsl_dcu_drm_drv.h"
> > +#include "fsl_dcu_drm_connector.h"
> > +
> > +static void fsl_dcu_drm_encoder_dpms(struct drm_encoder *encoder, int
> mode)
> > +{
> > +}
> > +
> > +static void fsl_dcu_drm_encoder_mode_prepare(struct drm_encoder
> *encoder)
> > +{
> > +}
> > +
> > +static void fsl_dcu_drm_encoder_mode_set(struct drm_encoder *encoder,
> > +					 struct drm_display_mode *mode,
> > +					 struct drm_display_mode *adjusted_mode)
> > +{
> > +}
> > +
> > +static void fsl_dcu_drm_encoder_mode_commit(struct drm_encoder *encoder)
> > +{
> > +}
> > +
> > +static void fsl_dcu_drm_encoder_disable(struct drm_encoder *encoder)
> > +{
> > +}
> > +
> > +static int
> > +fsl_dcu_drm_encoder_atomic_check(struct drm_encoder *encoder,
> > +				 struct drm_crtc_state *crtc_state,
> > +				 struct drm_connector_state *conn_state)
> > +{
> > +	return 0;
> > +}
> > +
> > +static void fsl_dcu_drm_encoder_destroy(struct drm_encoder *encoder)
> > +{
> > +	drm_encoder_cleanup(encoder);
> > +}
> > +
> > +static const struct drm_encoder_helper_funcs encoder_helper_funcs = {
> > +	.dpms = fsl_dcu_drm_encoder_dpms,
> > +	.prepare = fsl_dcu_drm_encoder_mode_prepare,
> > +	.commit = fsl_dcu_drm_encoder_mode_commit,
> > +	.mode_set = fsl_dcu_drm_encoder_mode_set,
> > +	.disable = fsl_dcu_drm_encoder_disable,
> > +	.atomic_check = fsl_dcu_drm_encoder_atomic_check,
> > +};
> > +
> > +static const struct drm_encoder_funcs encoder_funcs = {
> > +	.destroy = fsl_dcu_drm_encoder_destroy,
> > +};
> > +
> > +int fsl_dcu_drm_encoder_create(struct fsl_dcu_drm_device *fsl_dev,
> > +			       struct fsl_dcu_drm_crtc *crtc)
> > +{
> > +	struct drm_encoder *encoder = &fsl_dev->encoder;
> > +	int ret;
> > +
> > +	ret = drm_encoder_init(fsl_dev->ddev, encoder, &encoder_funcs,
> > +			       DRM_MODE_ENCODER_LVDS);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	drm_encoder_helper_add(encoder, &encoder_helper_funcs);
> > +	encoder->crtc = &crtc->crtc;
> > +
> > +	return 0;
> > +}
> > +
> > +#define to_fsl_dcu_connector(connector) \
> > +	container_of(connector, struct fsl_dcu_drm_connector, connector)
> > +
> > +static int fsl_dcu_drm_connector_get_modes(struct drm_connector
> *connector)
> > +{
> > +	struct drm_device *dev = connector->dev;
> > +	struct device_node *display_np, *np = dev->dev->of_node;
> > +	struct drm_display_mode *mode = drm_mode_create(connector->dev);
> > +	int num_modes = 0;
> > +
> > +	if (np) {
> > +		display_np = of_parse_phandle(np, "display", 0);
> > +		if (!display_np) {
> > +			dev_err(dev->dev, "failed to find display phandle\n");
> > +			return num_modes;
> > +		}
> > +		of_get_drm_display_mode(display_np, mode, OF_USE_NATIVE_MODE);
> > +		mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
> > +		drm_mode_probed_add(connector, mode);
> > +		num_modes++;
> > +	}
> > +
> > +	return num_modes;
> > +}
> > +
> > +static int fsl_dcu_drm_connector_mode_valid(struct drm_connector
> *connector,
> > +					    struct drm_display_mode *mode)
> > +{
> > +	return MODE_OK;
> > +}
> > +
> > +static struct drm_encoder *
> > +fsl_dcu_drm_connector_best_encoder(struct drm_connector *connector)
> > +{
> > +	struct fsl_dcu_drm_connector *fsl_con =
> to_fsl_dcu_connector(connector);
> > +
> > +	return fsl_con->encoder;
> > +}
> > +
> > +static void fsl_dcu_drm_connector_destroy(struct drm_connector
> *connector)
> > +{
> > +	drm_connector_unregister(connector);
> > +	drm_connector_cleanup(connector);
> > +}
> > +
> > +static enum drm_connector_status
> > +fsl_dcu_drm_connector_detect(struct drm_connector *connector, bool
> force)
> > +{
> > +	return connector_status_connected;
> > +}
> > +
> > +static const struct drm_connector_funcs fsl_dcu_drm_connector_funcs = {
> > +	.dpms = drm_atomic_helper_connector_dpms,
> > +	.reset = drm_atomic_helper_connector_reset,
> > +	.detect = fsl_dcu_drm_connector_detect,
> > +	.fill_modes = drm_helper_probe_single_connector_modes,
> > +	.destroy = fsl_dcu_drm_connector_destroy,
> > +	.atomic_duplicate_state =
> drm_atomic_helper_connector_duplicate_state,
> > +	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> > +};
> > +
> > +static const struct drm_connector_helper_funcs connector_helper_funcs =
> {
> > +	.get_modes = fsl_dcu_drm_connector_get_modes,
> > +	.mode_valid = fsl_dcu_drm_connector_mode_valid,
> > +	.best_encoder = fsl_dcu_drm_connector_best_encoder,
> > +};
> > +
> > +int fsl_dcu_drm_connector_create(struct fsl_dcu_drm_device *fsl_dev,
> > +				 struct drm_encoder *encoder)
> > +{
> > +	struct drm_connector *connector = &fsl_dev->connector.connector;
> > +	int ret;
> > +
> > +	fsl_dev->connector.encoder = encoder;
> > +
> > +	connector->display_info.width_mm = 0;
> > +	connector->display_info.height_mm = 0;
> > +
> > +	ret = drm_connector_init(fsl_dev->ddev, connector,
> > +				 &fsl_dcu_drm_connector_funcs,
> > +				 DRM_MODE_CONNECTOR_LVDS);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	connector->dpms = DRM_MODE_DPMS_OFF;
> > +	drm_connector_helper_add(connector, &connector_helper_funcs);
> > +	ret = drm_connector_register(connector);
> > +	if (ret < 0)
> > +		goto err_cleanup;
> > +
> > +	ret = drm_mode_connector_attach_encoder(connector, encoder);
> > +	if (ret < 0)
> > +		goto err_sysfs;
> > +
> > +	connector->encoder = encoder;
> > +
> > +	drm_object_property_set_value
> > +		(&connector->base, fsl_dev->ddev->mode_config.dpms_property,
> > +		DRM_MODE_DPMS_OFF);
> > +
> > +	return 0;
> > +
> > +err_sysfs:
> > +	drm_connector_unregister(connector);
> > +err_cleanup:
> > +	drm_connector_cleanup(connector);
> > +	return ret;
> > +}
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_connector.h
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_connector.h
> > new file mode 100644
> > index 0000000..bbf6d38
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_connector.h
> > @@ -0,0 +1,30 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#ifndef __FSL_DCU_DRM_CONNECTOR_H__
> > +#define __FSL_DCU_DRM_CONNECTOR_H__
> > +
> > +#include <drm/drmP.h>
> > +#include <drm/drm_crtc.h>
> > +#include "fsl_dcu_drm_crtc.h"
> > +
> > +struct fsl_dcu_drm_device;
> > +struct fsl_dcu_drm_connector {
> > +	struct drm_connector connector;
> > +	struct drm_encoder *encoder;
> > +};
> > +
> > +int fsl_dcu_drm_encoder_create(struct fsl_dcu_drm_device *fsl_dev,
> > +			       struct fsl_dcu_drm_crtc *crtc);
> > +int fsl_dcu_drm_connector_create(struct fsl_dcu_drm_device *fsl_dev,
> > +				 struct drm_encoder *encoder);
> > +
> > +#endif /* __FSL_DCU_DRM_CONNECTOR_H__ */
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.c
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.c
> > new file mode 100644
> > index 0000000..076e273
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.c
> > @@ -0,0 +1,165 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#include <linux/regmap.h>
> > +#include <linux/clk.h>
> > +
> > +#include <drm/drmP.h>
> > +#include <drm/drm_atomic.h>
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_crtc.h>
> > +
> > +#include "fsl_dcu_drm_crtc.h"
> > +#include "fsl_dcu_drm_drv.h"
> > +#include "fsl_dcu_drm_plane.h"
> > +
> > +#define to_fsl_dcu_crtc(c)	container_of(c, struct fsl_dcu_drm_crtc,
> crtc)
> > +
> > +void fsl_dcu_drm_crtc_suspend(struct drm_crtc *crtc)
> > +{
> > +}
> > +
> > +static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
> > +{
> > +	struct drm_device *dev = crtc->dev;
> > +	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
> > +	struct drm_display_mode *mode = &crtc->state->mode;
> > +	uint32_t hbp, hfp, hsw, vbp, vfp, vsw, div, index;
> > +
> > +	DBG(": set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
> > +	    mode->base.id, mode->name,
> > +	    mode->vrefresh, mode->clock,
> > +	    mode->hdisplay, mode->hsync_start,
> > +	    mode->hsync_end, mode->htotal,
> > +	    mode->vdisplay, mode->vsync_start,
> > +	    mode->vsync_end, mode->vtotal,
> > +	    mode->type, mode->flags);
> > +
> > +	index = drm_crtc_index(crtc);
> > +	div = (uint32_t)clk_get_rate(fsl_dev->clk) / mode->clock / 1000;
> > +
> > +	/* Configure timings: */
> > +	hbp = mode->htotal - mode->hsync_end;
> > +	hfp = mode->hsync_start - mode->hdisplay;
> > +	hsw = mode->hsync_end - mode->hsync_start;
> > +	vbp = mode->vtotal - mode->vsync_end;
> > +	vfp = mode->vsync_start - mode->vdisplay;
> > +	vsw = mode->vsync_end - mode->vsync_start;
> > +
> > +	regmap_write(fsl_dev->regmap, DCU_HSYN_PARA,
> > +		     DCU_HSYN_PARA_BP(hbp) |
> > +		     DCU_HSYN_PARA_PW(hsw) |
> > +		     DCU_HSYN_PARA_FP(hfp));
> > +	regmap_write(fsl_dev->regmap, DCU_VSYN_PARA,
> > +		     DCU_VSYN_PARA_BP(vbp) |
> > +		     DCU_VSYN_PARA_PW(vsw) |
> > +		     DCU_VSYN_PARA_FP(vfp));
> > +	regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
> > +		     DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) |
> > +		     DCU_DISP_SIZE_DELTA_X(mode->hdisplay));
> > +	regmap_write(fsl_dev->regmap, DCU_DIV_RATIO, div);
> > +	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
> DCU_UPDATE_MODE_READREG);
> > +}
> > +
> > +static bool fsl_dcu_drm_crtc_mode_fixup(struct drm_crtc *crtc,
> > +					const struct drm_display_mode *mode,
> > +					struct drm_display_mode *adjusted_mode)
> > +{
> > +	return true;
> > +}
> > +
> > +static void fsl_dcu_drm_crtc_prepare(struct drm_crtc *crtc)
> > +{
> > +}
> > +
> > +/* Now enable the clocks, plane, pipe, and connectors that we set up.
> */
> > +static void fsl_dcu_drm_crtc_mode_commit(struct drm_crtc *crtc)
> > +{
> > +}
> > +
> > +static int fsl_dcu_drm_crtc_atomic_check(struct drm_crtc *crtc,
> > +					 struct drm_crtc_state *state)
> > +{
> > +	return 0;
> > +}
> > +
> > +static void fsl_dcu_drm_crtc_atomic_begin(struct drm_crtc *crtc)
> > +{
> > +}
> > +
> > +static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc)
> > +{
> > +}
> > +
> > +static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
> > +{
> > +}
> > +
> > +static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs = {
> > +	.page_flip = drm_atomic_helper_page_flip,
> > +	.set_config = drm_atomic_helper_set_config,
> > +	.destroy = drm_crtc_cleanup,
> > +	.reset = drm_atomic_helper_crtc_reset,
> > +	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
> > +	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
> > +};
> > +
> > +static void fsl_dcu_drm_crtc_dpms(struct drm_crtc *crtc, int mode)
> > +{
> > +}
> > +
> > +static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs
> = {
> > +	.disable = fsl_dcu_drm_disable_crtc,
> > +	.mode_fixup = fsl_dcu_drm_crtc_mode_fixup,
> > +	.mode_set = drm_helper_crtc_mode_set,
> > +	.mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb,
> > +	.mode_set_base = drm_helper_crtc_mode_set_base,
> > +	.prepare = fsl_dcu_drm_crtc_prepare,
> > +	.commit = fsl_dcu_drm_crtc_mode_commit,
> > +	.atomic_check = fsl_dcu_drm_crtc_atomic_check,
> > +	.atomic_begin = fsl_dcu_drm_crtc_atomic_begin,
> > +	.atomic_flush = fsl_dcu_drm_crtc_atomic_flush,
> > +	.dpms = fsl_dcu_drm_crtc_dpms,
> > +};
> > +
> > +int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
> > +{
> > +	struct drm_plane *primary;
> > +	struct drm_crtc *crtc = &fsl_dev->crtc.crtc;
> > +	int ret;
> > +
> > +	fsl_dev->crtc.dpms = DRM_MODE_DPMS_OFF;
> > +
> > +	primary = fsl_dcu_drm_primary_create_plane(fsl_dev->ddev);
> > +	ret = drm_crtc_init_with_planes(fsl_dev->ddev, crtc, primary, NULL,
> > +					&fsl_dcu_drm_crtc_funcs);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs);
> > +
> > +	regmap_write(fsl_dev->regmap, DCU_SYN_POL,
> > +		     DCU_SYN_POL_INV_VS_LOW | DCU_SYN_POL_INV_HS_LOW);
> > +	regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |
> > +		     DCU_BGND_G(0) | DCU_BGND_B(0));
> > +	regmap_write(fsl_dev->regmap, DCU_DCU_MODE,
> > +		     DCU_MODE_BLEND_ITER(1) | DCU_MODE_RASTER_EN);
> > +	regmap_write(fsl_dev->regmap, DCU_THRESHOLD,
> > +		     DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
> > +		     DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
> > +		     DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
> > +	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
> > +			   DCU_MODE_DCU_MODE_MASK,
> > +			   DCU_MODE_DCU_MODE(DCU_MODE_OFF));
> > +	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
> DCU_UPDATE_MODE_READREG);
> > +
> > +	return 0;
> > +}
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.h
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.h
> > new file mode 100644
> > index 0000000..d44b564
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.h
> > @@ -0,0 +1,26 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#ifndef __FSL_DCU_DRM_CRTC_H__
> > +#define __FSL_DCU_DRM_CRTC_H__
> > +
> > +#include <drm/drmP.h>
> > +#include <drm/drm_crtc.h>
> > +
> > +struct fsl_dcu_drm_device;
> > +struct fsl_dcu_drm_crtc {
> > +	struct drm_crtc crtc;
> > +	int dpms;
> > +};
> > +
> > +int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev);
> > +
> > +#endif /* __FSL_DCU_DRM_CRTC_H__ */
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c
> > new file mode 100644
> > index 0000000..d4a559a
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c
> > @@ -0,0 +1,331 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/io.h>
> > +#include <linux/mm.h>
> > +#include <linux/module.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/regmap.h>
> > +
> > +#include <drm/drmP.h>
> > +#include <linux/fsl/dcu.h>
> 
> This file seems to be missing in that patch.
> 
 
This file in patch 2/4, It's LS1021A platform related code.

> > +
> > +#include "fsl_dcu_drm_drv.h"
> > +#include "fsl_dcu_drm_kms.h"
> > +
> > +static int fsl_dcu_unload(struct drm_device *dev)
> > +{
> > +	drm_mode_config_cleanup(dev);
> > +	drm_vblank_cleanup(dev);
> > +	drm_irq_uninstall(dev);
> > +
> > +	dev->dev_private = NULL;
> > +
> > +	return 0;
> > +}
> > +
> > +static struct regmap_config fsl_dcu_regmap_config = {
> > +	.reg_bits = 32,
> > +	.reg_stride = 4,
> > +	.val_bits = 32,
> > +};
> > +
> > +static int fsl_dcu_bypass_tcon(struct fsl_dcu_drm_device *fsl_dev,
> > +			       struct device_node *np)
> > +{
> > +	struct device_node *tcon_np;
> > +	struct platform_device *pdev;
> > +	struct clk *tcon_clk;
> > +	struct resource *res;
> > +	void __iomem *base;
> > +
> > +	tcon_np = of_parse_phandle(np, "tcon-controller", 0);
> > +	if (!tcon_np)
> > +		return -EINVAL;
> > +
> > +	pdev = of_find_device_by_node(tcon_np);
> > +	if (!pdev)
> > +		return -EINVAL;
> > +
> > +	tcon_clk = devm_clk_get(&pdev->dev, "tcon");
> > +	if (IS_ERR(tcon_clk))
> > +		return PTR_ERR(tcon_clk);
> > +	clk_prepare_enable(tcon_clk);
> 
> You enable the clock explicitly...
> 
> > +
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	if (!res)
> > +		return -ENODEV;
> > +
> > +	base = devm_ioremap_resource(&pdev->dev, res);
> > +	if (IS_ERR(base))
> > +		return PTR_ERR(base);
> > +
> > +	fsl_dev->tcon_regmap = devm_regmap_init_mmio_clk(&pdev->dev,
> > +			"tcon", base, &fsl_dcu_regmap_config);
> 
> And implicitly using regmap. In a short test on Vybrid, the clock is
> actually not needed during operation, hence we could use the explicit
> enabling above, what do you think?
> 
> Also, the clock and tcon in general currently does not get handled by
> suspend/resume code...
> 

OK, I'll update code here

> > +	if (IS_ERR(fsl_dev->tcon_regmap)) {
> > +		dev_err(&pdev->dev, "regmap init failed\n");
> > +		return PTR_ERR(fsl_dev->tcon_regmap);
> > +	}
> > +
> > +	regmap_write(fsl_dev->tcon_regmap, TCON_CTRL1, TCON_BYPASS_ENABLE);
> > +	return 0;
> > +}
> > +
> > +static int fsl_dcu_drm_irq_init(struct drm_device *dev)
> > +{
> > +	struct platform_device *pdev = dev->platformdev;
> > +	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
> > +	unsigned int int_mask;
> > +	int ret;
> > +
> > +	ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
> > +	if (ret < 0)
> > +		dev_err(&pdev->dev, "failed to install IRQ handler\n");
> > +
> > +	dev->irq_enabled = true;
> > +	dev->vblank_disable_allowed = true;
> > +
> > +	regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0);
> > +	regmap_read(fsl_dev->regmap, DCU_INT_MASK, &int_mask);
> > +	regmap_write(fsl_dev->regmap, DCU_INT_MASK, int_mask &
> > +		     ~DCU_INT_MASK_VBLANK);
> > +	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
> DCU_UPDATE_MODE_READREG);
> > +
> > +	return 0;
> > +}
> > +
> > +static int fsl_dcu_load(struct drm_device *dev, unsigned long flags)
> > +{
> > +	struct platform_device *pdev = dev->platformdev;
> > +	struct fsl_dcu_drm_device *fsl_dev;
> > +	struct resource *res;
> > +	void __iomem *base;
> > +	int ret;
> > +
> > +	fsl_dev = devm_kzalloc(&pdev->dev, sizeof(*fsl_dev), GFP_KERNEL);
> > +	if (!fsl_dev)
> > +		return -ENOMEM;
> > +
> > +	fsl_dev->dev = &pdev->dev;
> > +	fsl_dev->ddev = dev;
> > +	fsl_dev->np = pdev->dev.of_node;
> > +	dev->dev_private = fsl_dev;
> > +	drm_dev_set_unique(dev, dev_name(dev->dev));
> > +
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	if (!res) {
> > +		dev_err(&pdev->dev, "could not get memory IO resource\n");
> > +		return -ENODEV;
> > +	}
> > +
> > +	base = devm_ioremap_resource(&pdev->dev, res);
> > +	if (IS_ERR(base)) {
> > +		ret = PTR_ERR(base);
> > +		return ret;
> > +	}
> > +
> > +	fsl_dev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL,
> > +			base, &fsl_dcu_regmap_config);
> > +	if (IS_ERR(fsl_dev->regmap)) {
> > +		dev_err(&pdev->dev, "regmap init failed\n");
> > +		return PTR_ERR(fsl_dev->regmap);
> > +	}
> > +
> > +	/* Put TCON in bypass mode, so the input signals from DCU are passed
> > +	 * through TCON unchanged */
> > +	fsl_dcu_bypass_tcon(fsl_dev, fsl_dev->np);
> > +	fsl_dev->clk = devm_clk_get(&pdev->dev, "dcu");
> > +	if (IS_ERR(fsl_dev->clk)) {
> > +		ret = PTR_ERR(fsl_dev->clk);
> > +		dev_err(&pdev->dev, "could not get clock\n");
> > +		return ret;
> > +	}
> > +	clk_prepare_enable(fsl_dev->clk);
> > +	dev_set_drvdata(dev->dev, fsl_dev);
> > +
> > +	ret = fsl_dcu_drm_modeset_init(fsl_dev);
> > +	if (ret < 0) {
> > +		dev_err(&pdev->dev, "failed to initialize mode setting\n");
> > +		return ret;
> > +	}
> > +
> > +	ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
> > +	if (ret < 0) {
> > +		dev_err(&pdev->dev, "failed to initialize vblank\n");
> > +		goto done;
> > +	}
> > +
> > +	ret = fsl_dcu_drm_irq_init(dev);
> > +	if (ret < 0)
> > +		goto done;
> > +
> > +	fsl_dcu_fbdev_init(dev);
> > +
> > +	return 0;
> > +done:
> > +	if (ret)
> > +		fsl_dcu_unload(dev);
> > +
> > +	return ret;
> > +}
> > +
> > +static void fsl_dcu_drm_preclose(struct drm_device *dev, struct
> drm_file *file)
> > +{
> > +	;
> > +}
> > +
> > +static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg)
> > +{
> > +	struct drm_device *dev = arg;
> > +	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
> > +	unsigned int int_status;
> > +
> > +	regmap_read(fsl_dev->regmap, DCU_INT_STATUS, &int_status);
> > +	if (int_status & DCU_INT_STATUS_VBLANK)
> > +		drm_handle_vblank(dev, 0);
> > +
> > +	regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0xffffffff);
> > +	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
> DCU_UPDATE_MODE_READREG);
> > +
> > +	return IRQ_HANDLED;
> > +}
> > +
> > +static int fsl_dcu_drm_enable_vblank(struct drm_device *dev, int crtc)
> > +{
> > +	return 0;
> > +}
> > +
> > +static void fsl_dcu_drm_disable_vblank(struct drm_device *dev, int crtc)
> > +{
> > +	;
> > +}
> > +
> > +static const struct file_operations fsl_dcu_drm_fops = {
> > +	.owner		= THIS_MODULE,
> > +	.open		= drm_open,
> > +	.release	= drm_release,
> > +	.unlocked_ioctl	= drm_ioctl,
> > +#ifdef CONFIG_COMPAT
> > +	.compat_ioctl	= drm_compat_ioctl,
> > +#endif
> > +	.poll		= drm_poll,
> > +	.read		= drm_read,
> > +	.llseek		= no_llseek,
> > +	.mmap		= drm_gem_cma_mmap,
> > +};
> > +
> > +static struct drm_driver fsl_dcu_drm_driver = {
> > +	.driver_features	= DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET
> > +				| DRIVER_PRIME,
> > +	.load			= fsl_dcu_load,
> > +	.unload			= fsl_dcu_unload,
> > +	.preclose		= fsl_dcu_drm_preclose,
> > +	.irq_handler		= fsl_dcu_drm_irq,
> > +	.get_vblank_counter	= drm_vblank_count,
> > +	.enable_vblank		= fsl_dcu_drm_enable_vblank,
> > +	.disable_vblank		= fsl_dcu_drm_disable_vblank,
> > +	.gem_free_object	= drm_gem_cma_free_object,
> > +	.gem_vm_ops		= &drm_gem_cma_vm_ops,
> > +	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
> > +	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
> > +	.gem_prime_import	= drm_gem_prime_import,
> > +	.gem_prime_export	= drm_gem_prime_export,
> > +	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
> > +	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> > +	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
> > +	.gem_prime_vunmap	= drm_gem_cma_prime_vunmap,
> > +	.gem_prime_mmap		= drm_gem_cma_prime_mmap,
> > +	.dumb_create		= drm_gem_cma_dumb_create,
> > +	.dumb_map_offset	= drm_gem_cma_dumb_map_offset,
> > +	.dumb_destroy		= drm_gem_dumb_destroy,
> > +	.fops			= &fsl_dcu_drm_fops,
> > +	.name			= "fsl-dcu-drm",
> > +	.desc			= "Freescale DCU DRM",
> > +	.date			= "20150213",
> > +	.major			= 1,
> > +	.minor			= 0,
> > +};
> > +
> > +#ifdef CONFIG_PM_SLEEP
> > +static int fsl_dcu_drm_pm_suspend(struct device *dev)
> > +{
> > +	struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
> > +
> > +	if (of_device_is_compatible(fsl_dev->np, "fsl,ls1021a-dcu"))
> > +		dcu_pixclk_disable();
> > +
> > +	drm_kms_helper_poll_disable(fsl_dev->ddev);
> > +	fsl_dcu_drm_crtc_suspend(&fsl_dev->crtc);
> 
> I get
> 
> drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c: In function
> 'fsl_dcu_drm_pm_suspend':
> drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c:270:2: error: implicit declaration
> of function 'fsl_dcu_drm_crtc_suspend'
> [-Werror=implicit-function-declaration]
>   fsl_dcu_drm_crtc_suspend(&fsl_dev->crtc);
>   ^
> drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c: In function
> 'fsl_dcu_drm_pm_resume':
> drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c:280:2: error: implicit declaration
> of function 'fsl_dcu_drm_crtc_resume'
> [-Werror=implicit-function-declaration]
>   fsl_dcu_drm_crtc_resume(&fsl_dev->crtc);
>   ^
> 
> The function fsl_dcu_drm_crtc_suspend seems to be part of
> fsl_dcu_drm_crtc.c, but is empty. While the other is missing
> completely... Please fix/remove as appropriate.
> 

OK, I'll fix it

Regards
Jianwei
> > +
> > +	return 0;
> > +}
> > +
> > +static int fsl_dcu_drm_pm_resume(struct device *dev)
> > +{
> > +	struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
> > +
> > +	drm_modeset_lock_all(fsl_dev->ddev);
> > +	fsl_dcu_drm_crtc_resume(&fsl_dev->crtc);
> > +	drm_modeset_unlock_all(fsl_dev->ddev);
> > +	drm_kms_helper_poll_enable(fsl_dev->ddev);
> > +
> > +	if (of_device_is_compatible(fsl_dev->np, "fsl,ls1021a-dcu"))
> > +		dcu_pixclk_enable();
> > +
> > +	return 0;
> > +}
> > +#endif
> > +
> > +static const struct dev_pm_ops fsl_dcu_drm_pm_ops = {
> > +	SET_SYSTEM_SLEEP_PM_OPS(fsl_dcu_drm_pm_suspend,
> fsl_dcu_drm_pm_resume)
> > +};
> > +
> > +static int fsl_dcu_drm_probe(struct platform_device *pdev)
> > +{
> > +	return drm_platform_init(&fsl_dcu_drm_driver, pdev);
> > +}
> > +
> > +static int fsl_dcu_drm_remove(struct platform_device *pdev)
> > +{
> > +	struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
> > +
> > +	drm_put_dev(fsl_dev->ddev);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct of_device_id fsl_dcu_of_match[] = {
> > +		{ .compatible = "fsl,ls1021a-dcu", },
> > +		{ .compatible = "fsl,vf610-dcu", },
> > +		{ },
> > +};
> > +MODULE_DEVICE_TABLE(of, fsl_dcu_of_match);
> > +
> > +static struct platform_driver fsl_dcu_drm_platform_driver = {
> > +	.probe		= fsl_dcu_drm_probe,
> > +	.remove		= fsl_dcu_drm_remove,
> > +	.driver		= {
> > +		.owner	= THIS_MODULE,
> > +		.name	= "fsl,dcu",
> > +		.pm	= &fsl_dcu_drm_pm_ops,
> > +		.of_match_table = fsl_dcu_of_match,
> > +	},
> > +};
> > +
> > +module_platform_driver(fsl_dcu_drm_platform_driver);
> > +
> > +MODULE_ALIAS("platform:fsl-dcu-drm");
> > +MODULE_DESCRIPTION("Freescale DCU DRM Driver");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_drv.h
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_drv.h
> > new file mode 100644
> > index 0000000..27226109
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_drv.h
> > @@ -0,0 +1,210 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#ifndef __FSL_DCU_DRM_DRV_H__
> > +#define __FSL_DCU_DRM_DRV_H__
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/spinlock.h>
> > +#include <stddef.h>
> > +#include <drm/drm.h>
> > +#include <drm/drmP.h>
> > +#include <drm/drm_fb_helper.h>
> > +#include <drm/drm_crtc_helper.h>
> > +#include <drm/drm_gem_cma_helper.h>
> > +#include <drm/drm_fb_cma_helper.h>
> > +
> > +#include "fsl_dcu_drm_crtc.h"
> > +#include "fsl_dcu_drm_plane.h"
> > +#include "fsl_dcu_drm_connector.h"
> > +#define DRIVER_NAME			"fsl-dcu-drm"
> > +
> > +#define DCU_DCU_MODE			0x0010
> > +#define DCU_MODE_BLEND_ITER(x)		((x) << 20)
> > +#define DCU_MODE_RASTER_EN		BIT(14)
> > +#define DCU_MODE_DCU_MODE(x)		(x)
> > +#define DCU_MODE_DCU_MODE_MASK		0x03
> > +#define DCU_MODE_OFF			0
> > +#define DCU_MODE_NORMAL			1
> > +#define DCU_MODE_TEST			2
> > +#define DCU_MODE_COLORBAR		3
> > +
> > +#define DCU_BGND			0x0014
> > +#define DCU_BGND_R(x)			((x) << 16)
> > +#define DCU_BGND_G(x)			((x) << 8)
> > +#define DCU_BGND_B(x)			(x)
> > +
> > +#define DCU_DISP_SIZE			0x0018
> > +#define DCU_DISP_SIZE_DELTA_Y(x)	((x) << 16)
> > +/*Regisiter value 1/16 of horizontal resolution*/
> > +#define DCU_DISP_SIZE_DELTA_X(x)	((x) >> 4)
> > +
> > +#define DCU_HSYN_PARA			0x001c
> > +#define DCU_HSYN_PARA_BP(x)		((x) << 22)
> > +#define DCU_HSYN_PARA_PW(x)		((x) << 11)
> > +#define DCU_HSYN_PARA_FP(x)		(x)
> > +
> > +#define DCU_VSYN_PARA			0x0020
> > +#define DCU_VSYN_PARA_BP(x)		((x) << 22)
> > +#define DCU_VSYN_PARA_PW(x)		((x) << 11)
> > +#define DCU_VSYN_PARA_FP(x)		(x)
> > +
> > +#define DCU_SYN_POL			0x0024
> > +#define DCU_SYN_POL_INV_PXCK_FALL	(0 << 6)
> > +#define DCU_SYN_POL_NEG_REMAIN		(0 << 5)
> > +#define DCU_SYN_POL_INV_VS_LOW		BIT(1)
> > +#define DCU_SYN_POL_INV_HS_LOW		BIT(0)
> > +
> > +#define DCU_THRESHOLD			0x0028
> > +#define DCU_THRESHOLD_LS_BF_VS(x)	((x) << 16)
> > +#define DCU_THRESHOLD_OUT_BUF_HIGH(x)	((x) << 8)
> > +#define DCU_THRESHOLD_OUT_BUF_LOW(x)	(x)
> > +#define BF_VS_VAL			0x03
> > +#define BUF_MAX_VAL			0x78
> > +#define BUF_MIN_VAL			0x0a
> > +
> > +#define DCU_INT_STATUS			0x002C
> > +#define DCU_INT_STATUS_VSYNC		BIT(0)
> > +#define DCU_INT_STATUS_UNDRUN		BIT(1)
> > +#define DCU_INT_STATUS_LSBFVS		BIT(2)
> > +#define DCU_INT_STATUS_VBLANK		BIT(3)
> > +#define DCU_INT_STATUS_CRCREADY		BIT(4)
> > +#define DCU_INT_STATUS_CRCOVERFLOW	BIT(5)
> > +#define DCU_INT_STATUS_P1FIFOLO		BIT(6)
> > +#define DCU_INT_STATUS_P1FIFOHI		BIT(7)
> > +#define DCU_INT_STATUS_P2FIFOLO		BIT(8)
> > +#define DCU_INT_STATUS_P2FIFOHI		BIT(9)
> > +#define DCU_INT_STATUS_PROGEND		BIT(10)
> > +#define DCU_INT_STATUS_IPMERROR		BIT(11)
> > +#define DCU_INT_STATUS_LYRTRANS		BIT(12)
> > +#define DCU_INT_STATUS_DMATRANS		BIT(14)
> > +#define DCU_INT_STATUS_P3FIFOLO		BIT(16)
> > +#define DCU_INT_STATUS_P3FIFOHI		BIT(17)
> > +#define DCU_INT_STATUS_P4FIFOLO		BIT(18)
> > +#define DCU_INT_STATUS_P4FIFOHI		BIT(19)
> > +#define DCU_INT_STATUS_P1EMPTY		BIT(26)
> > +#define DCU_INT_STATUS_P2EMPTY		BIT(27)
> > +#define DCU_INT_STATUS_P3EMPTY		BIT(28)
> > +#define DCU_INT_STATUS_P4EMPTY		BIT(29)
> > +
> > +#define DCU_INT_MASK			0x0030
> > +#define DCU_INT_MASK_VSYNC		BIT(0)
> > +#define DCU_INT_MASK_UNDRUN		BIT(1)
> > +#define DCU_INT_MASK_LSBFVS		BIT(2)
> > +#define DCU_INT_MASK_VBLANK		BIT(3)
> > +#define DCU_INT_MASK_CRCREADY		BIT(4)
> > +#define DCU_INT_MASK_CRCOVERFLOW	BIT(5)
> > +#define DCU_INT_MASK_P1FIFOLO		BIT(6)
> > +#define DCU_INT_MASK_P1FIFOHI		BIT(7)
> > +#define DCU_INT_MASK_P2FIFOLO		BIT(8)
> > +#define DCU_INT_MASK_P2FIFOHI		BIT(9)
> > +#define DCU_INT_MASK_PROGEND		BIT(10)
> > +#define DCU_INT_MASK_IPMERROR		BIT(11)
> > +#define DCU_INT_MASK_LYRTRANS		BIT(12)
> > +#define DCU_INT_MASK_DMATRANS		BIT(14)
> > +#define DCU_INT_MASK_P3FIFOLO		BIT(16)
> > +#define DCU_INT_MASK_P3FIFOHI		BIT(17)
> > +#define DCU_INT_MASK_P4FIFOLO		BIT(18)
> > +#define DCU_INT_MASK_P4FIFOHI		BIT(19)
> > +#define DCU_INT_MASK_P1EMPTY		BIT(26)
> > +#define DCU_INT_MASK_P2EMPTY		BIT(27)
> > +#define DCU_INT_MASK_P3EMPTY		BIT(28)
> > +#define DCU_INT_MASK_P4EMPTY		BIT(29)
> > +
> > +#define DCU_DIV_RATIO			0x0054
> > +
> > +#define DCU_UPDATE_MODE			0x00cc
> > +#define DCU_UPDATE_MODE_MODE		BIT(31)
> > +#define DCU_UPDATE_MODE_READREG		BIT(30)
> > +
> > +#define DCU_DCFB_MAX			0x300
> > +
> > +#define DCU_CTRLDESCLN_1(x)		(0x200 + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_1_HEIGHT(x)	((x) << 16)
> > +#define DCU_CTRLDESCLN_1_WIDTH(x)	(x)
> > +
> > +#define DCU_CTRLDESCLN_2(x)		(0x204 + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_2_POSY(x)	((x) << 16)
> > +#define DCU_CTRLDESCLN_2_POSX(x)	(x)
> > +
> > +#define DCU_CTRLDESCLN_3(x)		(0x208 + (x) * 0x40)
> > +
> > +#define DCU_CTRLDESCLN_4(x)		(0x20c + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_4_EN		BIT(31)
> > +#define DCU_CTRLDESCLN_4_TILE_EN	BIT(30)
> > +#define DCU_CTRLDESCLN_4_DATA_SEL_CLUT	BIT(29)
> > +#define DCU_CTRLDESCLN_4_SAFETY_EN	BIT(28)
> > +#define DCU_CTRLDESCLN_4_TRANS(x)	((x) << 20)
> > +#define DCU_CTRLDESCLN_4_BPP(x)		((x) << 16)
> > +#define DCU_CTRLDESCLN_4_RLE_EN		BIT(15)
> > +#define DCU_CTRLDESCLN_4_LUOFFS(x)	((x) << 4)
> > +#define DCU_CTRLDESCLN_4_BB_ON		BIT(2)
> > +#define DCU_CTRLDESCLN_4_AB(x)		(x)
> > +
> > +#define DCU_CTRLDESCLN_5(x)		(0x210 + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_5_CKMAX_R(x)	((x) << 16)
> > +#define DCU_CTRLDESCLN_5_CKMAX_G(x)	((x) << 8)
> > +#define DCU_CTRLDESCLN_5_CKMAX_B(x)	(x)
> > +
> > +#define DCU_CTRLDESCLN_6(x)		(0x214 + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_6_CKMIN_R(x)	((x) << 16)
> > +#define DCU_CTRLDESCLN_6_CKMIN_G(x)	((x) << 8)
> > +#define DCU_CTRLDESCLN_6_CKMIN_B(x)	(x)
> > +
> > +#define DCU_CTRLDESCLN_7(x)		(0x218 + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_7_TILE_VER(x)	((x) << 16)
> > +#define DCU_CTRLDESCLN_7_TILE_HOR(x)	(x)
> > +
> > +#define DCU_CTRLDESCLN_8(x)		(0x21c + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_8_FG_FCOLOR(x)	(x)
> > +
> > +#define DCU_CTRLDESCLN_9(x)		(0x220 + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_9_BG_BCOLOR(x)	(x)
> > +
> > +#define DCU_CTRLDESCLN_10(x)		(0x224 + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_10_POST_SKIP(x)	((x) << 16)
> > +#define DCU_CTRLDESCLN_10_PRE_SKIP(x)	(x)
> > +
> > +#define FSL_DCU_RGB565			4
> > +#define FSL_DCU_RGB888			5
> > +#define FSL_DCU_ARGB8888		6
> > +#define FSL_DCU_ARGB1555		11
> > +#define FSL_DCU_ARGB4444		12
> > +#define FSL_DCU_YUV422			14
> > +
> > +#define TCON_CTRL1			0x0000
> > +#define TCON_BYPASS_ENABLE		BIT(29)
> > +
> > +#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
> > +
> > +struct clk;
> > +struct device;
> > +struct drm_device;
> > +
> > +struct fsl_dcu_drm_device {
> > +	struct device *dev;
> > +	struct device_node *np;
> > +	struct regmap *regmap;
> > +	struct regmap *tcon_regmap;
> > +	unsigned int irq;
> > +	struct clk *clk;
> > +	/*protects hardware register*/
> > +	spinlock_t irq_lock;
> > +	struct drm_device *ddev;
> > +	struct drm_fbdev_cma *fbdev;
> > +	struct fsl_dcu_drm_crtc crtc;
> > +	struct drm_encoder encoder;
> > +	struct fsl_dcu_drm_connector connector;
> > +};
> > +
> > +void fsl_dcu_fbdev_init(struct drm_device *dev);
> > +
> > +#endif /* __FSL_DCU_DRM_DRV_H__ */
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_fbdev.c
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_fbdev.c
> > new file mode 100644
> > index 0000000..f8ef0e1
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_fbdev.c
> > @@ -0,0 +1,26 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> it
> > + * under the terms of the GNU General Public License version 2 as
> published by
> > + * the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful, but
> WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> or
> > + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
> License for
> > + * more details.
> > + *
> > + */
> > +
> > +#include <drm/drmP.h>
> > +#include <drm/drm_fb_cma_helper.h>
> > +
> > +#include "fsl_dcu_drm_drv.h"
> > +
> > +/* initialize fbdev helper */
> > +void fsl_dcu_fbdev_init(struct drm_device *dev)
> > +{
> > +	struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev->dev);
> > +
> > +	fsl_dev->fbdev = drm_fbdev_cma_init(dev, 24, 1, 1);
> > +}
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_kms.c
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_kms.c
> > new file mode 100644
> > index 0000000..0de21c6
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_kms.c
> > @@ -0,0 +1,42 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#include <drm/drmP.h>
> > +#include <drm/drm_atomic_helper.h>
> > +
> > +#include "fsl_dcu_drm_crtc.h"
> > +#include "fsl_dcu_drm_connector.h"
> > +#include "fsl_dcu_drm_drv.h"
> > +
> > +static const struct drm_mode_config_funcs fsl_dcu_drm_mode_config_funcs
> = {
> > +	.fb_create = drm_fb_cma_create,
> > +	.atomic_check = drm_atomic_helper_check,
> > +	.atomic_commit = drm_atomic_helper_commit,
> > +};
> > +
> > +int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev)
> > +{
> > +	drm_mode_config_init(fsl_dev->ddev);
> > +
> > +	fsl_dev->ddev->mode_config.min_width = 0;
> > +	fsl_dev->ddev->mode_config.min_height = 0;
> > +	fsl_dev->ddev->mode_config.max_width = 2031;
> > +	fsl_dev->ddev->mode_config.max_height = 2047;
> > +	fsl_dev->ddev->mode_config.funcs = &fsl_dcu_drm_mode_config_funcs;
> > +
> > +	drm_kms_helper_poll_init(fsl_dev->ddev);
> > +	fsl_dcu_drm_crtc_create(fsl_dev);
> > +	fsl_dcu_drm_encoder_create(fsl_dev, &fsl_dev->crtc);
> > +	fsl_dcu_drm_connector_create(fsl_dev, &fsl_dev->encoder);
> > +	drm_mode_config_reset(fsl_dev->ddev);
> > +
> > +	return 0;
> > +}
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_kms.h
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_kms.h
> > new file mode 100644
> > index 0000000..b9bd299
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_kms.h
> > @@ -0,0 +1,17 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#ifndef __FSL_DCU_DRM_KMS_H__
> > +#define __FSL_DCU_DRM_KMS_H__
> > +
> > +int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev);
> > +
> > +#endif /* __FSL_DCU_DRM_KMS_H__ */
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_plane.c
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_plane.c
> > new file mode 100644
> > index 0000000..6146e80
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_plane.c
> > @@ -0,0 +1,192 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#include <drm/drmP.h>
> > +#include <drm/drm_crtc.h>
> > +#include <drm/drm_crtc_helper.h>
> > +#include <drm/drm_fb_cma_helper.h>
> > +#include <drm/drm_gem_cma_helper.h>
> > +#include <linux/regmap.h>
> > +#include <drm/drm_plane_helper.h>
> > +#include <drm/drm_atomic_helper.h>
> > +
> > +#include "fsl_dcu_drm_drv.h"
> > +#include "fsl_dcu_drm_kms.h"
> > +#include "fsl_dcu_drm_plane.h"
> > +
> > +#define to_fsl_dcu_plane(plane) \
> > +	container_of(plane, struct fsl_dcu_drm_plane, plane)
> > +
> > +static int
> > +fsl_dcu_drm_plane_prepare_fb(struct drm_plane *plane,
> > +			     struct drm_framebuffer *fb,
> > +			     const struct drm_plane_state *new_state)
> > +{
> > +	return 0;
> > +}
> > +
> > +static void
> > +fsl_dcu_drm_plane_cleanup_fb(struct drm_plane *plane,
> > +			     struct drm_framebuffer *fb,
> > +			     const struct drm_plane_state *new_state)
> > +{
> > +}
> > +
> > +static int fsl_dcu_drm_plane_atomic_check(struct drm_plane *plane,
> > +					  struct drm_plane_state *state)
> > +{
> > +	return 0;
> > +}
> > +
> > +static void fsl_dcu_drm_plane_atomic_disable(struct drm_plane *plane,
> > +					     struct drm_plane_state *old_state)
> > +{
> > +}
> > +
> > +void fsl_dcu_drm_plane_atomic_update(struct drm_plane *plane,
> > +				     struct drm_plane_state *old_state)
> > +{
> > +	struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private;
> > +	struct drm_plane_state *state = plane->state;
> > +	struct drm_framebuffer *fb = plane->state->fb;
> > +	u32 index, alpha, bpp;
> > +	struct drm_gem_cma_object *gem;
> > +	struct fsl_dcu_drm_plane *fsl_plane = to_fsl_dcu_plane(plane);
> > +
> > +	index = fsl_plane->index;
> > +	gem = drm_fb_cma_get_gem_obj(fb, 0);
> > +
> > +	switch (fb->pixel_format) {
> > +	case DRM_FORMAT_RGB565:
> > +		bpp = FSL_DCU_RGB565;
> > +		alpha = 0xff;
> > +		break;
> > +	case DRM_FORMAT_RGB888:
> > +		bpp = FSL_DCU_RGB888;
> > +		alpha = 0xff;
> > +		break;
> > +	case DRM_FORMAT_ARGB8888:
> > +		bpp = FSL_DCU_ARGB8888;
> > +		alpha = 0xff;
> > +		break;
> > +	case DRM_FORMAT_BGRA4444:
> > +		bpp = FSL_DCU_ARGB4444;
> > +		alpha = 0xff;
> > +		break;
> > +	case DRM_FORMAT_ARGB1555:
> > +		bpp = FSL_DCU_ARGB1555;
> > +		alpha = 0xff;
> > +		break;
> > +	case DRM_FORMAT_YUV422:
> > +		bpp = FSL_DCU_YUV422;
> > +		alpha = 0xff;
> > +		break;
> > +	default:
> > +		return;
> > +	}
> > +
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_1(index),
> > +		     DCU_CTRLDESCLN_1_HEIGHT(state->crtc_h) |
> > +		     DCU_CTRLDESCLN_1_WIDTH(state->crtc_w));
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_2(index),
> > +		     DCU_CTRLDESCLN_2_POSY(state->crtc_y) |
> > +		     DCU_CTRLDESCLN_2_POSX(state->crtc_x));
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_3(index), gem->paddr);
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_4(index),
> > +		     DCU_CTRLDESCLN_4_EN |
> > +		     DCU_CTRLDESCLN_4_TRANS(alpha) |
> > +		     DCU_CTRLDESCLN_4_BPP(bpp) |
> > +		     DCU_CTRLDESCLN_4_AB(0));
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_5(index),
> > +		     DCU_CTRLDESCLN_5_CKMAX_R(0xFF) |
> > +		     DCU_CTRLDESCLN_5_CKMAX_G(0xFF) |
> > +		     DCU_CTRLDESCLN_5_CKMAX_B(0xFF));
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_6(index),
> > +		     DCU_CTRLDESCLN_6_CKMIN_R(0) |
> > +		     DCU_CTRLDESCLN_6_CKMIN_G(0) |
> > +		     DCU_CTRLDESCLN_6_CKMIN_B(0));
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_7(index), 0);
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_8(index),
> > +		     DCU_CTRLDESCLN_8_FG_FCOLOR(0));
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_9(index),
> > +		     DCU_CTRLDESCLN_9_BG_BCOLOR(0));
> > +	if (of_device_is_compatible(fsl_dev->np, "fsl,ls1021a-dcu"))
> > +		regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_10(index),
> > +			     DCU_CTRLDESCLN_10_POST_SKIP(0) |
> > +			     DCU_CTRLDESCLN_10_PRE_SKIP(0));
> > +	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
> > +			   DCU_MODE_DCU_MODE_MASK,
> > +			   DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
> > +	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
> DCU_UPDATE_MODE_READREG);
> > +}
> > +
> > +int fsl_dcu_drm_plane_disable(struct drm_plane *plane)
> > +{
> > +	return 0;
> > +}
> > +
> > +void fsl_dcu_drm_plane_destroy(struct drm_plane *plane)
> > +{
> > +	fsl_dcu_drm_plane_disable(plane);
> > +	drm_plane_cleanup(plane);
> > +}
> > +
> > +static const uint32_t fsl_dcu_drm_plane_formats[] = {
> > +	DRM_FORMAT_RGB565,
> > +	DRM_FORMAT_RGB888,
> > +	DRM_FORMAT_ARGB8888,
> > +	DRM_FORMAT_ARGB4444,
> > +	DRM_FORMAT_ARGB1555,
> > +	DRM_FORMAT_YUV422,
> > +};
> > +
> > +static const struct drm_plane_funcs fsl_dcu_drm_plane_funcs = {
> > +	.update_plane = drm_atomic_helper_update_plane,
> > +	.disable_plane = drm_atomic_helper_disable_plane,
> > +	.destroy = fsl_dcu_drm_plane_destroy,
> > +	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
> > +	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
> > +	.reset = drm_atomic_helper_plane_reset,
> > +};
> > +
> > +static const struct drm_plane_helper_funcs
> fsl_dcu_drm_plane_helper_funcs = {
> > +	.prepare_fb = fsl_dcu_drm_plane_prepare_fb,
> > +	.cleanup_fb = fsl_dcu_drm_plane_cleanup_fb,
> > +	.atomic_check = fsl_dcu_drm_plane_atomic_check,
> > +	.atomic_update = fsl_dcu_drm_plane_atomic_update,
> > +	.atomic_disable = fsl_dcu_drm_plane_atomic_disable,
> > +};
> > +
> > +struct drm_plane *fsl_dcu_drm_primary_create_plane(struct drm_device
> *dev)
> > +{
> > +	struct drm_plane *primary;
> > +	int ret;
> > +
> > +	primary = kzalloc(sizeof(*primary), GFP_KERNEL);
> > +	if (!primary) {
> > +		DRM_DEBUG_KMS("Failed to allocate primary plane\n");
> > +		return NULL;
> > +	}
> > +
> > +	/* possible_crtc's will be filled in later by crtc_init */
> > +	ret = drm_universal_plane_init(dev, primary, 0,
> > +				       &fsl_dcu_drm_plane_funcs,
> > +				       fsl_dcu_drm_plane_formats,
> > +				       ARRAY_SIZE(fsl_dcu_drm_plane_formats),
> > +				       DRM_PLANE_TYPE_PRIMARY);
> > +	if (ret) {
> > +		kfree(primary);
> > +		primary = NULL;
> > +	}
> > +	drm_plane_helper_add(primary, &fsl_dcu_drm_plane_helper_funcs);
> > +
> > +	return primary;
> > +}
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_plane.h
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_plane.h
> > new file mode 100644
> > index 0000000..ccbfa61
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_plane.h
> > @@ -0,0 +1,23 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#ifndef __FSL_DCU_DRM_PLANE_H__
> > +#define __FSL_DCU_DRM_PLANE_H__
> > +
> > +struct fsl_dcu_drm_device;
> > +struct fsl_dcu_drm_plane {
> > +	struct drm_plane plane;
> > +	unsigned int index;
> > +};
> > +
> > +struct drm_plane *fsl_dcu_drm_primary_create_plane(struct drm_device
> *dev);
> > +
> > +#endif /* __FSL_DCU_DRM_PLANE_H__ */
���{.n�+�������+%�����ݶ��w��{.n�+����{��G�����{ay�ʇڙ�,j��f���h��������z_�(�階�ݢj"���m������G������?����&���~��iO��z��v�^�m����������?�I�

From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Jianwei.Wang@freescale.com" <Jianwei.Wang@freescale.com>
Subject: RE: [PATCH v3 1/4] drm/layerscape: Add Freescale DCU DRM driver
Date: Tue, 7 Apr 2015 06:44:47 +0000
Message-ID: <CY1PR0301MB12268B3F7505EFB85D874B499FFD0@CY1PR0301MB1226.namprd03.prod.outlook.com>
References: <1427348225-40731-1-git-send-email-b52261@freescale.com>
 <a248211878c93298700ca1e39ab1812b@agner.ch>
Mime-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: base64
Return-path: <linux-kernel-owner@vger.kernel.org>
In-Reply-To: <a248211878c93298700ca1e39ab1812b@agner.ch>
Content-Language: en-US
Sender: linux-kernel-owner@vger.kernel.org
To: Stefan Agner <stefan@agner.ch>
Cc: Scott Wood <scottwood@freescale.com>, "airlied@linux.ie" <airlied@linux.ie>, "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, Xiubo Li <lixiubo@cmss.chinamobile.com>, Huan Wang <alison.wang@freescale.com>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "Jason.Jin@freescale.com" <Jason.Jin@freescale.com>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>
List-Id: devicetree@vger.kernel.org

SGkgU3RlZmFuLA0KDQpUaGFuayB5b3UgZm9yIHlvdXIgcmV2aWV3IGFuZCB0ZXN0aW5nIG9uIFZ5
YnJpZCBGNjEwIGRldmljZS4gVGhpcyBkcml2ZXIgDQpqdXN0IGltcGxlbWVudCB0aGUgYmFzaWMg
ZnVuY3Rpb25zIGFuZCBpdCBvbmx5IHN1cHBvcnQgdGhlIGV4cG9ydGVkIA0KZnJhbWVidWZmZXIg
YWNjZXNzLiBTb21lIERSTSBpbnRlcmZhY2VzIGFyZSBub3QgaW1wbGVtZW50ZWQgbm93LiBTbyB5
b3VyIA0KdGVzdCByZXN1bHQgaXMgbm9ybWFsLiBJIHdpbGwgaW1wbGVtZW50IHRoZXNlIGludGVy
ZmFjZXMgd2l0aCBwYXRjaGVzIHNvb24gDQphZnRlcndhcmRzLiBJIGRvbid0IHBsYW4gdG8gYWRk
IG5ldyBmZWF0dXJlcyBmb3IgdGhlIGluaXRpYWwgdmVyc2lvbiBkcml2ZXIsDQpvdGhlcndpc2Ug
aXQgd2lsbCBiZSBhIGxvbmcgdGVybSBmb3IgdGhpcyB2ZXJzaW9uLg0KDQpJIHRlc3RlZCBvbiBs
czEwMjFhIHVzaW5nIFRGVCBwYW5lbCwgdGhlcmUgYXJlIG5vIGZsaWNrZXJzIG9uIHRoZSBzY3Jl
ZW4NCndoZW4gaW5zZXJ0aW5nIGEgVVNCIEhJRCBkZXZpY2UuIEkgd2lsbCBkbyBtb3JlIHRlc3Qg
aWYgdGltZSBwZXJtaXRzLg0KDQpCeSB0aGUgd2F5LCBjb3VsZCBwbGVhc2UgZ2l2ZSBtZSBzb21l
IGd1aWRhbmNlIG9uIGhvdyBYLVNlcnZlciB1c2UgRFJNIA0KSW50ZXJmYWNlIGRpcmVjdGx5PyBE
byB5b3UgaGF2ZSBzb21lIHBhcGVycyBvciB3ZWJwYWdlIGFib3V0IHRoaXM/DQoNCk15IHJlcGx5
IGJlbG93Li4uDQoNCj4gDQo+IEhpIEppYW53ZWksDQo+IA0KPiBUaGUgZHJpdmVyIHdvcmtlZCBv
biBhIFZ5YnJpZCBWRjYxMCBkZXZpY2UgdXNpbmcgdGhlIGV4cG9ydGVkDQo+IGZyYW1lYnVmZmVy
LiBIb3dldmVyLCB3aGVuIHVzaW5nIFgtU2VydmVyIHRocm91Z2ggdGhlIERSTSBpbnRlcmZhY2UN
Cj4gZGlyZWN0bHkgKGJ5IHVzaW5nIHRoZSBtb2Rlc2V0dGluZyBkcml2ZXIpIEkgZ2V0IGp1c3Qg
YSBibGFjayBzY3JlZW4gc28NCj4gZmFyLCBzdGlsbCBpbnZlc3RpZ2F0aW5nIHRoZSByZWFzb24u
IFdoYXQgdXNlci1zcGFjZSBpbnRlcmZhY2VzIGRpZCB5b3UNCj4gdGVzdD8NCj4gDQo+IFdoZW4g
dXNpbmcgdGhlIEZCIGRldmljZSBhbmQgaW5zZXJ0IGEgVVNCIEhJRCBkZXZpY2UsIEkgZ2V0IHNv
bWUNCj4gZmxpY2tlcnMgb24gdGhlIHNjcmVlbi4gSSBkaWRuJ3QgaGFkIHRob3NlIG9uIHRoZSBk
Y3VmYiBkcml2ZXIsIGRpZCB5b3UNCj4gbm90aWNlIHNvbWV0aGluZyBsaWtlIHRoaXMgdG9vPyBQ
cm9iYWJseSByZWxhdGVkIHRvIHRoZSByZXNvbHV0aW9uLCBJJ20NCj4gdXNpbmcgVkdBIHJlc29s
dXRpb24uDQo+IA0KPiBTb21lIGNvbW1lbnRzIGJlbG93Lg0KPiANCj4gDQo+IE9uIDIwMTUtMDMt
MjYgMDY6MzcsIEppYW53ZWkgV2FuZyB3cm90ZToNCj4gPiBUaGlzIHBhdGNoIGFkZCBzdXBwb3J0
IGZvciBUd28gRGltZW5zaW9uYWwgQW5pbWF0aW9uIGFuZCBDb21wb3NpdGluZw0KPiA+IEVuZ2lu
ZSAoMkQtQUNFKSBvbiB0aGUgRnJlZXNjYWxlIFNvQ3MuDQo+ID4NCj4gPiAyRC1BQ0UgaXMgYSBG
cmVlc2NhbGUgZGlzcGxheSBjb250cm9sbGVyLiAyRC1BQ0UgZGVzY3JpYmVzDQo+ID4gdGhlIGZ1
bmN0aW9uYWxpdHkgb2YgdGhlIG1vZHVsZSBleHRyZW1lbHkgd2VsbCBpdHMgbmFtZSBpcyBhIHZh
bHVlDQo+ID4gdGhhdCBjYW5ub3QgYmUgdXNlZCBhcyBhIHRva2VuIGluIHByb2dyYW1taW5nIGxh
bmd1YWdlcy4NCj4gPiBJbnN0ZWFkIHRoZSB2YWxpZCB0b2tlbiAiRENVIiBpcyB1c2VkIHRvIHRh
ZyB0aGUgcmVnaXN0ZXIgbmFtZXMgYW5kDQo+ID4gZnVuY3Rpb24gbmFtZXMuDQo+ID4NCj4gPiBU
aGUgRGlzcGxheSBDb250cm9sbGVyIFVuaXQgKERDVSkgbW9kdWxlIGlzIGEgc3lzdGVtIG1hc3Rl
ciB0aGF0DQo+ID4gZmV0Y2hlcyBncmFwaGljcyBzdG9yZWQgaW4gaW50ZXJuYWwgb3IgZXh0ZXJu
YWwgbWVtb3J5IGFuZCBkaXNwbGF5cw0KPiA+IHRoZW0gb24gYSBURlQgTENEIHBhbmVsLiBBIHdp
ZGUgcmFuZ2Ugb2YgcGFuZWwgc2l6ZXMgaXMgc3VwcG9ydGVkDQo+ID4gYW5kIHRoZSB0aW1pbmcg
b2YgdGhlIGludGVyZmFjZSBzaWduYWxzIGlzIGhpZ2hseSBjb25maWd1cmFibGUuDQo+ID4gR3Jh
cGhpY3MgYXJlIHJlYWQgZGlyZWN0bHkgZnJvbSBtZW1vcnkgYW5kIHRoZW4gYmxlbmRlZCBpbiBy
ZWFsLXRpbWUsDQo+ID4gd2hpY2ggYWxsb3dzIGZvciBkeW5hbWljIGNvbnRlbnQgY3JlYXRpb24g
d2l0aCBtaW5pbWFsIENQVQ0KPiA+IGludGVydmVudGlvbi4NCj4gPg0KPiA+IFRoZSBmZWF0dXJl
czoNCj4gPiAoMSkgRnVsbCBSR0I4ODggb3V0cHV0IHRvIFRGVCBMQ0QgcGFuZWwuDQo+ID4gKDIp
IEZvciB0aGUgY3VycmVudCBMQ0QgcGFuZWwsIFdRVkdBICI0ODB4MjcyIiBpcyBzdXBwb3J0ZWQu
DQo+ID4gKDMpIEJsZW5kaW5nIG9mIGVhY2ggcGl4ZWwgdXNpbmcgdXAgdG8gNCBzb3VyY2UgbGF5
ZXJzDQo+ID4gZGVwZW5kZW50IG9uIHNpemUgb2YgcGFuZWwuDQo+IA0KPiBtb2RldGVzdCBvbmx5
IHNob3dzIG9uZSBsYXllciBjdXJyZW50bHkuLi4NCg0KWWVzLCBvbmx5IG9uZSBwbGFuZSBhbmQg
b25lIGZyYW1lYnVmZmVyIHdlcmUgY3JlYXRlZCBub3csIG90aGVycw0KbWF5YmUgY3JlYXRlIGFz
IHVzZXIgcmVxdWlyZW1lbnQgb3IgY3JlYXRlIGFsbCB3aGVuIGluaXRpYWxpemluZywNCkknbSBu
b3Qgc3VyZSBub3cuIFRoaXMgZGVzY3JpYmUgdGhlIGhhcmR3YXJlIGZlYXR1cmUNCg0KPiANCj4g
PiAoNCkgRWFjaCBncmFwaGljIGxheWVyIGNhbiBiZSBwbGFjZWQgd2l0aCBvbmUgcGl4ZWwgcmVz
b2x1dGlvbg0KPiA+IGluIGVpdGhlciBheGlzLg0KPiA+ICg1KSBFYWNoIGdyYXBoaWMgbGF5ZXIg
c3VwcG9ydCBSR0I1NjUgYW5kIFJHQjg4OCBkaXJlY3QgY29sb3JzDQo+ID4gd2l0aG91dCBhbHBo
YSBjaGFubmVsDQo+ID4gYW5kIEJHUkE4ODg4IGRpcmVjdCBjb2xvcnMgd2l0aCBhbiBhbHBoYSBj
aGFubmVsLg0KPiANCj4gVGhlIGFycmF5IGZzbF9kY3VfZHJtX3BsYW5lX2Zvcm1hdHMgYmVsb3cg
c2hvd3MgbW9yZSBmb3JtYXRzLCBkb2VzIHRoaXMNCj4gY29tbWl0IGxvZyBuZWVkcyB1cGRhdGlu
Zz8NCj4gDQoNCkkgYWdyZWUgd2l0aCB5b3VyIHN1Z2dlc3Rpb24sIEkgd2lsbCB1cGRhdGUgdGhp
cyBjb21taXQgbG9nDQoNCj4gPiAoNikgRWFjaCBncmFwaGljIGxheWVyIHN1cHBvcnQgYWxwaGEg
YmxlbmRpbmcgd2l0aCA4LWJpdA0KPiA+IHJlc29sdXRpb24uDQo+ID4NCj4gPiBUaGlzIGlzIGEg
c2ltcGxpZmllZCB2ZXJzaW9uLCBvbmx5IG9uZSBwcmltYXJ5IHBsYW5lLCBvbmUNCj4gPiBmcmFt
ZWJ1ZmZlciBjcmVhdGVkIGZvciBmYmRldiwgb25lIGNydGMsIG9uZSBjb25uZWN0b3IgZm9yDQo+
ID4gVEZUIExDRCBwYW5lbCwgYW4gZW5jb2Rlci4NCj4gPg0KPiA+IFNpZ25lZC1vZmYtYnk6IEFs
aXNvbiBXYW5nIDxiMTg5NjVAZnJlZXNjYWxlLmNvbT4NCj4gPiBTaWduZWQtb2ZmLWJ5OiBYaXVi
byBMaSA8bGl4aXVib0BjbXNzLmNoaW5hbW9iaWxlLmNvbT4NCj4gPiBTaWduZWQtb2ZmLWJ5OiBK
aWFud2VpIFdhbmcgPGI1MjI2MUBmcmVlc2NhbGUuY29tPg0KPiA+IC0tLQ0KPiA+DQo+ID4gQ2hh
bmdlZCBpbiBWMzoNCj4gPg0KPiA+IC0gVGVzdCBkcml2ZXIgb24gVnlicmlkIGJvYXJkIGFuZCBh
ZGQgY29tcGF0aWJsZSBzdHJpbmcNCj4gPiAtIFJlbW92ZSB1bnVzZWQgZnVuY3Rpb25zDQo+ID4g
LSBzZXQgZGVmYXVsdCBjcnRjIGZvciBlbmNvZGVyDQo+ID4gLSByZXBsYWNlIGxlZ2FjeSBmdW5j
dGlvbnMgd2l0aCBhdG9taWMgaGVscCBmdW5jdGlvbnMNCj4gPiAtIFNldCB0aGUgdW5pcXVlIG5h
bWUgb2YgdGhlIERSTSBkZXZpY2UNCj4gPiAtIEltcGxlbWVudCBpcnEgaGFuZGxlIGZ1bmN0aW9u
IGZvciB2YmxhbmsgaW50ZXJydXB0DQo+ID4NCj4gPiBDaGFuZ2VkIGluIHYyOg0KPiA+IC0gQWRk
IGF0b21pYyBzdXBwb3J0DQo+ID4gLSBNb2RpZnkgYmluZGluZ3MgZmlsZQ0KPiA+IC0gUmVuYW1l
IG5vZGUgZm9yIGNvbXBhdGliaWxpdHkNCj4gPiAtIE1vdmUgcGxhdGZvcm0gcmVsYXRlZCBjb2Rl
IG91dCBmb3IgY29tcGF0aWJpbGl0eQ0KPiA+DQo+ID4gIC4uLi9kZXZpY2V0cmVlL2JpbmRpbmdz
L2RybS9mc2wvZnNsLGRjdS50eHQgICAgICAgIHwgIDUwICsrKysNCj4gPiAgZHJpdmVycy9ncHUv
ZHJtL0tjb25maWcgICAgICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKw0KPiA+ICBkcml2
ZXJzL2dwdS9kcm0vTWFrZWZpbGUgICAgICAgICAgICAgICAgICAgICAgICAgICB8ICAgMSArDQo+
ID4gIGRyaXZlcnMvZ3B1L2RybS9mc2wvS2NvbmZpZyAgICAgICAgICAgICAgICAgICAgICAgIHwg
IDE3ICsrDQo+ID4gIGRyaXZlcnMvZ3B1L2RybS9mc2wvTWFrZWZpbGUgICAgICAgICAgICAgICAg
ICAgICAgIHwgICA4ICsNCj4gPiAgZHJpdmVycy9ncHUvZHJtL2ZzbC9mc2xfZGN1X2RybV9jb25u
ZWN0b3IuYyAgICAgICAgfCAxOTMgKysrKysrKysrKysrDQo+ID4gIGRyaXZlcnMvZ3B1L2RybS9m
c2wvZnNsX2RjdV9kcm1fY29ubmVjdG9yLmggICAgICAgIHwgIDMwICsrDQo+ID4gIGRyaXZlcnMv
Z3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fY3J0Yy5jICAgICAgICAgICAgIHwgMTY1ICsrKysrKysr
KysNCj4gPiAgZHJpdmVycy9ncHUvZHJtL2ZzbC9mc2xfZGN1X2RybV9jcnRjLmggICAgICAgICAg
ICAgfCAgMjYgKysNCj4gPiAgZHJpdmVycy9ncHUvZHJtL2ZzbC9mc2xfZGN1X2RybV9kcnYuYyAg
ICAgICAgICAgICAgfCAzMzENCj4gKysrKysrKysrKysrKysrKysrKysrDQo+ID4gIGRyaXZlcnMv
Z3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fZHJ2LmggICAgICAgICAgICAgIHwgMjEwICsrKysrKysr
KysrKysNCj4gPiAgZHJpdmVycy9ncHUvZHJtL2ZzbC9mc2xfZGN1X2RybV9mYmRldi5jICAgICAg
ICAgICAgfCAgMjYgKysNCj4gPiAgZHJpdmVycy9ncHUvZHJtL2ZzbC9mc2xfZGN1X2RybV9rbXMu
YyAgICAgICAgICAgICAgfCAgNDIgKysrDQo+ID4gIGRyaXZlcnMvZ3B1L2RybS9mc2wvZnNsX2Rj
dV9kcm1fa21zLmggICAgICAgICAgICAgIHwgIDE3ICsrDQo+ID4gIGRyaXZlcnMvZ3B1L2RybS9m
c2wvZnNsX2RjdV9kcm1fcGxhbmUuYyAgICAgICAgICAgIHwgMTkyICsrKysrKysrKysrKw0KPiA+
ICBkcml2ZXJzL2dwdS9kcm0vZnNsL2ZzbF9kY3VfZHJtX3BsYW5lLmggICAgICAgICAgICB8ICAy
MyArKw0KPiA+ICAxNiBmaWxlcyBjaGFuZ2VkLCAxMzMzIGluc2VydGlvbnMoKykNCj4gPiAgY3Jl
YXRlIG1vZGUgMTAwNjQ0DQo+IERvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9kcm0v
ZnNsL2ZzbCxkY3UudHh0DQo+ID4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2dwdS9kcm0v
ZnNsL0tjb25maWcNCj4gPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZ3B1L2RybS9mc2wv
TWFrZWZpbGUNCj4gPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZ3B1L2RybS9mc2wvZnNs
X2RjdV9kcm1fY29ubmVjdG9yLmMNCj4gPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZ3B1
L2RybS9mc2wvZnNsX2RjdV9kcm1fY29ubmVjdG9yLmgNCj4gPiAgY3JlYXRlIG1vZGUgMTAwNjQ0
IGRyaXZlcnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fY3J0Yy5jDQo+ID4gIGNyZWF0ZSBtb2Rl
IDEwMDY0NCBkcml2ZXJzL2dwdS9kcm0vZnNsL2ZzbF9kY3VfZHJtX2NydGMuaA0KPiA+ICBjcmVh
dGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL2ZzbC9mc2xfZGN1X2RybV9kcnYuYw0KPiA+
ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL2ZzbC9mc2xfZGN1X2RybV9kcnYu
aA0KPiA+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL2ZzbC9mc2xfZGN1X2Ry
bV9mYmRldi5jDQo+ID4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2dwdS9kcm0vZnNsL2Zz
bF9kY3VfZHJtX2ttcy5jDQo+ID4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2dwdS9kcm0v
ZnNsL2ZzbF9kY3VfZHJtX2ttcy5oDQo+ID4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2dw
dS9kcm0vZnNsL2ZzbF9kY3VfZHJtX3BsYW5lLmMNCj4gPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRy
aXZlcnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fcGxhbmUuaA0KPiA+DQo+ID4gZGlmZiAtLWdp
dCBhL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9kcm0vZnNsL2ZzbCxkY3UudHh0
DQo+ID4gYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZHJtL2ZzbC9mc2wsZGN1
LnR4dA0KPiA+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0DQo+ID4gaW5kZXggMDAwMDAwMC4uYmRjN2Q1
Yg0KPiA+IC0tLSAvZGV2L251bGwNCj4gPiArKysgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUv
YmluZGluZ3MvZHJtL2ZzbC9mc2wsZGN1LnR4dA0KPiA+IEBAIC0wLDAgKzEsNTAgQEANCj4gPiAr
RGV2aWNlIFRyZWUgYmluZGluZ3MgZm9yIEZyZWVzY2FsZSBEQ1UgRFJNIERyaXZlcg0KPiA+ICsN
Cj4gPiArUmVxdWlyZWQgcHJvcGVydGllczoNCj4gPiArLSBjb21wYXRpYmxlOiAgICAgICAgICAg
U2hvdWxkIGJlIG9uZSBvZg0KPiA+ICsJKiAiZnNsLGxzMTAyMWEtZGN1Ii4NCj4gPiArCSogImZz
bCx2ZjYxMC1kY3UiLg0KPiANCj4gSW4gdGhlIFZ5YnJpZCByZWZlcmVuY2UgbWFudWFsLCB0aGF0
IElQIGlzIGRlbm90ZWQgYXMgIkRDVTQiLiBBbnkgcmVhc29uDQo+IHdoeSB5b3UgbGVmdCBvdXQg
dGhlIERDVSB2ZXJzaW9uPyBJcyB0aGlzIGRpZmZlcmVudCBmb3IgTFMxMDIxYT8gT24gdGhlDQo+
IG90aGVyIGhhbmQsIHdpdGggdGhlIFNvQyBpbiB0aGUgbmFtZSwgdGhlIElQIHNob3VsZCBiZSBz
cGVjaWZpZWQgY2xlYXINCj4gZW5vdWdoLg0KPiANCg0KSW4gdGhlIExTMTAyMUEgcmVmZXJlbmNl
IG1hbnVhbCwgbm8gRENVIHZlcnNpb24gcmVsYXRlZCB3b3Jkcy4gSSBhc2tlZA0KcHJldmlvdXMg
RENVIG93bmVyLCBzaGUgdG9sZCBtZSB0aGF0IExTMTAyMUEgdXNlIERDVTUgYW5kIHNoZSBhbHNv
IHBvaW50DQpvdXQgdGhhdCB0aGUgc2FtZSBEQ1UgdmVyc2lvbiB0aGVyZSBtYXkgYmUgZGlmZmVy
ZW5jZXMgYmV0d2VlbiBkaWZmZXJlbnQgDQpTb0NzLiBTbyBJIG5hbWVkIGNvbXBhdGlibGUgc3Ry
aW5nIHdpdGggU29DIG5hbWUuDQoNCj4gPiArLSByZWc6ICAgICAgICAgICAgICAgICAgQWRkcmVz
cyBhbmQgbGVuZ3RoIG9mIHRoZSByZWdpc3RlciBzZXQgZm9yIGRjdS4NCj4gPiArLSBjbG9ja3M6
ICAgICAgICAgICAgICAgRnJvbSBjb21tb24gY2xvY2sgYmluZGluZzogaGFuZGxlIHRvIGRjdSBj
bG9jay4NCj4gPiArLSBjbG9jay1uYW1lczogICAgICAgICAgRnJvbSBjb21tb24gY2xvY2sgYmlu
ZGluZzogU2hhbGwgYmUgImRjdSIuDQo+ID4gKy0gZGlzcGxheTogICAgICAgICAgICAgIFRoZSBw
aGFuZGxlIHRvIGRpc3BsYXkgbm9kZS4NCj4gPiArDQo+ID4gK1JlcXVpcmVkIHByb3BlcnRpZXM6
DQo+ID4gKy0gYml0cy1wZXItcGl4ZWw6ICAgICAgIDwxNj4gZm9yIFJHQjU2NSwNCj4gPiArCQkJ
PDI0PiBmb3IgUkdCODg4LA0KPiA+ICsJCQk8MzI+IGZvciBSR0I4ODg4Lg0KPiA+ICsNCj4gPiAr
UmVxdWlyZWQgdGltaW5nIG5vZGUgZm9yIGRpc3BwbGF5IHN1Yi1ub2RlOg0KPiA+ICstIGRpc3Bs
YXktdGltaW5nczogICAgICBSZWZlciB0byBiaW5kaW5nIGRvYyBkaXNwbGF5LXRpbWluZy50eHQg
Zm9yDQo+IGRldGFpbHMuDQo+ID4gKw0KPiA+ICtFeGFtcGxlczoNCj4gPiArZGN1OiBkY3VAMmNl
MDAwMCB7DQo+ID4gKwljb21wYXRpYmxlID0gImZzbCxsczEwMjFhLWRjdSI7DQo+ID4gKwlyZWcg
PSA8MHgwIDB4MmNlMDAwMCAweDAgMHgxMDAwMD47DQo+ID4gKwljbG9ja3MgPSA8JnBsYXRmb3Jt
X2NsayAwPjsNCj4gPiArCWNsb2NrLW5hbWVzID0gImRjdSI7DQo+ID4gKwliaWctZW5kaWFuOw0K
PiA+ICsJZGlzcGxheSA9IDwmZGlzcGxheT47DQo+ID4gKw0KPiA+ICsJZGlzcGxheTogZGlzcGxh
eUAwIHsNCj4gPiArCQliaXRzLXBlci1waXhlbCA9IDwyND47DQo+ID4gKw0KPiA+ICsJCWRpc3Bs
YXktdGltaW5ncyB7DQo+ID4gKwkJCW5hdGl2ZS1tb2RlID0gPCZ0aW1pbmcwPjsNCj4gPiArCQkJ
dGltaW5nMDogbmw0ODI3aGMxOSB7DQo+ID4gKwkJCQljbG9jay1mcmVxdWVuY3kgPSA8MTA4NzAw
MDA+Ow0KPiA+ICsJCQkJaGFjdGl2ZSA9IDw0ODA+Ow0KPiA+ICsJCQkJdmFjdGl2ZSA9IDwyNzI+
Ow0KPiA+ICsJCQkJaGJhY2stcG9yY2ggPSA8Mj47DQo+ID4gKwkJCQloZnJvbnQtcG9yY2ggPSA8
Mj47DQo+ID4gKwkJCQl2YmFjay1wb3JjaCA9IDwxPjsNCj4gPiArCQkJCXZmcm9udC1wb3JjaCA9
IDwxPjsNCj4gPiArCQkJCWhzeW5jLWxlbiA9IDw0MT47DQo+ID4gKwkJCQl2c3luYy1sZW4gPSA8
Mj47DQo+ID4gKwkJCQloc3luYy1hY3RpdmUgPSA8MT47DQo+ID4gKwkJCQl2c3luYy1hY3RpdmUg
PSA8MT47DQo+ID4gKwkJCX07DQo+ID4gKwkJfTsNCj4gPiArCX07DQo+ID4gK307DQo+ID4gKw0K
PiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vS2NvbmZpZyBiL2RyaXZlcnMvZ3B1L2Ry
bS9LY29uZmlnDQo+ID4gaW5kZXggMTUxYTA1MC4uYTY5NTdhYSAxMDA2NDQNCj4gPiAtLS0gYS9k
cml2ZXJzL2dwdS9kcm0vS2NvbmZpZw0KPiA+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9LY29uZmln
DQo+ID4gQEAgLTE5OSw2ICsxOTksOCBAQCBzb3VyY2UgImRyaXZlcnMvZ3B1L2RybS9ib2Nocy9L
Y29uZmlnIg0KPiA+DQo+ID4gIHNvdXJjZSAiZHJpdmVycy9ncHUvZHJtL21zbS9LY29uZmlnIg0K
PiA+DQo+ID4gK3NvdXJjZSAiZHJpdmVycy9ncHUvZHJtL2ZzbC9LY29uZmlnIg0KPiA+ICsNCj4g
PiAgc291cmNlICJkcml2ZXJzL2dwdS9kcm0vdGVncmEvS2NvbmZpZyINCj4gPg0KPiA+ICBzb3Vy
Y2UgImRyaXZlcnMvZ3B1L2RybS9wYW5lbC9LY29uZmlnIg0KPiA+IGRpZmYgLS1naXQgYS9kcml2
ZXJzL2dwdS9kcm0vTWFrZWZpbGUgYi9kcml2ZXJzL2dwdS9kcm0vTWFrZWZpbGUNCj4gPiBpbmRl
eCAyYzIzOWI5Li5hYjViOWVmIDEwMDY0NA0KPiA+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9NYWtl
ZmlsZQ0KPiA+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9NYWtlZmlsZQ0KPiA+IEBAIC01Niw2ICs1
Niw3IEBAIG9iai0kKENPTkZJR19EUk1fVURMKSArPSB1ZGwvDQo+ID4gIG9iai0kKENPTkZJR19E
Uk1fQVNUKSArPSBhc3QvDQo+ID4gIG9iai0kKENPTkZJR19EUk1fQVJNQURBKSArPSBhcm1hZGEv
DQo+ID4gIG9iai0kKENPTkZJR19EUk1fQVRNRUxfSExDREMpCSs9IGF0bWVsLWhsY2RjLw0KPiA+
ICtvYmotJChDT05GSUdfRFJNX0ZTTF9EQ1UpICs9IGZzbC8NCj4gDQo+IEhtLCBJJ20gd29uZGVy
aW5nIHdoZXRoZXIgaXQgd291bGQgYmUgYSBnb29kIGlkZWEgdG8gc3RvcmUgdGhhdCBkcml2ZXIN
Cj4gdW5kZXIgZnNsLWRjdS8uLi4gQW55IG9waW5pb24/DQo+IA0KDQpJIHRoaW5rIGl0IGlzIGdv
b2QgYWR2aWNlLCBJJ2xsIHRoaW5rIGFib3V0IHRoaXMNCg0KPiA+ICBvYmotJChDT05GSUdfRFJN
X1JDQVJfRFUpICs9IHJjYXItZHUvDQo+ID4gIG9iai0kKENPTkZJR19EUk1fU0hNT0JJTEUpICs9
c2htb2JpbGUvDQo+ID4gIG9iai0kKENPTkZJR19EUk1fT01BUCkJKz0gb21hcGRybS8NCj4gPiBk
aWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2ZzbC9LY29uZmlnIGIvZHJpdmVycy9ncHUvZHJt
L2ZzbC9LY29uZmlnDQo+ID4gbmV3IGZpbGUgbW9kZSAxMDA2NDQNCj4gPiBpbmRleCAwMDAwMDAw
Li5lNGY4ZGYwDQo+ID4gLS0tIC9kZXYvbnVsbA0KPiA+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9m
c2wvS2NvbmZpZw0KPiA+IEBAIC0wLDAgKzEsMTcgQEANCj4gPiArY29uZmlnIERSTV9GU0xfRENV
DQo+ID4gKwl0cmlzdGF0ZSAiRFJNIFN1cHBvcnQgZm9yIEZyZWVzY2FsZSBEQ1UiDQo+ID4gKwlk
ZXBlbmRzIG9uIERSTSAmJiBPRiAmJiBBUk0NCj4gPiArCXNlbGVjdCBEUk1fS01TX0hFTFBFUg0K
PiA+ICsJc2VsZWN0IERSTV9LTVNfQ01BX0hFTFBFUg0KPiA+ICsJc2VsZWN0IFZJREVPTU9ERV9I
RUxQRVJTDQo+ID4gKwlzZWxlY3QgQkFDS0xJR0hUX0NMQVNTX0RFVklDRQ0KPiA+ICsJc2VsZWN0
IEJBQ0tMSUdIVF9MQ0RfU1VQUE9SVA0KPiA+ICsJc2VsZWN0IFJFR01BUF9NTUlPDQo+ID4gKwlz
ZWxlY3QgRFJNX0tNU19GQl9IRUxQRVINCj4gPiArCXNlbGVjdCBGQl9TWVNfRklMTFJFQ1QNCj4g
PiArCXNlbGVjdCBGQl9TWVNfQ09QWUFSRUENCj4gPiArCXNlbGVjdCBGQl9TWVNfSU1BR0VCTElU
DQo+ID4gKwlzZWxlY3QgRkJfU1lTX0ZPUFMNCj4gPiArCWhlbHANCj4gPiArCSAgQ2hvb3NlIHRo
aXMgb3B0aW9uIGlmIHlvdSBoYXZlIGFuIEZyZWVzY2FsZSBEQ1UgY2hpcHNldC4NCj4gPiArCSAg
SWYgTSBpcyBzZWxlY3RlZCB0aGUgbW9kdWxlIHdpbGwgYmUgY2FsbGVkIGZzbC1kY3UtZHJtLg0K
PiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vZnNsL01ha2VmaWxlIGIvZHJpdmVycy9n
cHUvZHJtL2ZzbC9NYWtlZmlsZQ0KPiA+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0DQo+ID4gaW5kZXgg
MDAwMDAwMC4uNWY3NGFlZQ0KPiA+IC0tLSAvZGV2L251bGwNCj4gPiArKysgYi9kcml2ZXJzL2dw
dS9kcm0vZnNsL01ha2VmaWxlDQo+ID4gQEAgLTAsMCArMSw4IEBADQo+ID4gK2ZzbC1kY3UtZHJt
LXkgOj0gZnNsX2RjdV9kcm1fZHJ2Lm8gXA0KPiA+ICsJICAgICAgIGZzbF9kY3VfZHJtX2ttcy5v
IFwNCj4gPiArCSAgICAgICBmc2xfZGN1X2RybV9jb25uZWN0b3IubyBcDQo+ID4gKwkgICAgICAg
ZnNsX2RjdV9kcm1fcGxhbmUubyBcDQo+ID4gKwkgICAgICAgZnNsX2RjdV9kcm1fY3J0Yy5vIFwN
Cj4gPiArCSAgICAgICBmc2xfZGN1X2RybV9mYmRldi5vIFwNCj4gPiArDQo+ID4gK29iai0kKENP
TkZJR19EUk1fRlNMX0RDVSkJKz0gZnNsLWRjdS1kcm0ubw0KPiA+IGRpZmYgLS1naXQgYS9kcml2
ZXJzL2dwdS9kcm0vZnNsL2ZzbF9kY3VfZHJtX2Nvbm5lY3Rvci5jDQo+ID4gYi9kcml2ZXJzL2dw
dS9kcm0vZnNsL2ZzbF9kY3VfZHJtX2Nvbm5lY3Rvci5jDQo+ID4gbmV3IGZpbGUgbW9kZSAxMDA2
NDQNCj4gPiBpbmRleCAwMDAwMDAwLi40NjEwNjQ3DQo+ID4gLS0tIC9kZXYvbnVsbA0KPiA+ICsr
KyBiL2RyaXZlcnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fY29ubmVjdG9yLmMNCj4gPiBAQCAt
MCwwICsxLDE5MyBAQA0KPiA+ICsvKg0KPiA+ICsgKiBDb3B5cmlnaHQgMjAxNSBGcmVlc2NhbGUg
U2VtaWNvbmR1Y3RvciwgSW5jLg0KPiA+ICsgKg0KPiA+ICsgKiBGcmVlc2NhbGUgRENVIGRybSBk
ZXZpY2UgZHJpdmVyDQo+ID4gKyAqDQo+ID4gKyAqIFRoaXMgcHJvZ3JhbSBpcyBmcmVlIHNvZnR3
YXJlOyB5b3UgY2FuIHJlZGlzdHJpYnV0ZSBpdCBhbmQvb3IgbW9kaWZ5DQo+ID4gKyAqIGl0IHVu
ZGVyIHRoZSB0ZXJtcyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljIExpY2Vuc2UgYXMgcHVibGlz
aGVkIGJ5DQo+ID4gKyAqIHRoZSBGcmVlIFNvZnR3YXJlIEZvdW5kYXRpb247IGVpdGhlciB2ZXJz
aW9uIDIgb2YgdGhlIExpY2Vuc2UsIG9yDQo+ID4gKyAqIChhdCB5b3VyIG9wdGlvbikgYW55IGxh
dGVyIHZlcnNpb24uDQo+ID4gKyAqLw0KPiA+ICsNCj4gPiArI2luY2x1ZGUgPGxpbnV4L2JhY2ts
aWdodC5oPg0KPiA+ICsNCj4gPiArI2luY2x1ZGUgPGRybS9kcm1QLmg+DQo+ID4gKyNpbmNsdWRl
IDxkcm0vZHJtX2F0b21pY19oZWxwZXIuaD4NCj4gPiArI2luY2x1ZGUgPHZpZGVvL29mX2Rpc3Bs
YXlfdGltaW5nLmg+DQo+ID4gKw0KPiA+ICsjaW5jbHVkZSAiZnNsX2RjdV9kcm1fZHJ2LmgiDQo+
ID4gKyNpbmNsdWRlICJmc2xfZGN1X2RybV9jb25uZWN0b3IuaCINCj4gPiArDQo+ID4gK3N0YXRp
YyB2b2lkIGZzbF9kY3VfZHJtX2VuY29kZXJfZHBtcyhzdHJ1Y3QgZHJtX2VuY29kZXIgKmVuY29k
ZXIsIGludA0KPiBtb2RlKQ0KPiA+ICt7DQo+ID4gK30NCj4gPiArDQo+ID4gK3N0YXRpYyB2b2lk
IGZzbF9kY3VfZHJtX2VuY29kZXJfbW9kZV9wcmVwYXJlKHN0cnVjdCBkcm1fZW5jb2Rlcg0KPiAq
ZW5jb2RlcikNCj4gPiArew0KPiA+ICt9DQo+ID4gKw0KPiA+ICtzdGF0aWMgdm9pZCBmc2xfZGN1
X2RybV9lbmNvZGVyX21vZGVfc2V0KHN0cnVjdCBkcm1fZW5jb2RlciAqZW5jb2RlciwNCj4gPiAr
CQkJCQkgc3RydWN0IGRybV9kaXNwbGF5X21vZGUgKm1vZGUsDQo+ID4gKwkJCQkJIHN0cnVjdCBk
cm1fZGlzcGxheV9tb2RlICphZGp1c3RlZF9tb2RlKQ0KPiA+ICt7DQo+ID4gK30NCj4gPiArDQo+
ID4gK3N0YXRpYyB2b2lkIGZzbF9kY3VfZHJtX2VuY29kZXJfbW9kZV9jb21taXQoc3RydWN0IGRy
bV9lbmNvZGVyICplbmNvZGVyKQ0KPiA+ICt7DQo+ID4gK30NCj4gPiArDQo+ID4gK3N0YXRpYyB2
b2lkIGZzbF9kY3VfZHJtX2VuY29kZXJfZGlzYWJsZShzdHJ1Y3QgZHJtX2VuY29kZXIgKmVuY29k
ZXIpDQo+ID4gK3sNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGljIGludA0KPiA+ICtmc2xfZGN1
X2RybV9lbmNvZGVyX2F0b21pY19jaGVjayhzdHJ1Y3QgZHJtX2VuY29kZXIgKmVuY29kZXIsDQo+
ID4gKwkJCQkgc3RydWN0IGRybV9jcnRjX3N0YXRlICpjcnRjX3N0YXRlLA0KPiA+ICsJCQkJIHN0
cnVjdCBkcm1fY29ubmVjdG9yX3N0YXRlICpjb25uX3N0YXRlKQ0KPiA+ICt7DQo+ID4gKwlyZXR1
cm4gMDsNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGljIHZvaWQgZnNsX2RjdV9kcm1fZW5jb2Rl
cl9kZXN0cm95KHN0cnVjdCBkcm1fZW5jb2RlciAqZW5jb2RlcikNCj4gPiArew0KPiA+ICsJZHJt
X2VuY29kZXJfY2xlYW51cChlbmNvZGVyKTsNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGljIGNv
bnN0IHN0cnVjdCBkcm1fZW5jb2Rlcl9oZWxwZXJfZnVuY3MgZW5jb2Rlcl9oZWxwZXJfZnVuY3Mg
PSB7DQo+ID4gKwkuZHBtcyA9IGZzbF9kY3VfZHJtX2VuY29kZXJfZHBtcywNCj4gPiArCS5wcmVw
YXJlID0gZnNsX2RjdV9kcm1fZW5jb2Rlcl9tb2RlX3ByZXBhcmUsDQo+ID4gKwkuY29tbWl0ID0g
ZnNsX2RjdV9kcm1fZW5jb2Rlcl9tb2RlX2NvbW1pdCwNCj4gPiArCS5tb2RlX3NldCA9IGZzbF9k
Y3VfZHJtX2VuY29kZXJfbW9kZV9zZXQsDQo+ID4gKwkuZGlzYWJsZSA9IGZzbF9kY3VfZHJtX2Vu
Y29kZXJfZGlzYWJsZSwNCj4gPiArCS5hdG9taWNfY2hlY2sgPSBmc2xfZGN1X2RybV9lbmNvZGVy
X2F0b21pY19jaGVjaywNCj4gPiArfTsNCj4gPiArDQo+ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qg
ZHJtX2VuY29kZXJfZnVuY3MgZW5jb2Rlcl9mdW5jcyA9IHsNCj4gPiArCS5kZXN0cm95ID0gZnNs
X2RjdV9kcm1fZW5jb2Rlcl9kZXN0cm95LA0KPiA+ICt9Ow0KPiA+ICsNCj4gPiAraW50IGZzbF9k
Y3VfZHJtX2VuY29kZXJfY3JlYXRlKHN0cnVjdCBmc2xfZGN1X2RybV9kZXZpY2UgKmZzbF9kZXYs
DQo+ID4gKwkJCSAgICAgICBzdHJ1Y3QgZnNsX2RjdV9kcm1fY3J0YyAqY3J0YykNCj4gPiArew0K
PiA+ICsJc3RydWN0IGRybV9lbmNvZGVyICplbmNvZGVyID0gJmZzbF9kZXYtPmVuY29kZXI7DQo+
ID4gKwlpbnQgcmV0Ow0KPiA+ICsNCj4gPiArCXJldCA9IGRybV9lbmNvZGVyX2luaXQoZnNsX2Rl
di0+ZGRldiwgZW5jb2RlciwgJmVuY29kZXJfZnVuY3MsDQo+ID4gKwkJCSAgICAgICBEUk1fTU9E
RV9FTkNPREVSX0xWRFMpOw0KPiA+ICsJaWYgKHJldCA8IDApDQo+ID4gKwkJcmV0dXJuIHJldDsN
Cj4gPiArDQo+ID4gKwlkcm1fZW5jb2Rlcl9oZWxwZXJfYWRkKGVuY29kZXIsICZlbmNvZGVyX2hl
bHBlcl9mdW5jcyk7DQo+ID4gKwllbmNvZGVyLT5jcnRjID0gJmNydGMtPmNydGM7DQo+ID4gKw0K
PiA+ICsJcmV0dXJuIDA7DQo+ID4gK30NCj4gPiArDQo+ID4gKyNkZWZpbmUgdG9fZnNsX2RjdV9j
b25uZWN0b3IoY29ubmVjdG9yKSBcDQo+ID4gKwljb250YWluZXJfb2YoY29ubmVjdG9yLCBzdHJ1
Y3QgZnNsX2RjdV9kcm1fY29ubmVjdG9yLCBjb25uZWN0b3IpDQo+ID4gKw0KPiA+ICtzdGF0aWMg
aW50IGZzbF9kY3VfZHJtX2Nvbm5lY3Rvcl9nZXRfbW9kZXMoc3RydWN0IGRybV9jb25uZWN0b3IN
Cj4gKmNvbm5lY3RvcikNCj4gPiArew0KPiA+ICsJc3RydWN0IGRybV9kZXZpY2UgKmRldiA9IGNv
bm5lY3Rvci0+ZGV2Ow0KPiA+ICsJc3RydWN0IGRldmljZV9ub2RlICpkaXNwbGF5X25wLCAqbnAg
PSBkZXYtPmRldi0+b2Zfbm9kZTsNCj4gPiArCXN0cnVjdCBkcm1fZGlzcGxheV9tb2RlICptb2Rl
ID0gZHJtX21vZGVfY3JlYXRlKGNvbm5lY3Rvci0+ZGV2KTsNCj4gPiArCWludCBudW1fbW9kZXMg
PSAwOw0KPiA+ICsNCj4gPiArCWlmIChucCkgew0KPiA+ICsJCWRpc3BsYXlfbnAgPSBvZl9wYXJz
ZV9waGFuZGxlKG5wLCAiZGlzcGxheSIsIDApOw0KPiA+ICsJCWlmICghZGlzcGxheV9ucCkgew0K
PiA+ICsJCQlkZXZfZXJyKGRldi0+ZGV2LCAiZmFpbGVkIHRvIGZpbmQgZGlzcGxheSBwaGFuZGxl
XG4iKTsNCj4gPiArCQkJcmV0dXJuIG51bV9tb2RlczsNCj4gPiArCQl9DQo+ID4gKwkJb2ZfZ2V0
X2RybV9kaXNwbGF5X21vZGUoZGlzcGxheV9ucCwgbW9kZSwgT0ZfVVNFX05BVElWRV9NT0RFKTsN
Cj4gPiArCQltb2RlLT50eXBlIHw9IERSTV9NT0RFX1RZUEVfRFJJVkVSIHwgRFJNX01PREVfVFlQ
RV9QUkVGRVJSRUQsDQo+ID4gKwkJZHJtX21vZGVfcHJvYmVkX2FkZChjb25uZWN0b3IsIG1vZGUp
Ow0KPiA+ICsJCW51bV9tb2RlcysrOw0KPiA+ICsJfQ0KPiA+ICsNCj4gPiArCXJldHVybiBudW1f
bW9kZXM7DQo+ID4gK30NCj4gPiArDQo+ID4gK3N0YXRpYyBpbnQgZnNsX2RjdV9kcm1fY29ubmVj
dG9yX21vZGVfdmFsaWQoc3RydWN0IGRybV9jb25uZWN0b3INCj4gKmNvbm5lY3RvciwNCj4gPiAr
CQkJCQkgICAgc3RydWN0IGRybV9kaXNwbGF5X21vZGUgKm1vZGUpDQo+ID4gK3sNCj4gPiArCXJl
dHVybiBNT0RFX09LOw0KPiA+ICt9DQo+ID4gKw0KPiA+ICtzdGF0aWMgc3RydWN0IGRybV9lbmNv
ZGVyICoNCj4gPiArZnNsX2RjdV9kcm1fY29ubmVjdG9yX2Jlc3RfZW5jb2RlcihzdHJ1Y3QgZHJt
X2Nvbm5lY3RvciAqY29ubmVjdG9yKQ0KPiA+ICt7DQo+ID4gKwlzdHJ1Y3QgZnNsX2RjdV9kcm1f
Y29ubmVjdG9yICpmc2xfY29uID0NCj4gdG9fZnNsX2RjdV9jb25uZWN0b3IoY29ubmVjdG9yKTsN
Cj4gPiArDQo+ID4gKwlyZXR1cm4gZnNsX2Nvbi0+ZW5jb2RlcjsNCj4gPiArfQ0KPiA+ICsNCj4g
PiArc3RhdGljIHZvaWQgZnNsX2RjdV9kcm1fY29ubmVjdG9yX2Rlc3Ryb3koc3RydWN0IGRybV9j
b25uZWN0b3INCj4gKmNvbm5lY3RvcikNCj4gPiArew0KPiA+ICsJZHJtX2Nvbm5lY3Rvcl91bnJl
Z2lzdGVyKGNvbm5lY3Rvcik7DQo+ID4gKwlkcm1fY29ubmVjdG9yX2NsZWFudXAoY29ubmVjdG9y
KTsNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGljIGVudW0gZHJtX2Nvbm5lY3Rvcl9zdGF0dXMN
Cj4gPiArZnNsX2RjdV9kcm1fY29ubmVjdG9yX2RldGVjdChzdHJ1Y3QgZHJtX2Nvbm5lY3RvciAq
Y29ubmVjdG9yLCBib29sDQo+IGZvcmNlKQ0KPiA+ICt7DQo+ID4gKwlyZXR1cm4gY29ubmVjdG9y
X3N0YXR1c19jb25uZWN0ZWQ7DQo+ID4gK30NCj4gPiArDQo+ID4gK3N0YXRpYyBjb25zdCBzdHJ1
Y3QgZHJtX2Nvbm5lY3Rvcl9mdW5jcyBmc2xfZGN1X2RybV9jb25uZWN0b3JfZnVuY3MgPSB7DQo+
ID4gKwkuZHBtcyA9IGRybV9hdG9taWNfaGVscGVyX2Nvbm5lY3Rvcl9kcG1zLA0KPiA+ICsJLnJl
c2V0ID0gZHJtX2F0b21pY19oZWxwZXJfY29ubmVjdG9yX3Jlc2V0LA0KPiA+ICsJLmRldGVjdCA9
IGZzbF9kY3VfZHJtX2Nvbm5lY3Rvcl9kZXRlY3QsDQo+ID4gKwkuZmlsbF9tb2RlcyA9IGRybV9o
ZWxwZXJfcHJvYmVfc2luZ2xlX2Nvbm5lY3Rvcl9tb2RlcywNCj4gPiArCS5kZXN0cm95ID0gZnNs
X2RjdV9kcm1fY29ubmVjdG9yX2Rlc3Ryb3ksDQo+ID4gKwkuYXRvbWljX2R1cGxpY2F0ZV9zdGF0
ZSA9DQo+IGRybV9hdG9taWNfaGVscGVyX2Nvbm5lY3Rvcl9kdXBsaWNhdGVfc3RhdGUsDQo+ID4g
KwkuYXRvbWljX2Rlc3Ryb3lfc3RhdGUgPSBkcm1fYXRvbWljX2hlbHBlcl9jb25uZWN0b3JfZGVz
dHJveV9zdGF0ZSwNCj4gPiArfTsNCj4gPiArDQo+ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgZHJt
X2Nvbm5lY3Rvcl9oZWxwZXJfZnVuY3MgY29ubmVjdG9yX2hlbHBlcl9mdW5jcyA9DQo+IHsNCj4g
PiArCS5nZXRfbW9kZXMgPSBmc2xfZGN1X2RybV9jb25uZWN0b3JfZ2V0X21vZGVzLA0KPiA+ICsJ
Lm1vZGVfdmFsaWQgPSBmc2xfZGN1X2RybV9jb25uZWN0b3JfbW9kZV92YWxpZCwNCj4gPiArCS5i
ZXN0X2VuY29kZXIgPSBmc2xfZGN1X2RybV9jb25uZWN0b3JfYmVzdF9lbmNvZGVyLA0KPiA+ICt9
Ow0KPiA+ICsNCj4gPiAraW50IGZzbF9kY3VfZHJtX2Nvbm5lY3Rvcl9jcmVhdGUoc3RydWN0IGZz
bF9kY3VfZHJtX2RldmljZSAqZnNsX2RldiwNCj4gPiArCQkJCSBzdHJ1Y3QgZHJtX2VuY29kZXIg
KmVuY29kZXIpDQo+ID4gK3sNCj4gPiArCXN0cnVjdCBkcm1fY29ubmVjdG9yICpjb25uZWN0b3Ig
PSAmZnNsX2Rldi0+Y29ubmVjdG9yLmNvbm5lY3RvcjsNCj4gPiArCWludCByZXQ7DQo+ID4gKw0K
PiA+ICsJZnNsX2Rldi0+Y29ubmVjdG9yLmVuY29kZXIgPSBlbmNvZGVyOw0KPiA+ICsNCj4gPiAr
CWNvbm5lY3Rvci0+ZGlzcGxheV9pbmZvLndpZHRoX21tID0gMDsNCj4gPiArCWNvbm5lY3Rvci0+
ZGlzcGxheV9pbmZvLmhlaWdodF9tbSA9IDA7DQo+ID4gKw0KPiA+ICsJcmV0ID0gZHJtX2Nvbm5l
Y3Rvcl9pbml0KGZzbF9kZXYtPmRkZXYsIGNvbm5lY3RvciwNCj4gPiArCQkJCSAmZnNsX2RjdV9k
cm1fY29ubmVjdG9yX2Z1bmNzLA0KPiA+ICsJCQkJIERSTV9NT0RFX0NPTk5FQ1RPUl9MVkRTKTsN
Cj4gPiArCWlmIChyZXQgPCAwKQ0KPiA+ICsJCXJldHVybiByZXQ7DQo+ID4gKw0KPiA+ICsJY29u
bmVjdG9yLT5kcG1zID0gRFJNX01PREVfRFBNU19PRkY7DQo+ID4gKwlkcm1fY29ubmVjdG9yX2hl
bHBlcl9hZGQoY29ubmVjdG9yLCAmY29ubmVjdG9yX2hlbHBlcl9mdW5jcyk7DQo+ID4gKwlyZXQg
PSBkcm1fY29ubmVjdG9yX3JlZ2lzdGVyKGNvbm5lY3Rvcik7DQo+ID4gKwlpZiAocmV0IDwgMCkN
Cj4gPiArCQlnb3RvIGVycl9jbGVhbnVwOw0KPiA+ICsNCj4gPiArCXJldCA9IGRybV9tb2RlX2Nv
bm5lY3Rvcl9hdHRhY2hfZW5jb2Rlcihjb25uZWN0b3IsIGVuY29kZXIpOw0KPiA+ICsJaWYgKHJl
dCA8IDApDQo+ID4gKwkJZ290byBlcnJfc3lzZnM7DQo+ID4gKw0KPiA+ICsJY29ubmVjdG9yLT5l
bmNvZGVyID0gZW5jb2RlcjsNCj4gPiArDQo+ID4gKwlkcm1fb2JqZWN0X3Byb3BlcnR5X3NldF92
YWx1ZQ0KPiA+ICsJCSgmY29ubmVjdG9yLT5iYXNlLCBmc2xfZGV2LT5kZGV2LT5tb2RlX2NvbmZp
Zy5kcG1zX3Byb3BlcnR5LA0KPiA+ICsJCURSTV9NT0RFX0RQTVNfT0ZGKTsNCj4gPiArDQo+ID4g
KwlyZXR1cm4gMDsNCj4gPiArDQo+ID4gK2Vycl9zeXNmczoNCj4gPiArCWRybV9jb25uZWN0b3Jf
dW5yZWdpc3Rlcihjb25uZWN0b3IpOw0KPiA+ICtlcnJfY2xlYW51cDoNCj4gPiArCWRybV9jb25u
ZWN0b3JfY2xlYW51cChjb25uZWN0b3IpOw0KPiA+ICsJcmV0dXJuIHJldDsNCj4gPiArfQ0KPiA+
IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vZnNsL2ZzbF9kY3VfZHJtX2Nvbm5lY3Rvci5o
DQo+ID4gYi9kcml2ZXJzL2dwdS9kcm0vZnNsL2ZzbF9kY3VfZHJtX2Nvbm5lY3Rvci5oDQo+ID4g
bmV3IGZpbGUgbW9kZSAxMDA2NDQNCj4gPiBpbmRleCAwMDAwMDAwLi5iYmY2ZDM4DQo+ID4gLS0t
IC9kZXYvbnVsbA0KPiA+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fY29u
bmVjdG9yLmgNCj4gPiBAQCAtMCwwICsxLDMwIEBADQo+ID4gKy8qDQo+ID4gKyAqIENvcHlyaWdo
dCAyMDE1IEZyZWVzY2FsZSBTZW1pY29uZHVjdG9yLCBJbmMuDQo+ID4gKyAqDQo+ID4gKyAqIEZy
ZWVzY2FsZSBEQ1UgZHJtIGRldmljZSBkcml2ZXINCj4gPiArICoNCj4gPiArICogVGhpcyBwcm9n
cmFtIGlzIGZyZWUgc29mdHdhcmU7IHlvdSBjYW4gcmVkaXN0cmlidXRlIGl0IGFuZC9vciBtb2Rp
ZnkNCj4gPiArICogaXQgdW5kZXIgdGhlIHRlcm1zIG9mIHRoZSBHTlUgR2VuZXJhbCBQdWJsaWMg
TGljZW5zZSBhcyBwdWJsaXNoZWQgYnkNCj4gPiArICogdGhlIEZyZWUgU29mdHdhcmUgRm91bmRh
dGlvbjsgZWl0aGVyIHZlcnNpb24gMiBvZiB0aGUgTGljZW5zZSwgb3INCj4gPiArICogKGF0IHlv
dXIgb3B0aW9uKSBhbnkgbGF0ZXIgdmVyc2lvbi4NCj4gPiArICovDQo+ID4gKw0KPiA+ICsjaWZu
ZGVmIF9fRlNMX0RDVV9EUk1fQ09OTkVDVE9SX0hfXw0KPiA+ICsjZGVmaW5lIF9fRlNMX0RDVV9E
Uk1fQ09OTkVDVE9SX0hfXw0KPiA+ICsNCj4gPiArI2luY2x1ZGUgPGRybS9kcm1QLmg+DQo+ID4g
KyNpbmNsdWRlIDxkcm0vZHJtX2NydGMuaD4NCj4gPiArI2luY2x1ZGUgImZzbF9kY3VfZHJtX2Ny
dGMuaCINCj4gPiArDQo+ID4gK3N0cnVjdCBmc2xfZGN1X2RybV9kZXZpY2U7DQo+ID4gK3N0cnVj
dCBmc2xfZGN1X2RybV9jb25uZWN0b3Igew0KPiA+ICsJc3RydWN0IGRybV9jb25uZWN0b3IgY29u
bmVjdG9yOw0KPiA+ICsJc3RydWN0IGRybV9lbmNvZGVyICplbmNvZGVyOw0KPiA+ICt9Ow0KPiA+
ICsNCj4gPiAraW50IGZzbF9kY3VfZHJtX2VuY29kZXJfY3JlYXRlKHN0cnVjdCBmc2xfZGN1X2Ry
bV9kZXZpY2UgKmZzbF9kZXYsDQo+ID4gKwkJCSAgICAgICBzdHJ1Y3QgZnNsX2RjdV9kcm1fY3J0
YyAqY3J0Yyk7DQo+ID4gK2ludCBmc2xfZGN1X2RybV9jb25uZWN0b3JfY3JlYXRlKHN0cnVjdCBm
c2xfZGN1X2RybV9kZXZpY2UgKmZzbF9kZXYsDQo+ID4gKwkJCQkgc3RydWN0IGRybV9lbmNvZGVy
ICplbmNvZGVyKTsNCj4gPiArDQo+ID4gKyNlbmRpZiAvKiBfX0ZTTF9EQ1VfRFJNX0NPTk5FQ1RP
Ul9IX18gKi8NCj4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2ZzbC9mc2xfZGN1X2Ry
bV9jcnRjLmMNCj4gPiBiL2RyaXZlcnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fY3J0Yy5jDQo+
ID4gbmV3IGZpbGUgbW9kZSAxMDA2NDQNCj4gPiBpbmRleCAwMDAwMDAwLi4wNzZlMjczDQo+ID4g
LS0tIC9kZXYvbnVsbA0KPiA+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1f
Y3J0Yy5jDQo+ID4gQEAgLTAsMCArMSwxNjUgQEANCj4gPiArLyoNCj4gPiArICogQ29weXJpZ2h0
IDIwMTUgRnJlZXNjYWxlIFNlbWljb25kdWN0b3IsIEluYy4NCj4gPiArICoNCj4gPiArICogRnJl
ZXNjYWxlIERDVSBkcm0gZGV2aWNlIGRyaXZlcg0KPiA+ICsgKg0KPiA+ICsgKiBUaGlzIHByb2dy
YW0gaXMgZnJlZSBzb2Z0d2FyZTsgeW91IGNhbiByZWRpc3RyaWJ1dGUgaXQgYW5kL29yIG1vZGlm
eQ0KPiA+ICsgKiBpdCB1bmRlciB0aGUgdGVybXMgb2YgdGhlIEdOVSBHZW5lcmFsIFB1YmxpYyBM
aWNlbnNlIGFzIHB1Ymxpc2hlZCBieQ0KPiA+ICsgKiB0aGUgRnJlZSBTb2Z0d2FyZSBGb3VuZGF0
aW9uOyBlaXRoZXIgdmVyc2lvbiAyIG9mIHRoZSBMaWNlbnNlLCBvcg0KPiA+ICsgKiAoYXQgeW91
ciBvcHRpb24pIGFueSBsYXRlciB2ZXJzaW9uLg0KPiA+ICsgKi8NCj4gPiArDQo+ID4gKyNpbmNs
dWRlIDxsaW51eC9yZWdtYXAuaD4NCj4gPiArI2luY2x1ZGUgPGxpbnV4L2Nsay5oPg0KPiA+ICsN
Cj4gPiArI2luY2x1ZGUgPGRybS9kcm1QLmg+DQo+ID4gKyNpbmNsdWRlIDxkcm0vZHJtX2F0b21p
Yy5oPg0KPiA+ICsjaW5jbHVkZSA8ZHJtL2RybV9hdG9taWNfaGVscGVyLmg+DQo+ID4gKyNpbmNs
dWRlIDxkcm0vZHJtX2NydGMuaD4NCj4gPiArDQo+ID4gKyNpbmNsdWRlICJmc2xfZGN1X2RybV9j
cnRjLmgiDQo+ID4gKyNpbmNsdWRlICJmc2xfZGN1X2RybV9kcnYuaCINCj4gPiArI2luY2x1ZGUg
ImZzbF9kY3VfZHJtX3BsYW5lLmgiDQo+ID4gKw0KPiA+ICsjZGVmaW5lIHRvX2ZzbF9kY3VfY3J0
YyhjKQljb250YWluZXJfb2YoYywgc3RydWN0IGZzbF9kY3VfZHJtX2NydGMsDQo+IGNydGMpDQo+
ID4gKw0KPiA+ICt2b2lkIGZzbF9kY3VfZHJtX2NydGNfc3VzcGVuZChzdHJ1Y3QgZHJtX2NydGMg
KmNydGMpDQo+ID4gK3sNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGljIHZvaWQgZnNsX2RjdV9k
cm1fY3J0Y19tb2RlX3NldF9ub2ZiKHN0cnVjdCBkcm1fY3J0YyAqY3J0YykNCj4gPiArew0KPiA+
ICsJc3RydWN0IGRybV9kZXZpY2UgKmRldiA9IGNydGMtPmRldjsNCj4gPiArCXN0cnVjdCBmc2xf
ZGN1X2RybV9kZXZpY2UgKmZzbF9kZXYgPSBkZXYtPmRldl9wcml2YXRlOw0KPiA+ICsJc3RydWN0
IGRybV9kaXNwbGF5X21vZGUgKm1vZGUgPSAmY3J0Yy0+c3RhdGUtPm1vZGU7DQo+ID4gKwl1aW50
MzJfdCBoYnAsIGhmcCwgaHN3LCB2YnAsIHZmcCwgdnN3LCBkaXYsIGluZGV4Ow0KPiA+ICsNCj4g
PiArCURCRygiOiBzZXQgbW9kZTogJWQ6XCIlc1wiICVkICVkICVkICVkICVkICVkICVkICVkICVk
ICVkIDB4JXggMHgleCIsDQo+ID4gKwkgICAgbW9kZS0+YmFzZS5pZCwgbW9kZS0+bmFtZSwNCj4g
PiArCSAgICBtb2RlLT52cmVmcmVzaCwgbW9kZS0+Y2xvY2ssDQo+ID4gKwkgICAgbW9kZS0+aGRp
c3BsYXksIG1vZGUtPmhzeW5jX3N0YXJ0LA0KPiA+ICsJICAgIG1vZGUtPmhzeW5jX2VuZCwgbW9k
ZS0+aHRvdGFsLA0KPiA+ICsJICAgIG1vZGUtPnZkaXNwbGF5LCBtb2RlLT52c3luY19zdGFydCwN
Cj4gPiArCSAgICBtb2RlLT52c3luY19lbmQsIG1vZGUtPnZ0b3RhbCwNCj4gPiArCSAgICBtb2Rl
LT50eXBlLCBtb2RlLT5mbGFncyk7DQo+ID4gKw0KPiA+ICsJaW5kZXggPSBkcm1fY3J0Y19pbmRl
eChjcnRjKTsNCj4gPiArCWRpdiA9ICh1aW50MzJfdCljbGtfZ2V0X3JhdGUoZnNsX2Rldi0+Y2xr
KSAvIG1vZGUtPmNsb2NrIC8gMTAwMDsNCj4gPiArDQo+ID4gKwkvKiBDb25maWd1cmUgdGltaW5n
czogKi8NCj4gPiArCWhicCA9IG1vZGUtPmh0b3RhbCAtIG1vZGUtPmhzeW5jX2VuZDsNCj4gPiAr
CWhmcCA9IG1vZGUtPmhzeW5jX3N0YXJ0IC0gbW9kZS0+aGRpc3BsYXk7DQo+ID4gKwloc3cgPSBt
b2RlLT5oc3luY19lbmQgLSBtb2RlLT5oc3luY19zdGFydDsNCj4gPiArCXZicCA9IG1vZGUtPnZ0
b3RhbCAtIG1vZGUtPnZzeW5jX2VuZDsNCj4gPiArCXZmcCA9IG1vZGUtPnZzeW5jX3N0YXJ0IC0g
bW9kZS0+dmRpc3BsYXk7DQo+ID4gKwl2c3cgPSBtb2RlLT52c3luY19lbmQgLSBtb2RlLT52c3lu
Y19zdGFydDsNCj4gPiArDQo+ID4gKwlyZWdtYXBfd3JpdGUoZnNsX2Rldi0+cmVnbWFwLCBEQ1Vf
SFNZTl9QQVJBLA0KPiA+ICsJCSAgICAgRENVX0hTWU5fUEFSQV9CUChoYnApIHwNCj4gPiArCQkg
ICAgIERDVV9IU1lOX1BBUkFfUFcoaHN3KSB8DQo+ID4gKwkJICAgICBEQ1VfSFNZTl9QQVJBX0ZQ
KGhmcCkpOw0KPiA+ICsJcmVnbWFwX3dyaXRlKGZzbF9kZXYtPnJlZ21hcCwgRENVX1ZTWU5fUEFS
QSwNCj4gPiArCQkgICAgIERDVV9WU1lOX1BBUkFfQlAodmJwKSB8DQo+ID4gKwkJICAgICBEQ1Vf
VlNZTl9QQVJBX1BXKHZzdykgfA0KPiA+ICsJCSAgICAgRENVX1ZTWU5fUEFSQV9GUCh2ZnApKTsN
Cj4gPiArCXJlZ21hcF93cml0ZShmc2xfZGV2LT5yZWdtYXAsIERDVV9ESVNQX1NJWkUsDQo+ID4g
KwkJICAgICBEQ1VfRElTUF9TSVpFX0RFTFRBX1kobW9kZS0+dmRpc3BsYXkpIHwNCj4gPiArCQkg
ICAgIERDVV9ESVNQX1NJWkVfREVMVEFfWChtb2RlLT5oZGlzcGxheSkpOw0KPiA+ICsJcmVnbWFw
X3dyaXRlKGZzbF9kZXYtPnJlZ21hcCwgRENVX0RJVl9SQVRJTywgZGl2KTsNCj4gPiArCXJlZ21h
cF93cml0ZShmc2xfZGV2LT5yZWdtYXAsIERDVV9VUERBVEVfTU9ERSwNCj4gRENVX1VQREFURV9N
T0RFX1JFQURSRUcpOw0KPiA+ICt9DQo+ID4gKw0KPiA+ICtzdGF0aWMgYm9vbCBmc2xfZGN1X2Ry
bV9jcnRjX21vZGVfZml4dXAoc3RydWN0IGRybV9jcnRjICpjcnRjLA0KPiA+ICsJCQkJCWNvbnN0
IHN0cnVjdCBkcm1fZGlzcGxheV9tb2RlICptb2RlLA0KPiA+ICsJCQkJCXN0cnVjdCBkcm1fZGlz
cGxheV9tb2RlICphZGp1c3RlZF9tb2RlKQ0KPiA+ICt7DQo+ID4gKwlyZXR1cm4gdHJ1ZTsNCj4g
PiArfQ0KPiA+ICsNCj4gPiArc3RhdGljIHZvaWQgZnNsX2RjdV9kcm1fY3J0Y19wcmVwYXJlKHN0
cnVjdCBkcm1fY3J0YyAqY3J0YykNCj4gPiArew0KPiA+ICt9DQo+ID4gKw0KPiA+ICsvKiBOb3cg
ZW5hYmxlIHRoZSBjbG9ja3MsIHBsYW5lLCBwaXBlLCBhbmQgY29ubmVjdG9ycyB0aGF0IHdlIHNl
dCB1cC4NCj4gKi8NCj4gPiArc3RhdGljIHZvaWQgZnNsX2RjdV9kcm1fY3J0Y19tb2RlX2NvbW1p
dChzdHJ1Y3QgZHJtX2NydGMgKmNydGMpDQo+ID4gK3sNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3Rh
dGljIGludCBmc2xfZGN1X2RybV9jcnRjX2F0b21pY19jaGVjayhzdHJ1Y3QgZHJtX2NydGMgKmNy
dGMsDQo+ID4gKwkJCQkJIHN0cnVjdCBkcm1fY3J0Y19zdGF0ZSAqc3RhdGUpDQo+ID4gK3sNCj4g
PiArCXJldHVybiAwOw0KPiA+ICt9DQo+ID4gKw0KPiA+ICtzdGF0aWMgdm9pZCBmc2xfZGN1X2Ry
bV9jcnRjX2F0b21pY19iZWdpbihzdHJ1Y3QgZHJtX2NydGMgKmNydGMpDQo+ID4gK3sNCj4gPiAr
fQ0KPiA+ICsNCj4gPiArc3RhdGljIHZvaWQgZnNsX2RjdV9kcm1fY3J0Y19hdG9taWNfZmx1c2go
c3RydWN0IGRybV9jcnRjICpjcnRjKQ0KPiA+ICt7DQo+ID4gK30NCj4gPiArDQo+ID4gK3N0YXRp
YyB2b2lkIGZzbF9kY3VfZHJtX2Rpc2FibGVfY3J0YyhzdHJ1Y3QgZHJtX2NydGMgKmNydGMpDQo+
ID4gK3sNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGljIGNvbnN0IHN0cnVjdCBkcm1fY3J0Y19m
dW5jcyBmc2xfZGN1X2RybV9jcnRjX2Z1bmNzID0gew0KPiA+ICsJLnBhZ2VfZmxpcCA9IGRybV9h
dG9taWNfaGVscGVyX3BhZ2VfZmxpcCwNCj4gPiArCS5zZXRfY29uZmlnID0gZHJtX2F0b21pY19o
ZWxwZXJfc2V0X2NvbmZpZywNCj4gPiArCS5kZXN0cm95ID0gZHJtX2NydGNfY2xlYW51cCwNCj4g
PiArCS5yZXNldCA9IGRybV9hdG9taWNfaGVscGVyX2NydGNfcmVzZXQsDQo+ID4gKwkuYXRvbWlj
X2R1cGxpY2F0ZV9zdGF0ZSA9IGRybV9hdG9taWNfaGVscGVyX2NydGNfZHVwbGljYXRlX3N0YXRl
LA0KPiA+ICsJLmF0b21pY19kZXN0cm95X3N0YXRlID0gZHJtX2F0b21pY19oZWxwZXJfY3J0Y19k
ZXN0cm95X3N0YXRlLA0KPiA+ICt9Ow0KPiA+ICsNCj4gPiArc3RhdGljIHZvaWQgZnNsX2RjdV9k
cm1fY3J0Y19kcG1zKHN0cnVjdCBkcm1fY3J0YyAqY3J0YywgaW50IG1vZGUpDQo+ID4gK3sNCj4g
PiArfQ0KPiA+ICsNCj4gPiArc3RhdGljIGNvbnN0IHN0cnVjdCBkcm1fY3J0Y19oZWxwZXJfZnVu
Y3MgZnNsX2RjdV9kcm1fY3J0Y19oZWxwZXJfZnVuY3MNCj4gPSB7DQo+ID4gKwkuZGlzYWJsZSA9
IGZzbF9kY3VfZHJtX2Rpc2FibGVfY3J0YywNCj4gPiArCS5tb2RlX2ZpeHVwID0gZnNsX2RjdV9k
cm1fY3J0Y19tb2RlX2ZpeHVwLA0KPiA+ICsJLm1vZGVfc2V0ID0gZHJtX2hlbHBlcl9jcnRjX21v
ZGVfc2V0LA0KPiA+ICsJLm1vZGVfc2V0X25vZmIgPSBmc2xfZGN1X2RybV9jcnRjX21vZGVfc2V0
X25vZmIsDQo+ID4gKwkubW9kZV9zZXRfYmFzZSA9IGRybV9oZWxwZXJfY3J0Y19tb2RlX3NldF9i
YXNlLA0KPiA+ICsJLnByZXBhcmUgPSBmc2xfZGN1X2RybV9jcnRjX3ByZXBhcmUsDQo+ID4gKwku
Y29tbWl0ID0gZnNsX2RjdV9kcm1fY3J0Y19tb2RlX2NvbW1pdCwNCj4gPiArCS5hdG9taWNfY2hl
Y2sgPSBmc2xfZGN1X2RybV9jcnRjX2F0b21pY19jaGVjaywNCj4gPiArCS5hdG9taWNfYmVnaW4g
PSBmc2xfZGN1X2RybV9jcnRjX2F0b21pY19iZWdpbiwNCj4gPiArCS5hdG9taWNfZmx1c2ggPSBm
c2xfZGN1X2RybV9jcnRjX2F0b21pY19mbHVzaCwNCj4gPiArCS5kcG1zID0gZnNsX2RjdV9kcm1f
Y3J0Y19kcG1zLA0KPiA+ICt9Ow0KPiA+ICsNCj4gPiAraW50IGZzbF9kY3VfZHJtX2NydGNfY3Jl
YXRlKHN0cnVjdCBmc2xfZGN1X2RybV9kZXZpY2UgKmZzbF9kZXYpDQo+ID4gK3sNCj4gPiArCXN0
cnVjdCBkcm1fcGxhbmUgKnByaW1hcnk7DQo+ID4gKwlzdHJ1Y3QgZHJtX2NydGMgKmNydGMgPSAm
ZnNsX2Rldi0+Y3J0Yy5jcnRjOw0KPiA+ICsJaW50IHJldDsNCj4gPiArDQo+ID4gKwlmc2xfZGV2
LT5jcnRjLmRwbXMgPSBEUk1fTU9ERV9EUE1TX09GRjsNCj4gPiArDQo+ID4gKwlwcmltYXJ5ID0g
ZnNsX2RjdV9kcm1fcHJpbWFyeV9jcmVhdGVfcGxhbmUoZnNsX2Rldi0+ZGRldik7DQo+ID4gKwly
ZXQgPSBkcm1fY3J0Y19pbml0X3dpdGhfcGxhbmVzKGZzbF9kZXYtPmRkZXYsIGNydGMsIHByaW1h
cnksIE5VTEwsDQo+ID4gKwkJCQkJJmZzbF9kY3VfZHJtX2NydGNfZnVuY3MpOw0KPiA+ICsJaWYg
KHJldCA8IDApDQo+ID4gKwkJcmV0dXJuIHJldDsNCj4gPiArDQo+ID4gKwlkcm1fY3J0Y19oZWxw
ZXJfYWRkKGNydGMsICZmc2xfZGN1X2RybV9jcnRjX2hlbHBlcl9mdW5jcyk7DQo+ID4gKw0KPiA+
ICsJcmVnbWFwX3dyaXRlKGZzbF9kZXYtPnJlZ21hcCwgRENVX1NZTl9QT0wsDQo+ID4gKwkJICAg
ICBEQ1VfU1lOX1BPTF9JTlZfVlNfTE9XIHwgRENVX1NZTl9QT0xfSU5WX0hTX0xPVyk7DQo+ID4g
KwlyZWdtYXBfd3JpdGUoZnNsX2Rldi0+cmVnbWFwLCBEQ1VfQkdORCwgRENVX0JHTkRfUigwKSB8
DQo+ID4gKwkJICAgICBEQ1VfQkdORF9HKDApIHwgRENVX0JHTkRfQigwKSk7DQo+ID4gKwlyZWdt
YXBfd3JpdGUoZnNsX2Rldi0+cmVnbWFwLCBEQ1VfRENVX01PREUsDQo+ID4gKwkJICAgICBEQ1Vf
TU9ERV9CTEVORF9JVEVSKDEpIHwgRENVX01PREVfUkFTVEVSX0VOKTsNCj4gPiArCXJlZ21hcF93
cml0ZShmc2xfZGV2LT5yZWdtYXAsIERDVV9USFJFU0hPTEQsDQo+ID4gKwkJICAgICBEQ1VfVEhS
RVNIT0xEX0xTX0JGX1ZTKEJGX1ZTX1ZBTCkgfA0KPiA+ICsJCSAgICAgRENVX1RIUkVTSE9MRF9P
VVRfQlVGX0hJR0goQlVGX01BWF9WQUwpIHwNCj4gPiArCQkgICAgIERDVV9USFJFU0hPTERfT1VU
X0JVRl9MT1coQlVGX01JTl9WQUwpKTsNCj4gPiArCXJlZ21hcF91cGRhdGVfYml0cyhmc2xfZGV2
LT5yZWdtYXAsIERDVV9EQ1VfTU9ERSwNCj4gPiArCQkJICAgRENVX01PREVfRENVX01PREVfTUFT
SywNCj4gPiArCQkJICAgRENVX01PREVfRENVX01PREUoRENVX01PREVfT0ZGKSk7DQo+ID4gKwly
ZWdtYXBfd3JpdGUoZnNsX2Rldi0+cmVnbWFwLCBEQ1VfVVBEQVRFX01PREUsDQo+IERDVV9VUERB
VEVfTU9ERV9SRUFEUkVHKTsNCj4gPiArDQo+ID4gKwlyZXR1cm4gMDsNCj4gPiArfQ0KPiA+IGRp
ZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vZnNsL2ZzbF9kY3VfZHJtX2NydGMuaA0KPiA+IGIv
ZHJpdmVycy9ncHUvZHJtL2ZzbC9mc2xfZGN1X2RybV9jcnRjLmgNCj4gPiBuZXcgZmlsZSBtb2Rl
IDEwMDY0NA0KPiA+IGluZGV4IDAwMDAwMDAuLmQ0NGI1NjQNCj4gPiAtLS0gL2Rldi9udWxsDQo+
ID4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2ZzbC9mc2xfZGN1X2RybV9jcnRjLmgNCj4gPiBAQCAt
MCwwICsxLDI2IEBADQo+ID4gKy8qDQo+ID4gKyAqIENvcHlyaWdodCAyMDE1IEZyZWVzY2FsZSBT
ZW1pY29uZHVjdG9yLCBJbmMuDQo+ID4gKyAqDQo+ID4gKyAqIEZyZWVzY2FsZSBEQ1UgZHJtIGRl
dmljZSBkcml2ZXINCj4gPiArICoNCj4gPiArICogVGhpcyBwcm9ncmFtIGlzIGZyZWUgc29mdHdh
cmU7IHlvdSBjYW4gcmVkaXN0cmlidXRlIGl0IGFuZC9vciBtb2RpZnkNCj4gPiArICogaXQgdW5k
ZXIgdGhlIHRlcm1zIG9mIHRoZSBHTlUgR2VuZXJhbCBQdWJsaWMgTGljZW5zZSBhcyBwdWJsaXNo
ZWQgYnkNCj4gPiArICogdGhlIEZyZWUgU29mdHdhcmUgRm91bmRhdGlvbjsgZWl0aGVyIHZlcnNp
b24gMiBvZiB0aGUgTGljZW5zZSwgb3INCj4gPiArICogKGF0IHlvdXIgb3B0aW9uKSBhbnkgbGF0
ZXIgdmVyc2lvbi4NCj4gPiArICovDQo+ID4gKw0KPiA+ICsjaWZuZGVmIF9fRlNMX0RDVV9EUk1f
Q1JUQ19IX18NCj4gPiArI2RlZmluZSBfX0ZTTF9EQ1VfRFJNX0NSVENfSF9fDQo+ID4gKw0KPiA+
ICsjaW5jbHVkZSA8ZHJtL2RybVAuaD4NCj4gPiArI2luY2x1ZGUgPGRybS9kcm1fY3J0Yy5oPg0K
PiA+ICsNCj4gPiArc3RydWN0IGZzbF9kY3VfZHJtX2RldmljZTsNCj4gPiArc3RydWN0IGZzbF9k
Y3VfZHJtX2NydGMgew0KPiA+ICsJc3RydWN0IGRybV9jcnRjIGNydGM7DQo+ID4gKwlpbnQgZHBt
czsNCj4gPiArfTsNCj4gPiArDQo+ID4gK2ludCBmc2xfZGN1X2RybV9jcnRjX2NyZWF0ZShzdHJ1
Y3QgZnNsX2RjdV9kcm1fZGV2aWNlICpmc2xfZGV2KTsNCj4gPiArDQo+ID4gKyNlbmRpZiAvKiBf
X0ZTTF9EQ1VfRFJNX0NSVENfSF9fICovDQo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2Ry
bS9mc2wvZnNsX2RjdV9kcm1fZHJ2LmMNCj4gPiBiL2RyaXZlcnMvZ3B1L2RybS9mc2wvZnNsX2Rj
dV9kcm1fZHJ2LmMNCj4gPiBuZXcgZmlsZSBtb2RlIDEwMDY0NA0KPiA+IGluZGV4IDAwMDAwMDAu
LmQ0YTU1OWENCj4gPiAtLS0gL2Rldi9udWxsDQo+ID4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2Zz
bC9mc2xfZGN1X2RybV9kcnYuYw0KPiA+IEBAIC0wLDAgKzEsMzMxIEBADQo+ID4gKy8qDQo+ID4g
KyAqIENvcHlyaWdodCAyMDE1IEZyZWVzY2FsZSBTZW1pY29uZHVjdG9yLCBJbmMuDQo+ID4gKyAq
DQo+ID4gKyAqIEZyZWVzY2FsZSBEQ1UgZHJtIGRldmljZSBkcml2ZXINCj4gPiArICoNCj4gPiAr
ICogVGhpcyBwcm9ncmFtIGlzIGZyZWUgc29mdHdhcmU7IHlvdSBjYW4gcmVkaXN0cmlidXRlIGl0
IGFuZC9vciBtb2RpZnkNCj4gPiArICogaXQgdW5kZXIgdGhlIHRlcm1zIG9mIHRoZSBHTlUgR2Vu
ZXJhbCBQdWJsaWMgTGljZW5zZSBhcyBwdWJsaXNoZWQgYnkNCj4gPiArICogdGhlIEZyZWUgU29m
dHdhcmUgRm91bmRhdGlvbjsgZWl0aGVyIHZlcnNpb24gMiBvZiB0aGUgTGljZW5zZSwgb3INCj4g
PiArICogKGF0IHlvdXIgb3B0aW9uKSBhbnkgbGF0ZXIgdmVyc2lvbi4NCj4gPiArICovDQo+ID4g
Kw0KPiA+ICsjaW5jbHVkZSA8bGludXgvY2xrLmg+DQo+ID4gKyNpbmNsdWRlIDxsaW51eC9pby5o
Pg0KPiA+ICsjaW5jbHVkZSA8bGludXgvbW0uaD4NCj4gPiArI2luY2x1ZGUgPGxpbnV4L21vZHVs
ZS5oPg0KPiA+ICsjaW5jbHVkZSA8bGludXgvb2ZfcGxhdGZvcm0uaD4NCj4gPiArI2luY2x1ZGUg
PGxpbnV4L3BsYXRmb3JtX2RldmljZS5oPg0KPiA+ICsjaW5jbHVkZSA8bGludXgvcG0uaD4NCj4g
PiArI2luY2x1ZGUgPGxpbnV4L3BtX3J1bnRpbWUuaD4NCj4gPiArI2luY2x1ZGUgPGxpbnV4L3Jl
Z21hcC5oPg0KPiA+ICsNCj4gPiArI2luY2x1ZGUgPGRybS9kcm1QLmg+DQo+ID4gKyNpbmNsdWRl
IDxsaW51eC9mc2wvZGN1Lmg+DQo+IA0KPiBUaGlzIGZpbGUgc2VlbXMgdG8gYmUgbWlzc2luZyBp
biB0aGF0IHBhdGNoLg0KPiANCiANClRoaXMgZmlsZSBpbiBwYXRjaCAyLzQsIEl0J3MgTFMxMDIx
QSBwbGF0Zm9ybSByZWxhdGVkIGNvZGUuDQoNCj4gPiArDQo+ID4gKyNpbmNsdWRlICJmc2xfZGN1
X2RybV9kcnYuaCINCj4gPiArI2luY2x1ZGUgImZzbF9kY3VfZHJtX2ttcy5oIg0KPiA+ICsNCj4g
PiArc3RhdGljIGludCBmc2xfZGN1X3VubG9hZChzdHJ1Y3QgZHJtX2RldmljZSAqZGV2KQ0KPiA+
ICt7DQo+ID4gKwlkcm1fbW9kZV9jb25maWdfY2xlYW51cChkZXYpOw0KPiA+ICsJZHJtX3ZibGFu
a19jbGVhbnVwKGRldik7DQo+ID4gKwlkcm1faXJxX3VuaW5zdGFsbChkZXYpOw0KPiA+ICsNCj4g
PiArCWRldi0+ZGV2X3ByaXZhdGUgPSBOVUxMOw0KPiA+ICsNCj4gPiArCXJldHVybiAwOw0KPiA+
ICt9DQo+ID4gKw0KPiA+ICtzdGF0aWMgc3RydWN0IHJlZ21hcF9jb25maWcgZnNsX2RjdV9yZWdt
YXBfY29uZmlnID0gew0KPiA+ICsJLnJlZ19iaXRzID0gMzIsDQo+ID4gKwkucmVnX3N0cmlkZSA9
IDQsDQo+ID4gKwkudmFsX2JpdHMgPSAzMiwNCj4gPiArfTsNCj4gPiArDQo+ID4gK3N0YXRpYyBp
bnQgZnNsX2RjdV9ieXBhc3NfdGNvbihzdHJ1Y3QgZnNsX2RjdV9kcm1fZGV2aWNlICpmc2xfZGV2
LA0KPiA+ICsJCQkgICAgICAgc3RydWN0IGRldmljZV9ub2RlICpucCkNCj4gPiArew0KPiA+ICsJ
c3RydWN0IGRldmljZV9ub2RlICp0Y29uX25wOw0KPiA+ICsJc3RydWN0IHBsYXRmb3JtX2Rldmlj
ZSAqcGRldjsNCj4gPiArCXN0cnVjdCBjbGsgKnRjb25fY2xrOw0KPiA+ICsJc3RydWN0IHJlc291
cmNlICpyZXM7DQo+ID4gKwl2b2lkIF9faW9tZW0gKmJhc2U7DQo+ID4gKw0KPiA+ICsJdGNvbl9u
cCA9IG9mX3BhcnNlX3BoYW5kbGUobnAsICJ0Y29uLWNvbnRyb2xsZXIiLCAwKTsNCj4gPiArCWlm
ICghdGNvbl9ucCkNCj4gPiArCQlyZXR1cm4gLUVJTlZBTDsNCj4gPiArDQo+ID4gKwlwZGV2ID0g
b2ZfZmluZF9kZXZpY2VfYnlfbm9kZSh0Y29uX25wKTsNCj4gPiArCWlmICghcGRldikNCj4gPiAr
CQlyZXR1cm4gLUVJTlZBTDsNCj4gPiArDQo+ID4gKwl0Y29uX2NsayA9IGRldm1fY2xrX2dldCgm
cGRldi0+ZGV2LCAidGNvbiIpOw0KPiA+ICsJaWYgKElTX0VSUih0Y29uX2NsaykpDQo+ID4gKwkJ
cmV0dXJuIFBUUl9FUlIodGNvbl9jbGspOw0KPiA+ICsJY2xrX3ByZXBhcmVfZW5hYmxlKHRjb25f
Y2xrKTsNCj4gDQo+IFlvdSBlbmFibGUgdGhlIGNsb2NrIGV4cGxpY2l0bHkuLi4NCj4gDQo+ID4g
Kw0KPiA+ICsJcmVzID0gcGxhdGZvcm1fZ2V0X3Jlc291cmNlKHBkZXYsIElPUkVTT1VSQ0VfTUVN
LCAwKTsNCj4gPiArCWlmICghcmVzKQ0KPiA+ICsJCXJldHVybiAtRU5PREVWOw0KPiA+ICsNCj4g
PiArCWJhc2UgPSBkZXZtX2lvcmVtYXBfcmVzb3VyY2UoJnBkZXYtPmRldiwgcmVzKTsNCj4gPiAr
CWlmIChJU19FUlIoYmFzZSkpDQo+ID4gKwkJcmV0dXJuIFBUUl9FUlIoYmFzZSk7DQo+ID4gKw0K
PiA+ICsJZnNsX2Rldi0+dGNvbl9yZWdtYXAgPSBkZXZtX3JlZ21hcF9pbml0X21taW9fY2xrKCZw
ZGV2LT5kZXYsDQo+ID4gKwkJCSJ0Y29uIiwgYmFzZSwgJmZzbF9kY3VfcmVnbWFwX2NvbmZpZyk7
DQo+IA0KPiBBbmQgaW1wbGljaXRseSB1c2luZyByZWdtYXAuIEluIGEgc2hvcnQgdGVzdCBvbiBW
eWJyaWQsIHRoZSBjbG9jayBpcw0KPiBhY3R1YWxseSBub3QgbmVlZGVkIGR1cmluZyBvcGVyYXRp
b24sIGhlbmNlIHdlIGNvdWxkIHVzZSB0aGUgZXhwbGljaXQNCj4gZW5hYmxpbmcgYWJvdmUsIHdo
YXQgZG8geW91IHRoaW5rPw0KPiANCj4gQWxzbywgdGhlIGNsb2NrIGFuZCB0Y29uIGluIGdlbmVy
YWwgY3VycmVudGx5IGRvZXMgbm90IGdldCBoYW5kbGVkIGJ5DQo+IHN1c3BlbmQvcmVzdW1lIGNv
ZGUuLi4NCj4gDQoNCk9LLCBJJ2xsIHVwZGF0ZSBjb2RlIGhlcmUNCg0KPiA+ICsJaWYgKElTX0VS
Uihmc2xfZGV2LT50Y29uX3JlZ21hcCkpIHsNCj4gPiArCQlkZXZfZXJyKCZwZGV2LT5kZXYsICJy
ZWdtYXAgaW5pdCBmYWlsZWRcbiIpOw0KPiA+ICsJCXJldHVybiBQVFJfRVJSKGZzbF9kZXYtPnRj
b25fcmVnbWFwKTsNCj4gPiArCX0NCj4gPiArDQo+ID4gKwlyZWdtYXBfd3JpdGUoZnNsX2Rldi0+
dGNvbl9yZWdtYXAsIFRDT05fQ1RSTDEsIFRDT05fQllQQVNTX0VOQUJMRSk7DQo+ID4gKwlyZXR1
cm4gMDsNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGljIGludCBmc2xfZGN1X2RybV9pcnFfaW5p
dChzdHJ1Y3QgZHJtX2RldmljZSAqZGV2KQ0KPiA+ICt7DQo+ID4gKwlzdHJ1Y3QgcGxhdGZvcm1f
ZGV2aWNlICpwZGV2ID0gZGV2LT5wbGF0Zm9ybWRldjsNCj4gPiArCXN0cnVjdCBmc2xfZGN1X2Ry
bV9kZXZpY2UgKmZzbF9kZXYgPSBkZXYtPmRldl9wcml2YXRlOw0KPiA+ICsJdW5zaWduZWQgaW50
IGludF9tYXNrOw0KPiA+ICsJaW50IHJldDsNCj4gPiArDQo+ID4gKwlyZXQgPSBkcm1faXJxX2lu
c3RhbGwoZGV2LCBwbGF0Zm9ybV9nZXRfaXJxKGRldi0+cGxhdGZvcm1kZXYsIDApKTsNCj4gPiAr
CWlmIChyZXQgPCAwKQ0KPiA+ICsJCWRldl9lcnIoJnBkZXYtPmRldiwgImZhaWxlZCB0byBpbnN0
YWxsIElSUSBoYW5kbGVyXG4iKTsNCj4gPiArDQo+ID4gKwlkZXYtPmlycV9lbmFibGVkID0gdHJ1
ZTsNCj4gPiArCWRldi0+dmJsYW5rX2Rpc2FibGVfYWxsb3dlZCA9IHRydWU7DQo+ID4gKw0KPiA+
ICsJcmVnbWFwX3dyaXRlKGZzbF9kZXYtPnJlZ21hcCwgRENVX0lOVF9TVEFUVVMsIDApOw0KPiA+
ICsJcmVnbWFwX3JlYWQoZnNsX2Rldi0+cmVnbWFwLCBEQ1VfSU5UX01BU0ssICZpbnRfbWFzayk7
DQo+ID4gKwlyZWdtYXBfd3JpdGUoZnNsX2Rldi0+cmVnbWFwLCBEQ1VfSU5UX01BU0ssIGludF9t
YXNrICYNCj4gPiArCQkgICAgIH5EQ1VfSU5UX01BU0tfVkJMQU5LKTsNCj4gPiArCXJlZ21hcF93
cml0ZShmc2xfZGV2LT5yZWdtYXAsIERDVV9VUERBVEVfTU9ERSwNCj4gRENVX1VQREFURV9NT0RF
X1JFQURSRUcpOw0KPiA+ICsNCj4gPiArCXJldHVybiAwOw0KPiA+ICt9DQo+ID4gKw0KPiA+ICtz
dGF0aWMgaW50IGZzbF9kY3VfbG9hZChzdHJ1Y3QgZHJtX2RldmljZSAqZGV2LCB1bnNpZ25lZCBs
b25nIGZsYWdzKQ0KPiA+ICt7DQo+ID4gKwlzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2ID0g
ZGV2LT5wbGF0Zm9ybWRldjsNCj4gPiArCXN0cnVjdCBmc2xfZGN1X2RybV9kZXZpY2UgKmZzbF9k
ZXY7DQo+ID4gKwlzdHJ1Y3QgcmVzb3VyY2UgKnJlczsNCj4gPiArCXZvaWQgX19pb21lbSAqYmFz
ZTsNCj4gPiArCWludCByZXQ7DQo+ID4gKw0KPiA+ICsJZnNsX2RldiA9IGRldm1fa3phbGxvYygm
cGRldi0+ZGV2LCBzaXplb2YoKmZzbF9kZXYpLCBHRlBfS0VSTkVMKTsNCj4gPiArCWlmICghZnNs
X2RldikNCj4gPiArCQlyZXR1cm4gLUVOT01FTTsNCj4gPiArDQo+ID4gKwlmc2xfZGV2LT5kZXYg
PSAmcGRldi0+ZGV2Ow0KPiA+ICsJZnNsX2Rldi0+ZGRldiA9IGRldjsNCj4gPiArCWZzbF9kZXYt
Pm5wID0gcGRldi0+ZGV2Lm9mX25vZGU7DQo+ID4gKwlkZXYtPmRldl9wcml2YXRlID0gZnNsX2Rl
djsNCj4gPiArCWRybV9kZXZfc2V0X3VuaXF1ZShkZXYsIGRldl9uYW1lKGRldi0+ZGV2KSk7DQo+
ID4gKw0KPiA+ICsJcmVzID0gcGxhdGZvcm1fZ2V0X3Jlc291cmNlKHBkZXYsIElPUkVTT1VSQ0Vf
TUVNLCAwKTsNCj4gPiArCWlmICghcmVzKSB7DQo+ID4gKwkJZGV2X2VycigmcGRldi0+ZGV2LCAi
Y291bGQgbm90IGdldCBtZW1vcnkgSU8gcmVzb3VyY2VcbiIpOw0KPiA+ICsJCXJldHVybiAtRU5P
REVWOw0KPiA+ICsJfQ0KPiA+ICsNCj4gPiArCWJhc2UgPSBkZXZtX2lvcmVtYXBfcmVzb3VyY2Uo
JnBkZXYtPmRldiwgcmVzKTsNCj4gPiArCWlmIChJU19FUlIoYmFzZSkpIHsNCj4gPiArCQlyZXQg
PSBQVFJfRVJSKGJhc2UpOw0KPiA+ICsJCXJldHVybiByZXQ7DQo+ID4gKwl9DQo+ID4gKw0KPiA+
ICsJZnNsX2Rldi0+cmVnbWFwID0gZGV2bV9yZWdtYXBfaW5pdF9tbWlvX2NsaygmcGRldi0+ZGV2
LCBOVUxMLA0KPiA+ICsJCQliYXNlLCAmZnNsX2RjdV9yZWdtYXBfY29uZmlnKTsNCj4gPiArCWlm
IChJU19FUlIoZnNsX2Rldi0+cmVnbWFwKSkgew0KPiA+ICsJCWRldl9lcnIoJnBkZXYtPmRldiwg
InJlZ21hcCBpbml0IGZhaWxlZFxuIik7DQo+ID4gKwkJcmV0dXJuIFBUUl9FUlIoZnNsX2Rldi0+
cmVnbWFwKTsNCj4gPiArCX0NCj4gPiArDQo+ID4gKwkvKiBQdXQgVENPTiBpbiBieXBhc3MgbW9k
ZSwgc28gdGhlIGlucHV0IHNpZ25hbHMgZnJvbSBEQ1UgYXJlIHBhc3NlZA0KPiA+ICsJICogdGhy
b3VnaCBUQ09OIHVuY2hhbmdlZCAqLw0KPiA+ICsJZnNsX2RjdV9ieXBhc3NfdGNvbihmc2xfZGV2
LCBmc2xfZGV2LT5ucCk7DQo+ID4gKwlmc2xfZGV2LT5jbGsgPSBkZXZtX2Nsa19nZXQoJnBkZXYt
PmRldiwgImRjdSIpOw0KPiA+ICsJaWYgKElTX0VSUihmc2xfZGV2LT5jbGspKSB7DQo+ID4gKwkJ
cmV0ID0gUFRSX0VSUihmc2xfZGV2LT5jbGspOw0KPiA+ICsJCWRldl9lcnIoJnBkZXYtPmRldiwg
ImNvdWxkIG5vdCBnZXQgY2xvY2tcbiIpOw0KPiA+ICsJCXJldHVybiByZXQ7DQo+ID4gKwl9DQo+
ID4gKwljbGtfcHJlcGFyZV9lbmFibGUoZnNsX2Rldi0+Y2xrKTsNCj4gPiArCWRldl9zZXRfZHJ2
ZGF0YShkZXYtPmRldiwgZnNsX2Rldik7DQo+ID4gKw0KPiA+ICsJcmV0ID0gZnNsX2RjdV9kcm1f
bW9kZXNldF9pbml0KGZzbF9kZXYpOw0KPiA+ICsJaWYgKHJldCA8IDApIHsNCj4gPiArCQlkZXZf
ZXJyKCZwZGV2LT5kZXYsICJmYWlsZWQgdG8gaW5pdGlhbGl6ZSBtb2RlIHNldHRpbmdcbiIpOw0K
PiA+ICsJCXJldHVybiByZXQ7DQo+ID4gKwl9DQo+ID4gKw0KPiA+ICsJcmV0ID0gZHJtX3ZibGFu
a19pbml0KGRldiwgZGV2LT5tb2RlX2NvbmZpZy5udW1fY3J0Yyk7DQo+ID4gKwlpZiAocmV0IDwg
MCkgew0KPiA+ICsJCWRldl9lcnIoJnBkZXYtPmRldiwgImZhaWxlZCB0byBpbml0aWFsaXplIHZi
bGFua1xuIik7DQo+ID4gKwkJZ290byBkb25lOw0KPiA+ICsJfQ0KPiA+ICsNCj4gPiArCXJldCA9
IGZzbF9kY3VfZHJtX2lycV9pbml0KGRldik7DQo+ID4gKwlpZiAocmV0IDwgMCkNCj4gPiArCQln
b3RvIGRvbmU7DQo+ID4gKw0KPiA+ICsJZnNsX2RjdV9mYmRldl9pbml0KGRldik7DQo+ID4gKw0K
PiA+ICsJcmV0dXJuIDA7DQo+ID4gK2RvbmU6DQo+ID4gKwlpZiAocmV0KQ0KPiA+ICsJCWZzbF9k
Y3VfdW5sb2FkKGRldik7DQo+ID4gKw0KPiA+ICsJcmV0dXJuIHJldDsNCj4gPiArfQ0KPiA+ICsN
Cj4gPiArc3RhdGljIHZvaWQgZnNsX2RjdV9kcm1fcHJlY2xvc2Uoc3RydWN0IGRybV9kZXZpY2Ug
KmRldiwgc3RydWN0DQo+IGRybV9maWxlICpmaWxlKQ0KPiA+ICt7DQo+ID4gKwk7DQo+ID4gK30N
Cj4gPiArDQo+ID4gK3N0YXRpYyBpcnFyZXR1cm5fdCBmc2xfZGN1X2RybV9pcnEoaW50IGlycSwg
dm9pZCAqYXJnKQ0KPiA+ICt7DQo+ID4gKwlzdHJ1Y3QgZHJtX2RldmljZSAqZGV2ID0gYXJnOw0K
PiA+ICsJc3RydWN0IGZzbF9kY3VfZHJtX2RldmljZSAqZnNsX2RldiA9IGRldi0+ZGV2X3ByaXZh
dGU7DQo+ID4gKwl1bnNpZ25lZCBpbnQgaW50X3N0YXR1czsNCj4gPiArDQo+ID4gKwlyZWdtYXBf
cmVhZChmc2xfZGV2LT5yZWdtYXAsIERDVV9JTlRfU1RBVFVTLCAmaW50X3N0YXR1cyk7DQo+ID4g
KwlpZiAoaW50X3N0YXR1cyAmIERDVV9JTlRfU1RBVFVTX1ZCTEFOSykNCj4gPiArCQlkcm1faGFu
ZGxlX3ZibGFuayhkZXYsIDApOw0KPiA+ICsNCj4gPiArCXJlZ21hcF93cml0ZShmc2xfZGV2LT5y
ZWdtYXAsIERDVV9JTlRfU1RBVFVTLCAweGZmZmZmZmZmKTsNCj4gPiArCXJlZ21hcF93cml0ZShm
c2xfZGV2LT5yZWdtYXAsIERDVV9VUERBVEVfTU9ERSwNCj4gRENVX1VQREFURV9NT0RFX1JFQURS
RUcpOw0KPiA+ICsNCj4gPiArCXJldHVybiBJUlFfSEFORExFRDsNCj4gPiArfQ0KPiA+ICsNCj4g
PiArc3RhdGljIGludCBmc2xfZGN1X2RybV9lbmFibGVfdmJsYW5rKHN0cnVjdCBkcm1fZGV2aWNl
ICpkZXYsIGludCBjcnRjKQ0KPiA+ICt7DQo+ID4gKwlyZXR1cm4gMDsNCj4gPiArfQ0KPiA+ICsN
Cj4gPiArc3RhdGljIHZvaWQgZnNsX2RjdV9kcm1fZGlzYWJsZV92Ymxhbmsoc3RydWN0IGRybV9k
ZXZpY2UgKmRldiwgaW50IGNydGMpDQo+ID4gK3sNCj4gPiArCTsNCj4gPiArfQ0KPiA+ICsNCj4g
PiArc3RhdGljIGNvbnN0IHN0cnVjdCBmaWxlX29wZXJhdGlvbnMgZnNsX2RjdV9kcm1fZm9wcyA9
IHsNCj4gPiArCS5vd25lcgkJPSBUSElTX01PRFVMRSwNCj4gPiArCS5vcGVuCQk9IGRybV9vcGVu
LA0KPiA+ICsJLnJlbGVhc2UJPSBkcm1fcmVsZWFzZSwNCj4gPiArCS51bmxvY2tlZF9pb2N0bAk9
IGRybV9pb2N0bCwNCj4gPiArI2lmZGVmIENPTkZJR19DT01QQVQNCj4gPiArCS5jb21wYXRfaW9j
dGwJPSBkcm1fY29tcGF0X2lvY3RsLA0KPiA+ICsjZW5kaWYNCj4gPiArCS5wb2xsCQk9IGRybV9w
b2xsLA0KPiA+ICsJLnJlYWQJCT0gZHJtX3JlYWQsDQo+ID4gKwkubGxzZWVrCQk9IG5vX2xsc2Vl
aywNCj4gPiArCS5tbWFwCQk9IGRybV9nZW1fY21hX21tYXAsDQo+ID4gK307DQo+ID4gKw0KPiA+
ICtzdGF0aWMgc3RydWN0IGRybV9kcml2ZXIgZnNsX2RjdV9kcm1fZHJpdmVyID0gew0KPiA+ICsJ
LmRyaXZlcl9mZWF0dXJlcwk9IERSSVZFUl9IQVZFX0lSUSB8IERSSVZFUl9HRU0gfCBEUklWRVJf
TU9ERVNFVA0KPiA+ICsJCQkJfCBEUklWRVJfUFJJTUUsDQo+ID4gKwkubG9hZAkJCT0gZnNsX2Rj
dV9sb2FkLA0KPiA+ICsJLnVubG9hZAkJCT0gZnNsX2RjdV91bmxvYWQsDQo+ID4gKwkucHJlY2xv
c2UJCT0gZnNsX2RjdV9kcm1fcHJlY2xvc2UsDQo+ID4gKwkuaXJxX2hhbmRsZXIJCT0gZnNsX2Rj
dV9kcm1faXJxLA0KPiA+ICsJLmdldF92YmxhbmtfY291bnRlcgk9IGRybV92YmxhbmtfY291bnQs
DQo+ID4gKwkuZW5hYmxlX3ZibGFuawkJPSBmc2xfZGN1X2RybV9lbmFibGVfdmJsYW5rLA0KPiA+
ICsJLmRpc2FibGVfdmJsYW5rCQk9IGZzbF9kY3VfZHJtX2Rpc2FibGVfdmJsYW5rLA0KPiA+ICsJ
LmdlbV9mcmVlX29iamVjdAk9IGRybV9nZW1fY21hX2ZyZWVfb2JqZWN0LA0KPiA+ICsJLmdlbV92
bV9vcHMJCT0gJmRybV9nZW1fY21hX3ZtX29wcywNCj4gPiArCS5wcmltZV9oYW5kbGVfdG9fZmQJ
PSBkcm1fZ2VtX3ByaW1lX2hhbmRsZV90b19mZCwNCj4gPiArCS5wcmltZV9mZF90b19oYW5kbGUJ
PSBkcm1fZ2VtX3ByaW1lX2ZkX3RvX2hhbmRsZSwNCj4gPiArCS5nZW1fcHJpbWVfaW1wb3J0CT0g
ZHJtX2dlbV9wcmltZV9pbXBvcnQsDQo+ID4gKwkuZ2VtX3ByaW1lX2V4cG9ydAk9IGRybV9nZW1f
cHJpbWVfZXhwb3J0LA0KPiA+ICsJLmdlbV9wcmltZV9nZXRfc2dfdGFibGUJPSBkcm1fZ2VtX2Nt
YV9wcmltZV9nZXRfc2dfdGFibGUsDQo+ID4gKwkuZ2VtX3ByaW1lX2ltcG9ydF9zZ190YWJsZSA9
IGRybV9nZW1fY21hX3ByaW1lX2ltcG9ydF9zZ190YWJsZSwNCj4gPiArCS5nZW1fcHJpbWVfdm1h
cAkJPSBkcm1fZ2VtX2NtYV9wcmltZV92bWFwLA0KPiA+ICsJLmdlbV9wcmltZV92dW5tYXAJPSBk
cm1fZ2VtX2NtYV9wcmltZV92dW5tYXAsDQo+ID4gKwkuZ2VtX3ByaW1lX21tYXAJCT0gZHJtX2dl
bV9jbWFfcHJpbWVfbW1hcCwNCj4gPiArCS5kdW1iX2NyZWF0ZQkJPSBkcm1fZ2VtX2NtYV9kdW1i
X2NyZWF0ZSwNCj4gPiArCS5kdW1iX21hcF9vZmZzZXQJPSBkcm1fZ2VtX2NtYV9kdW1iX21hcF9v
ZmZzZXQsDQo+ID4gKwkuZHVtYl9kZXN0cm95CQk9IGRybV9nZW1fZHVtYl9kZXN0cm95LA0KPiA+
ICsJLmZvcHMJCQk9ICZmc2xfZGN1X2RybV9mb3BzLA0KPiA+ICsJLm5hbWUJCQk9ICJmc2wtZGN1
LWRybSIsDQo+ID4gKwkuZGVzYwkJCT0gIkZyZWVzY2FsZSBEQ1UgRFJNIiwNCj4gPiArCS5kYXRl
CQkJPSAiMjAxNTAyMTMiLA0KPiA+ICsJLm1ham9yCQkJPSAxLA0KPiA+ICsJLm1pbm9yCQkJPSAw
LA0KPiA+ICt9Ow0KPiA+ICsNCj4gPiArI2lmZGVmIENPTkZJR19QTV9TTEVFUA0KPiA+ICtzdGF0
aWMgaW50IGZzbF9kY3VfZHJtX3BtX3N1c3BlbmQoc3RydWN0IGRldmljZSAqZGV2KQ0KPiA+ICt7
DQo+ID4gKwlzdHJ1Y3QgZnNsX2RjdV9kcm1fZGV2aWNlICpmc2xfZGV2ID0gZGV2X2dldF9kcnZk
YXRhKGRldik7DQo+ID4gKw0KPiA+ICsJaWYgKG9mX2RldmljZV9pc19jb21wYXRpYmxlKGZzbF9k
ZXYtPm5wLCAiZnNsLGxzMTAyMWEtZGN1IikpDQo+ID4gKwkJZGN1X3BpeGNsa19kaXNhYmxlKCk7
DQo+ID4gKw0KPiA+ICsJZHJtX2ttc19oZWxwZXJfcG9sbF9kaXNhYmxlKGZzbF9kZXYtPmRkZXYp
Ow0KPiA+ICsJZnNsX2RjdV9kcm1fY3J0Y19zdXNwZW5kKCZmc2xfZGV2LT5jcnRjKTsNCj4gDQo+
IEkgZ2V0DQo+IA0KPiBkcml2ZXJzL2dwdS9kcm0vZnNsL2ZzbF9kY3VfZHJtX2Rydi5jOiBJbiBm
dW5jdGlvbg0KPiAnZnNsX2RjdV9kcm1fcG1fc3VzcGVuZCc6DQo+IGRyaXZlcnMvZ3B1L2RybS9m
c2wvZnNsX2RjdV9kcm1fZHJ2LmM6MjcwOjI6IGVycm9yOiBpbXBsaWNpdCBkZWNsYXJhdGlvbg0K
PiBvZiBmdW5jdGlvbiAnZnNsX2RjdV9kcm1fY3J0Y19zdXNwZW5kJw0KPiBbLVdlcnJvcj1pbXBs
aWNpdC1mdW5jdGlvbi1kZWNsYXJhdGlvbl0NCj4gICBmc2xfZGN1X2RybV9jcnRjX3N1c3BlbmQo
JmZzbF9kZXYtPmNydGMpOw0KPiAgIF4NCj4gZHJpdmVycy9ncHUvZHJtL2ZzbC9mc2xfZGN1X2Ry
bV9kcnYuYzogSW4gZnVuY3Rpb24NCj4gJ2ZzbF9kY3VfZHJtX3BtX3Jlc3VtZSc6DQo+IGRyaXZl
cnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fZHJ2LmM6MjgwOjI6IGVycm9yOiBpbXBsaWNpdCBk
ZWNsYXJhdGlvbg0KPiBvZiBmdW5jdGlvbiAnZnNsX2RjdV9kcm1fY3J0Y19yZXN1bWUnDQo+IFst
V2Vycm9yPWltcGxpY2l0LWZ1bmN0aW9uLWRlY2xhcmF0aW9uXQ0KPiAgIGZzbF9kY3VfZHJtX2Ny
dGNfcmVzdW1lKCZmc2xfZGV2LT5jcnRjKTsNCj4gICBeDQo+IA0KPiBUaGUgZnVuY3Rpb24gZnNs
X2RjdV9kcm1fY3J0Y19zdXNwZW5kIHNlZW1zIHRvIGJlIHBhcnQgb2YNCj4gZnNsX2RjdV9kcm1f
Y3J0Yy5jLCBidXQgaXMgZW1wdHkuIFdoaWxlIHRoZSBvdGhlciBpcyBtaXNzaW5nDQo+IGNvbXBs
ZXRlbHkuLi4gUGxlYXNlIGZpeC9yZW1vdmUgYXMgYXBwcm9wcmlhdGUuDQo+IA0KDQpPSywgSSds
bCBmaXggaXQNCg0KUmVnYXJkcw0KSmlhbndlaQ0KPiA+ICsNCj4gPiArCXJldHVybiAwOw0KPiA+
ICt9DQo+ID4gKw0KPiA+ICtzdGF0aWMgaW50IGZzbF9kY3VfZHJtX3BtX3Jlc3VtZShzdHJ1Y3Qg
ZGV2aWNlICpkZXYpDQo+ID4gK3sNCj4gPiArCXN0cnVjdCBmc2xfZGN1X2RybV9kZXZpY2UgKmZz
bF9kZXYgPSBkZXZfZ2V0X2RydmRhdGEoZGV2KTsNCj4gPiArDQo+ID4gKwlkcm1fbW9kZXNldF9s
b2NrX2FsbChmc2xfZGV2LT5kZGV2KTsNCj4gPiArCWZzbF9kY3VfZHJtX2NydGNfcmVzdW1lKCZm
c2xfZGV2LT5jcnRjKTsNCj4gPiArCWRybV9tb2Rlc2V0X3VubG9ja19hbGwoZnNsX2Rldi0+ZGRl
dik7DQo+ID4gKwlkcm1fa21zX2hlbHBlcl9wb2xsX2VuYWJsZShmc2xfZGV2LT5kZGV2KTsNCj4g
PiArDQo+ID4gKwlpZiAob2ZfZGV2aWNlX2lzX2NvbXBhdGlibGUoZnNsX2Rldi0+bnAsICJmc2ws
bHMxMDIxYS1kY3UiKSkNCj4gPiArCQlkY3VfcGl4Y2xrX2VuYWJsZSgpOw0KPiA+ICsNCj4gPiAr
CXJldHVybiAwOw0KPiA+ICt9DQo+ID4gKyNlbmRpZg0KPiA+ICsNCj4gPiArc3RhdGljIGNvbnN0
IHN0cnVjdCBkZXZfcG1fb3BzIGZzbF9kY3VfZHJtX3BtX29wcyA9IHsNCj4gPiArCVNFVF9TWVNU
RU1fU0xFRVBfUE1fT1BTKGZzbF9kY3VfZHJtX3BtX3N1c3BlbmQsDQo+IGZzbF9kY3VfZHJtX3Bt
X3Jlc3VtZSkNCj4gPiArfTsNCj4gPiArDQo+ID4gK3N0YXRpYyBpbnQgZnNsX2RjdV9kcm1fcHJv
YmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikNCj4gPiArew0KPiA+ICsJcmV0dXJuIGRy
bV9wbGF0Zm9ybV9pbml0KCZmc2xfZGN1X2RybV9kcml2ZXIsIHBkZXYpOw0KPiA+ICt9DQo+ID4g
Kw0KPiA+ICtzdGF0aWMgaW50IGZzbF9kY3VfZHJtX3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2
aWNlICpwZGV2KQ0KPiA+ICt7DQo+ID4gKwlzdHJ1Y3QgZnNsX2RjdV9kcm1fZGV2aWNlICpmc2xf
ZGV2ID0gcGxhdGZvcm1fZ2V0X2RydmRhdGEocGRldik7DQo+ID4gKw0KPiA+ICsJZHJtX3B1dF9k
ZXYoZnNsX2Rldi0+ZGRldik7DQo+ID4gKw0KPiA+ICsJcmV0dXJuIDA7DQo+ID4gK30NCj4gPiAr
DQo+ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIGZzbF9kY3Vfb2ZfbWF0Y2hb
XSA9IHsNCj4gPiArCQl7IC5jb21wYXRpYmxlID0gImZzbCxsczEwMjFhLWRjdSIsIH0sDQo+ID4g
KwkJeyAuY29tcGF0aWJsZSA9ICJmc2wsdmY2MTAtZGN1IiwgfSwNCj4gPiArCQl7IH0sDQo+ID4g
K307DQo+ID4gK01PRFVMRV9ERVZJQ0VfVEFCTEUob2YsIGZzbF9kY3Vfb2ZfbWF0Y2gpOw0KPiA+
ICsNCj4gPiArc3RhdGljIHN0cnVjdCBwbGF0Zm9ybV9kcml2ZXIgZnNsX2RjdV9kcm1fcGxhdGZv
cm1fZHJpdmVyID0gew0KPiA+ICsJLnByb2JlCQk9IGZzbF9kY3VfZHJtX3Byb2JlLA0KPiA+ICsJ
LnJlbW92ZQkJPSBmc2xfZGN1X2RybV9yZW1vdmUsDQo+ID4gKwkuZHJpdmVyCQk9IHsNCj4gPiAr
CQkub3duZXIJPSBUSElTX01PRFVMRSwNCj4gPiArCQkubmFtZQk9ICJmc2wsZGN1IiwNCj4gPiAr
CQkucG0JPSAmZnNsX2RjdV9kcm1fcG1fb3BzLA0KPiA+ICsJCS5vZl9tYXRjaF90YWJsZSA9IGZz
bF9kY3Vfb2ZfbWF0Y2gsDQo+ID4gKwl9LA0KPiA+ICt9Ow0KPiA+ICsNCj4gPiArbW9kdWxlX3Bs
YXRmb3JtX2RyaXZlcihmc2xfZGN1X2RybV9wbGF0Zm9ybV9kcml2ZXIpOw0KPiA+ICsNCj4gPiAr
TU9EVUxFX0FMSUFTKCJwbGF0Zm9ybTpmc2wtZGN1LWRybSIpOw0KPiA+ICtNT0RVTEVfREVTQ1JJ
UFRJT04oIkZyZWVzY2FsZSBEQ1UgRFJNIERyaXZlciIpOw0KPiA+ICtNT0RVTEVfTElDRU5TRSgi
R1BMIik7DQo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1f
ZHJ2LmgNCj4gPiBiL2RyaXZlcnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fZHJ2LmgNCj4gPiBu
ZXcgZmlsZSBtb2RlIDEwMDY0NA0KPiA+IGluZGV4IDAwMDAwMDAuLjI3MjI2MTA5DQo+ID4gLS0t
IC9kZXYvbnVsbA0KPiA+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fZHJ2
LmgNCj4gPiBAQCAtMCwwICsxLDIxMCBAQA0KPiA+ICsvKg0KPiA+ICsgKiBDb3B5cmlnaHQgMjAx
NSBGcmVlc2NhbGUgU2VtaWNvbmR1Y3RvciwgSW5jLg0KPiA+ICsgKg0KPiA+ICsgKiBGcmVlc2Nh
bGUgRENVIGRybSBkZXZpY2UgZHJpdmVyDQo+ID4gKyAqDQo+ID4gKyAqIFRoaXMgcHJvZ3JhbSBp
cyBmcmVlIHNvZnR3YXJlOyB5b3UgY2FuIHJlZGlzdHJpYnV0ZSBpdCBhbmQvb3IgbW9kaWZ5DQo+
ID4gKyAqIGl0IHVuZGVyIHRoZSB0ZXJtcyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljIExpY2Vu
c2UgYXMgcHVibGlzaGVkIGJ5DQo+ID4gKyAqIHRoZSBGcmVlIFNvZnR3YXJlIEZvdW5kYXRpb247
IGVpdGhlciB2ZXJzaW9uIDIgb2YgdGhlIExpY2Vuc2UsIG9yDQo+ID4gKyAqIChhdCB5b3VyIG9w
dGlvbikgYW55IGxhdGVyIHZlcnNpb24uDQo+ID4gKyAqLw0KPiA+ICsNCj4gPiArI2lmbmRlZiBf
X0ZTTF9EQ1VfRFJNX0RSVl9IX18NCj4gPiArI2RlZmluZSBfX0ZTTF9EQ1VfRFJNX0RSVl9IX18N
Cj4gPiArDQo+ID4gKyNpbmNsdWRlIDxsaW51eC9rZXJuZWwuaD4NCj4gPiArI2luY2x1ZGUgPGxp
bnV4L3NwaW5sb2NrLmg+DQo+ID4gKyNpbmNsdWRlIDxzdGRkZWYuaD4NCj4gPiArI2luY2x1ZGUg
PGRybS9kcm0uaD4NCj4gPiArI2luY2x1ZGUgPGRybS9kcm1QLmg+DQo+ID4gKyNpbmNsdWRlIDxk
cm0vZHJtX2ZiX2hlbHBlci5oPg0KPiA+ICsjaW5jbHVkZSA8ZHJtL2RybV9jcnRjX2hlbHBlci5o
Pg0KPiA+ICsjaW5jbHVkZSA8ZHJtL2RybV9nZW1fY21hX2hlbHBlci5oPg0KPiA+ICsjaW5jbHVk
ZSA8ZHJtL2RybV9mYl9jbWFfaGVscGVyLmg+DQo+ID4gKw0KPiA+ICsjaW5jbHVkZSAiZnNsX2Rj
dV9kcm1fY3J0Yy5oIg0KPiA+ICsjaW5jbHVkZSAiZnNsX2RjdV9kcm1fcGxhbmUuaCINCj4gPiAr
I2luY2x1ZGUgImZzbF9kY3VfZHJtX2Nvbm5lY3Rvci5oIg0KPiA+ICsjZGVmaW5lIERSSVZFUl9O
QU1FCQkJImZzbC1kY3UtZHJtIg0KPiA+ICsNCj4gPiArI2RlZmluZSBEQ1VfRENVX01PREUJCQkw
eDAwMTANCj4gPiArI2RlZmluZSBEQ1VfTU9ERV9CTEVORF9JVEVSKHgpCQkoKHgpIDw8IDIwKQ0K
PiA+ICsjZGVmaW5lIERDVV9NT0RFX1JBU1RFUl9FTgkJQklUKDE0KQ0KPiA+ICsjZGVmaW5lIERD
VV9NT0RFX0RDVV9NT0RFKHgpCQkoeCkNCj4gPiArI2RlZmluZSBEQ1VfTU9ERV9EQ1VfTU9ERV9N
QVNLCQkweDAzDQo+ID4gKyNkZWZpbmUgRENVX01PREVfT0ZGCQkJMA0KPiA+ICsjZGVmaW5lIERD
VV9NT0RFX05PUk1BTAkJCTENCj4gPiArI2RlZmluZSBEQ1VfTU9ERV9URVNUCQkJMg0KPiA+ICsj
ZGVmaW5lIERDVV9NT0RFX0NPTE9SQkFSCQkzDQo+ID4gKw0KPiA+ICsjZGVmaW5lIERDVV9CR05E
CQkJMHgwMDE0DQo+ID4gKyNkZWZpbmUgRENVX0JHTkRfUih4KQkJCSgoeCkgPDwgMTYpDQo+ID4g
KyNkZWZpbmUgRENVX0JHTkRfRyh4KQkJCSgoeCkgPDwgOCkNCj4gPiArI2RlZmluZSBEQ1VfQkdO
RF9CKHgpCQkJKHgpDQo+ID4gKw0KPiA+ICsjZGVmaW5lIERDVV9ESVNQX1NJWkUJCQkweDAwMTgN
Cj4gPiArI2RlZmluZSBEQ1VfRElTUF9TSVpFX0RFTFRBX1koeCkJKCh4KSA8PCAxNikNCj4gPiAr
LypSZWdpc2l0ZXIgdmFsdWUgMS8xNiBvZiBob3Jpem9udGFsIHJlc29sdXRpb24qLw0KPiA+ICsj
ZGVmaW5lIERDVV9ESVNQX1NJWkVfREVMVEFfWCh4KQkoKHgpID4+IDQpDQo+ID4gKw0KPiA+ICsj
ZGVmaW5lIERDVV9IU1lOX1BBUkEJCQkweDAwMWMNCj4gPiArI2RlZmluZSBEQ1VfSFNZTl9QQVJB
X0JQKHgpCQkoKHgpIDw8IDIyKQ0KPiA+ICsjZGVmaW5lIERDVV9IU1lOX1BBUkFfUFcoeCkJCSgo
eCkgPDwgMTEpDQo+ID4gKyNkZWZpbmUgRENVX0hTWU5fUEFSQV9GUCh4KQkJKHgpDQo+ID4gKw0K
PiA+ICsjZGVmaW5lIERDVV9WU1lOX1BBUkEJCQkweDAwMjANCj4gPiArI2RlZmluZSBEQ1VfVlNZ
Tl9QQVJBX0JQKHgpCQkoKHgpIDw8IDIyKQ0KPiA+ICsjZGVmaW5lIERDVV9WU1lOX1BBUkFfUFco
eCkJCSgoeCkgPDwgMTEpDQo+ID4gKyNkZWZpbmUgRENVX1ZTWU5fUEFSQV9GUCh4KQkJKHgpDQo+
ID4gKw0KPiA+ICsjZGVmaW5lIERDVV9TWU5fUE9MCQkJMHgwMDI0DQo+ID4gKyNkZWZpbmUgRENV
X1NZTl9QT0xfSU5WX1BYQ0tfRkFMTAkoMCA8PCA2KQ0KPiA+ICsjZGVmaW5lIERDVV9TWU5fUE9M
X05FR19SRU1BSU4JCSgwIDw8IDUpDQo+ID4gKyNkZWZpbmUgRENVX1NZTl9QT0xfSU5WX1ZTX0xP
VwkJQklUKDEpDQo+ID4gKyNkZWZpbmUgRENVX1NZTl9QT0xfSU5WX0hTX0xPVwkJQklUKDApDQo+
ID4gKw0KPiA+ICsjZGVmaW5lIERDVV9USFJFU0hPTEQJCQkweDAwMjgNCj4gPiArI2RlZmluZSBE
Q1VfVEhSRVNIT0xEX0xTX0JGX1ZTKHgpCSgoeCkgPDwgMTYpDQo+ID4gKyNkZWZpbmUgRENVX1RI
UkVTSE9MRF9PVVRfQlVGX0hJR0goeCkJKCh4KSA8PCA4KQ0KPiA+ICsjZGVmaW5lIERDVV9USFJF
U0hPTERfT1VUX0JVRl9MT1coeCkJKHgpDQo+ID4gKyNkZWZpbmUgQkZfVlNfVkFMCQkJMHgwMw0K
PiA+ICsjZGVmaW5lIEJVRl9NQVhfVkFMCQkJMHg3OA0KPiA+ICsjZGVmaW5lIEJVRl9NSU5fVkFM
CQkJMHgwYQ0KPiA+ICsNCj4gPiArI2RlZmluZSBEQ1VfSU5UX1NUQVRVUwkJCTB4MDAyQw0KPiA+
ICsjZGVmaW5lIERDVV9JTlRfU1RBVFVTX1ZTWU5DCQlCSVQoMCkNCj4gPiArI2RlZmluZSBEQ1Vf
SU5UX1NUQVRVU19VTkRSVU4JCUJJVCgxKQ0KPiA+ICsjZGVmaW5lIERDVV9JTlRfU1RBVFVTX0xT
QkZWUwkJQklUKDIpDQo+ID4gKyNkZWZpbmUgRENVX0lOVF9TVEFUVVNfVkJMQU5LCQlCSVQoMykN
Cj4gPiArI2RlZmluZSBEQ1VfSU5UX1NUQVRVU19DUkNSRUFEWQkJQklUKDQpDQo+ID4gKyNkZWZp
bmUgRENVX0lOVF9TVEFUVVNfQ1JDT1ZFUkZMT1cJQklUKDUpDQo+ID4gKyNkZWZpbmUgRENVX0lO
VF9TVEFUVVNfUDFGSUZPTE8JCUJJVCg2KQ0KPiA+ICsjZGVmaW5lIERDVV9JTlRfU1RBVFVTX1Ax
RklGT0hJCQlCSVQoNykNCj4gPiArI2RlZmluZSBEQ1VfSU5UX1NUQVRVU19QMkZJRk9MTwkJQklU
KDgpDQo+ID4gKyNkZWZpbmUgRENVX0lOVF9TVEFUVVNfUDJGSUZPSEkJCUJJVCg5KQ0KPiA+ICsj
ZGVmaW5lIERDVV9JTlRfU1RBVFVTX1BST0dFTkQJCUJJVCgxMCkNCj4gPiArI2RlZmluZSBEQ1Vf
SU5UX1NUQVRVU19JUE1FUlJPUgkJQklUKDExKQ0KPiA+ICsjZGVmaW5lIERDVV9JTlRfU1RBVFVT
X0xZUlRSQU5TCQlCSVQoMTIpDQo+ID4gKyNkZWZpbmUgRENVX0lOVF9TVEFUVVNfRE1BVFJBTlMJ
CUJJVCgxNCkNCj4gPiArI2RlZmluZSBEQ1VfSU5UX1NUQVRVU19QM0ZJRk9MTwkJQklUKDE2KQ0K
PiA+ICsjZGVmaW5lIERDVV9JTlRfU1RBVFVTX1AzRklGT0hJCQlCSVQoMTcpDQo+ID4gKyNkZWZp
bmUgRENVX0lOVF9TVEFUVVNfUDRGSUZPTE8JCUJJVCgxOCkNCj4gPiArI2RlZmluZSBEQ1VfSU5U
X1NUQVRVU19QNEZJRk9ISQkJQklUKDE5KQ0KPiA+ICsjZGVmaW5lIERDVV9JTlRfU1RBVFVTX1Ax
RU1QVFkJCUJJVCgyNikNCj4gPiArI2RlZmluZSBEQ1VfSU5UX1NUQVRVU19QMkVNUFRZCQlCSVQo
MjcpDQo+ID4gKyNkZWZpbmUgRENVX0lOVF9TVEFUVVNfUDNFTVBUWQkJQklUKDI4KQ0KPiA+ICsj
ZGVmaW5lIERDVV9JTlRfU1RBVFVTX1A0RU1QVFkJCUJJVCgyOSkNCj4gPiArDQo+ID4gKyNkZWZp
bmUgRENVX0lOVF9NQVNLCQkJMHgwMDMwDQo+ID4gKyNkZWZpbmUgRENVX0lOVF9NQVNLX1ZTWU5D
CQlCSVQoMCkNCj4gPiArI2RlZmluZSBEQ1VfSU5UX01BU0tfVU5EUlVOCQlCSVQoMSkNCj4gPiAr
I2RlZmluZSBEQ1VfSU5UX01BU0tfTFNCRlZTCQlCSVQoMikNCj4gPiArI2RlZmluZSBEQ1VfSU5U
X01BU0tfVkJMQU5LCQlCSVQoMykNCj4gPiArI2RlZmluZSBEQ1VfSU5UX01BU0tfQ1JDUkVBRFkJ
CUJJVCg0KQ0KPiA+ICsjZGVmaW5lIERDVV9JTlRfTUFTS19DUkNPVkVSRkxPVwlCSVQoNSkNCj4g
PiArI2RlZmluZSBEQ1VfSU5UX01BU0tfUDFGSUZPTE8JCUJJVCg2KQ0KPiA+ICsjZGVmaW5lIERD
VV9JTlRfTUFTS19QMUZJRk9ISQkJQklUKDcpDQo+ID4gKyNkZWZpbmUgRENVX0lOVF9NQVNLX1Ay
RklGT0xPCQlCSVQoOCkNCj4gPiArI2RlZmluZSBEQ1VfSU5UX01BU0tfUDJGSUZPSEkJCUJJVCg5
KQ0KPiA+ICsjZGVmaW5lIERDVV9JTlRfTUFTS19QUk9HRU5ECQlCSVQoMTApDQo+ID4gKyNkZWZp
bmUgRENVX0lOVF9NQVNLX0lQTUVSUk9SCQlCSVQoMTEpDQo+ID4gKyNkZWZpbmUgRENVX0lOVF9N
QVNLX0xZUlRSQU5TCQlCSVQoMTIpDQo+ID4gKyNkZWZpbmUgRENVX0lOVF9NQVNLX0RNQVRSQU5T
CQlCSVQoMTQpDQo+ID4gKyNkZWZpbmUgRENVX0lOVF9NQVNLX1AzRklGT0xPCQlCSVQoMTYpDQo+
ID4gKyNkZWZpbmUgRENVX0lOVF9NQVNLX1AzRklGT0hJCQlCSVQoMTcpDQo+ID4gKyNkZWZpbmUg
RENVX0lOVF9NQVNLX1A0RklGT0xPCQlCSVQoMTgpDQo+ID4gKyNkZWZpbmUgRENVX0lOVF9NQVNL
X1A0RklGT0hJCQlCSVQoMTkpDQo+ID4gKyNkZWZpbmUgRENVX0lOVF9NQVNLX1AxRU1QVFkJCUJJ
VCgyNikNCj4gPiArI2RlZmluZSBEQ1VfSU5UX01BU0tfUDJFTVBUWQkJQklUKDI3KQ0KPiA+ICsj
ZGVmaW5lIERDVV9JTlRfTUFTS19QM0VNUFRZCQlCSVQoMjgpDQo+ID4gKyNkZWZpbmUgRENVX0lO
VF9NQVNLX1A0RU1QVFkJCUJJVCgyOSkNCj4gPiArDQo+ID4gKyNkZWZpbmUgRENVX0RJVl9SQVRJ
TwkJCTB4MDA1NA0KPiA+ICsNCj4gPiArI2RlZmluZSBEQ1VfVVBEQVRFX01PREUJCQkweDAwY2MN
Cj4gPiArI2RlZmluZSBEQ1VfVVBEQVRFX01PREVfTU9ERQkJQklUKDMxKQ0KPiA+ICsjZGVmaW5l
IERDVV9VUERBVEVfTU9ERV9SRUFEUkVHCQlCSVQoMzApDQo+ID4gKw0KPiA+ICsjZGVmaW5lIERD
VV9EQ0ZCX01BWAkJCTB4MzAwDQo+ID4gKw0KPiA+ICsjZGVmaW5lIERDVV9DVFJMREVTQ0xOXzEo
eCkJCSgweDIwMCArICh4KSAqIDB4NDApDQo+ID4gKyNkZWZpbmUgRENVX0NUUkxERVNDTE5fMV9I
RUlHSFQoeCkJKCh4KSA8PCAxNikNCj4gPiArI2RlZmluZSBEQ1VfQ1RSTERFU0NMTl8xX1dJRFRI
KHgpCSh4KQ0KPiA+ICsNCj4gPiArI2RlZmluZSBEQ1VfQ1RSTERFU0NMTl8yKHgpCQkoMHgyMDQg
KyAoeCkgKiAweDQwKQ0KPiA+ICsjZGVmaW5lIERDVV9DVFJMREVTQ0xOXzJfUE9TWSh4KQkoKHgp
IDw8IDE2KQ0KPiA+ICsjZGVmaW5lIERDVV9DVFJMREVTQ0xOXzJfUE9TWCh4KQkoeCkNCj4gPiAr
DQo+ID4gKyNkZWZpbmUgRENVX0NUUkxERVNDTE5fMyh4KQkJKDB4MjA4ICsgKHgpICogMHg0MCkN
Cj4gPiArDQo+ID4gKyNkZWZpbmUgRENVX0NUUkxERVNDTE5fNCh4KQkJKDB4MjBjICsgKHgpICog
MHg0MCkNCj4gPiArI2RlZmluZSBEQ1VfQ1RSTERFU0NMTl80X0VOCQlCSVQoMzEpDQo+ID4gKyNk
ZWZpbmUgRENVX0NUUkxERVNDTE5fNF9USUxFX0VOCUJJVCgzMCkNCj4gPiArI2RlZmluZSBEQ1Vf
Q1RSTERFU0NMTl80X0RBVEFfU0VMX0NMVVQJQklUKDI5KQ0KPiA+ICsjZGVmaW5lIERDVV9DVFJM
REVTQ0xOXzRfU0FGRVRZX0VOCUJJVCgyOCkNCj4gPiArI2RlZmluZSBEQ1VfQ1RSTERFU0NMTl80
X1RSQU5TKHgpCSgoeCkgPDwgMjApDQo+ID4gKyNkZWZpbmUgRENVX0NUUkxERVNDTE5fNF9CUFAo
eCkJCSgoeCkgPDwgMTYpDQo+ID4gKyNkZWZpbmUgRENVX0NUUkxERVNDTE5fNF9STEVfRU4JCUJJ
VCgxNSkNCj4gPiArI2RlZmluZSBEQ1VfQ1RSTERFU0NMTl80X0xVT0ZGUyh4KQkoKHgpIDw8IDQp
DQo+ID4gKyNkZWZpbmUgRENVX0NUUkxERVNDTE5fNF9CQl9PTgkJQklUKDIpDQo+ID4gKyNkZWZp
bmUgRENVX0NUUkxERVNDTE5fNF9BQih4KQkJKHgpDQo+ID4gKw0KPiA+ICsjZGVmaW5lIERDVV9D
VFJMREVTQ0xOXzUoeCkJCSgweDIxMCArICh4KSAqIDB4NDApDQo+ID4gKyNkZWZpbmUgRENVX0NU
UkxERVNDTE5fNV9DS01BWF9SKHgpCSgoeCkgPDwgMTYpDQo+ID4gKyNkZWZpbmUgRENVX0NUUkxE
RVNDTE5fNV9DS01BWF9HKHgpCSgoeCkgPDwgOCkNCj4gPiArI2RlZmluZSBEQ1VfQ1RSTERFU0NM
Tl81X0NLTUFYX0IoeCkJKHgpDQo+ID4gKw0KPiA+ICsjZGVmaW5lIERDVV9DVFJMREVTQ0xOXzYo
eCkJCSgweDIxNCArICh4KSAqIDB4NDApDQo+ID4gKyNkZWZpbmUgRENVX0NUUkxERVNDTE5fNl9D
S01JTl9SKHgpCSgoeCkgPDwgMTYpDQo+ID4gKyNkZWZpbmUgRENVX0NUUkxERVNDTE5fNl9DS01J
Tl9HKHgpCSgoeCkgPDwgOCkNCj4gPiArI2RlZmluZSBEQ1VfQ1RSTERFU0NMTl82X0NLTUlOX0Io
eCkJKHgpDQo+ID4gKw0KPiA+ICsjZGVmaW5lIERDVV9DVFJMREVTQ0xOXzcoeCkJCSgweDIxOCAr
ICh4KSAqIDB4NDApDQo+ID4gKyNkZWZpbmUgRENVX0NUUkxERVNDTE5fN19USUxFX1ZFUih4KQko
KHgpIDw8IDE2KQ0KPiA+ICsjZGVmaW5lIERDVV9DVFJMREVTQ0xOXzdfVElMRV9IT1IoeCkJKHgp
DQo+ID4gKw0KPiA+ICsjZGVmaW5lIERDVV9DVFJMREVTQ0xOXzgoeCkJCSgweDIxYyArICh4KSAq
IDB4NDApDQo+ID4gKyNkZWZpbmUgRENVX0NUUkxERVNDTE5fOF9GR19GQ09MT1IoeCkJKHgpDQo+
ID4gKw0KPiA+ICsjZGVmaW5lIERDVV9DVFJMREVTQ0xOXzkoeCkJCSgweDIyMCArICh4KSAqIDB4
NDApDQo+ID4gKyNkZWZpbmUgRENVX0NUUkxERVNDTE5fOV9CR19CQ09MT1IoeCkJKHgpDQo+ID4g
Kw0KPiA+ICsjZGVmaW5lIERDVV9DVFJMREVTQ0xOXzEwKHgpCQkoMHgyMjQgKyAoeCkgKiAweDQw
KQ0KPiA+ICsjZGVmaW5lIERDVV9DVFJMREVTQ0xOXzEwX1BPU1RfU0tJUCh4KQkoKHgpIDw8IDE2
KQ0KPiA+ICsjZGVmaW5lIERDVV9DVFJMREVTQ0xOXzEwX1BSRV9TS0lQKHgpCSh4KQ0KPiA+ICsN
Cj4gPiArI2RlZmluZSBGU0xfRENVX1JHQjU2NQkJCTQNCj4gPiArI2RlZmluZSBGU0xfRENVX1JH
Qjg4OAkJCTUNCj4gPiArI2RlZmluZSBGU0xfRENVX0FSR0I4ODg4CQk2DQo+ID4gKyNkZWZpbmUg
RlNMX0RDVV9BUkdCMTU1NQkJMTENCj4gPiArI2RlZmluZSBGU0xfRENVX0FSR0I0NDQ0CQkxMg0K
PiA+ICsjZGVmaW5lIEZTTF9EQ1VfWVVWNDIyCQkJMTQNCj4gPiArDQo+ID4gKyNkZWZpbmUgVENP
Tl9DVFJMMQkJCTB4MDAwMA0KPiA+ICsjZGVmaW5lIFRDT05fQllQQVNTX0VOQUJMRQkJQklUKDI5
KQ0KPiA+ICsNCj4gPiArI2RlZmluZSBEQkcoZm10LCAuLi4pIERSTV9ERUJVRyhmbXQiXG4iLCAj
I19fVkFfQVJHU19fKQ0KPiA+ICsNCj4gPiArc3RydWN0IGNsazsNCj4gPiArc3RydWN0IGRldmlj
ZTsNCj4gPiArc3RydWN0IGRybV9kZXZpY2U7DQo+ID4gKw0KPiA+ICtzdHJ1Y3QgZnNsX2RjdV9k
cm1fZGV2aWNlIHsNCj4gPiArCXN0cnVjdCBkZXZpY2UgKmRldjsNCj4gPiArCXN0cnVjdCBkZXZp
Y2Vfbm9kZSAqbnA7DQo+ID4gKwlzdHJ1Y3QgcmVnbWFwICpyZWdtYXA7DQo+ID4gKwlzdHJ1Y3Qg
cmVnbWFwICp0Y29uX3JlZ21hcDsNCj4gPiArCXVuc2lnbmVkIGludCBpcnE7DQo+ID4gKwlzdHJ1
Y3QgY2xrICpjbGs7DQo+ID4gKwkvKnByb3RlY3RzIGhhcmR3YXJlIHJlZ2lzdGVyKi8NCj4gPiAr
CXNwaW5sb2NrX3QgaXJxX2xvY2s7DQo+ID4gKwlzdHJ1Y3QgZHJtX2RldmljZSAqZGRldjsNCj4g
PiArCXN0cnVjdCBkcm1fZmJkZXZfY21hICpmYmRldjsNCj4gPiArCXN0cnVjdCBmc2xfZGN1X2Ry
bV9jcnRjIGNydGM7DQo+ID4gKwlzdHJ1Y3QgZHJtX2VuY29kZXIgZW5jb2RlcjsNCj4gPiArCXN0
cnVjdCBmc2xfZGN1X2RybV9jb25uZWN0b3IgY29ubmVjdG9yOw0KPiA+ICt9Ow0KPiA+ICsNCj4g
PiArdm9pZCBmc2xfZGN1X2ZiZGV2X2luaXQoc3RydWN0IGRybV9kZXZpY2UgKmRldik7DQo+ID4g
Kw0KPiA+ICsjZW5kaWYgLyogX19GU0xfRENVX0RSTV9EUlZfSF9fICovDQo+ID4gZGlmZiAtLWdp
dCBhL2RyaXZlcnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fZmJkZXYuYw0KPiA+IGIvZHJpdmVy
cy9ncHUvZHJtL2ZzbC9mc2xfZGN1X2RybV9mYmRldi5jDQo+ID4gbmV3IGZpbGUgbW9kZSAxMDA2
NDQNCj4gPiBpbmRleCAwMDAwMDAwLi5mOGVmMGUxDQo+ID4gLS0tIC9kZXYvbnVsbA0KPiA+ICsr
KyBiL2RyaXZlcnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fZmJkZXYuYw0KPiA+IEBAIC0wLDAg
KzEsMjYgQEANCj4gPiArLyoNCj4gPiArICogQ29weXJpZ2h0IDIwMTUgRnJlZXNjYWxlIFNlbWlj
b25kdWN0b3IsIEluYy4NCj4gPiArICoNCj4gPiArICogVGhpcyBwcm9ncmFtIGlzIGZyZWUgc29m
dHdhcmU7IHlvdSBjYW4gcmVkaXN0cmlidXRlIGl0IGFuZC9vciBtb2RpZnkNCj4gaXQNCj4gPiAr
ICogdW5kZXIgdGhlIHRlcm1zIG9mIHRoZSBHTlUgR2VuZXJhbCBQdWJsaWMgTGljZW5zZSB2ZXJz
aW9uIDIgYXMNCj4gcHVibGlzaGVkIGJ5DQo+ID4gKyAqIHRoZSBGcmVlIFNvZnR3YXJlIEZvdW5k
YXRpb24uDQo+ID4gKyAqDQo+ID4gKyAqIFRoaXMgcHJvZ3JhbSBpcyBkaXN0cmlidXRlZCBpbiB0
aGUgaG9wZSB0aGF0IGl0IHdpbGwgYmUgdXNlZnVsLCBidXQNCj4gV0lUSE9VVA0KPiA+ICsgKiBB
TlkgV0FSUkFOVFk7IHdpdGhvdXQgZXZlbiB0aGUgaW1wbGllZCB3YXJyYW50eSBvZiBNRVJDSEFO
VEFCSUxJVFkNCj4gb3INCj4gPiArICogRklUTkVTUyBGT1IgQSBQQVJUSUNVTEFSIFBVUlBPU0Uu
ICBTZWUgdGhlIEdOVSBHZW5lcmFsIFB1YmxpYw0KPiBMaWNlbnNlIGZvcg0KPiA+ICsgKiBtb3Jl
IGRldGFpbHMuDQo+ID4gKyAqDQo+ID4gKyAqLw0KPiA+ICsNCj4gPiArI2luY2x1ZGUgPGRybS9k
cm1QLmg+DQo+ID4gKyNpbmNsdWRlIDxkcm0vZHJtX2ZiX2NtYV9oZWxwZXIuaD4NCj4gPiArDQo+
ID4gKyNpbmNsdWRlICJmc2xfZGN1X2RybV9kcnYuaCINCj4gPiArDQo+ID4gKy8qIGluaXRpYWxp
emUgZmJkZXYgaGVscGVyICovDQo+ID4gK3ZvaWQgZnNsX2RjdV9mYmRldl9pbml0KHN0cnVjdCBk
cm1fZGV2aWNlICpkZXYpDQo+ID4gK3sNCj4gPiArCXN0cnVjdCBmc2xfZGN1X2RybV9kZXZpY2Ug
KmZzbF9kZXYgPSBkZXZfZ2V0X2RydmRhdGEoZGV2LT5kZXYpOw0KPiA+ICsNCj4gPiArCWZzbF9k
ZXYtPmZiZGV2ID0gZHJtX2ZiZGV2X2NtYV9pbml0KGRldiwgMjQsIDEsIDEpOw0KPiA+ICt9DQo+
ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fa21zLmMNCj4g
PiBiL2RyaXZlcnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fa21zLmMNCj4gPiBuZXcgZmlsZSBt
b2RlIDEwMDY0NA0KPiA+IGluZGV4IDAwMDAwMDAuLjBkZTIxYzYNCj4gPiAtLS0gL2Rldi9udWxs
DQo+ID4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2ZzbC9mc2xfZGN1X2RybV9rbXMuYw0KPiA+IEBA
IC0wLDAgKzEsNDIgQEANCj4gPiArLyoNCj4gPiArICogQ29weXJpZ2h0IDIwMTUgRnJlZXNjYWxl
IFNlbWljb25kdWN0b3IsIEluYy4NCj4gPiArICoNCj4gPiArICogRnJlZXNjYWxlIERDVSBkcm0g
ZGV2aWNlIGRyaXZlcg0KPiA+ICsgKg0KPiA+ICsgKiBUaGlzIHByb2dyYW0gaXMgZnJlZSBzb2Z0
d2FyZTsgeW91IGNhbiByZWRpc3RyaWJ1dGUgaXQgYW5kL29yIG1vZGlmeQ0KPiA+ICsgKiBpdCB1
bmRlciB0aGUgdGVybXMgb2YgdGhlIEdOVSBHZW5lcmFsIFB1YmxpYyBMaWNlbnNlIGFzIHB1Ymxp
c2hlZCBieQ0KPiA+ICsgKiB0aGUgRnJlZSBTb2Z0d2FyZSBGb3VuZGF0aW9uOyBlaXRoZXIgdmVy
c2lvbiAyIG9mIHRoZSBMaWNlbnNlLCBvcg0KPiA+ICsgKiAoYXQgeW91ciBvcHRpb24pIGFueSBs
YXRlciB2ZXJzaW9uLg0KPiA+ICsgKi8NCj4gPiArDQo+ID4gKyNpbmNsdWRlIDxkcm0vZHJtUC5o
Pg0KPiA+ICsjaW5jbHVkZSA8ZHJtL2RybV9hdG9taWNfaGVscGVyLmg+DQo+ID4gKw0KPiA+ICsj
aW5jbHVkZSAiZnNsX2RjdV9kcm1fY3J0Yy5oIg0KPiA+ICsjaW5jbHVkZSAiZnNsX2RjdV9kcm1f
Y29ubmVjdG9yLmgiDQo+ID4gKyNpbmNsdWRlICJmc2xfZGN1X2RybV9kcnYuaCINCj4gPiArDQo+
ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgZHJtX21vZGVfY29uZmlnX2Z1bmNzIGZzbF9kY3VfZHJt
X21vZGVfY29uZmlnX2Z1bmNzDQo+ID0gew0KPiA+ICsJLmZiX2NyZWF0ZSA9IGRybV9mYl9jbWFf
Y3JlYXRlLA0KPiA+ICsJLmF0b21pY19jaGVjayA9IGRybV9hdG9taWNfaGVscGVyX2NoZWNrLA0K
PiA+ICsJLmF0b21pY19jb21taXQgPSBkcm1fYXRvbWljX2hlbHBlcl9jb21taXQsDQo+ID4gK307
DQo+ID4gKw0KPiA+ICtpbnQgZnNsX2RjdV9kcm1fbW9kZXNldF9pbml0KHN0cnVjdCBmc2xfZGN1
X2RybV9kZXZpY2UgKmZzbF9kZXYpDQo+ID4gK3sNCj4gPiArCWRybV9tb2RlX2NvbmZpZ19pbml0
KGZzbF9kZXYtPmRkZXYpOw0KPiA+ICsNCj4gPiArCWZzbF9kZXYtPmRkZXYtPm1vZGVfY29uZmln
Lm1pbl93aWR0aCA9IDA7DQo+ID4gKwlmc2xfZGV2LT5kZGV2LT5tb2RlX2NvbmZpZy5taW5faGVp
Z2h0ID0gMDsNCj4gPiArCWZzbF9kZXYtPmRkZXYtPm1vZGVfY29uZmlnLm1heF93aWR0aCA9IDIw
MzE7DQo+ID4gKwlmc2xfZGV2LT5kZGV2LT5tb2RlX2NvbmZpZy5tYXhfaGVpZ2h0ID0gMjA0NzsN
Cj4gPiArCWZzbF9kZXYtPmRkZXYtPm1vZGVfY29uZmlnLmZ1bmNzID0gJmZzbF9kY3VfZHJtX21v
ZGVfY29uZmlnX2Z1bmNzOw0KPiA+ICsNCj4gPiArCWRybV9rbXNfaGVscGVyX3BvbGxfaW5pdChm
c2xfZGV2LT5kZGV2KTsNCj4gPiArCWZzbF9kY3VfZHJtX2NydGNfY3JlYXRlKGZzbF9kZXYpOw0K
PiA+ICsJZnNsX2RjdV9kcm1fZW5jb2Rlcl9jcmVhdGUoZnNsX2RldiwgJmZzbF9kZXYtPmNydGMp
Ow0KPiA+ICsJZnNsX2RjdV9kcm1fY29ubmVjdG9yX2NyZWF0ZShmc2xfZGV2LCAmZnNsX2Rldi0+
ZW5jb2Rlcik7DQo+ID4gKwlkcm1fbW9kZV9jb25maWdfcmVzZXQoZnNsX2Rldi0+ZGRldik7DQo+
ID4gKw0KPiA+ICsJcmV0dXJuIDA7DQo+ID4gK30NCj4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9n
cHUvZHJtL2ZzbC9mc2xfZGN1X2RybV9rbXMuaA0KPiA+IGIvZHJpdmVycy9ncHUvZHJtL2ZzbC9m
c2xfZGN1X2RybV9rbXMuaA0KPiA+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0DQo+ID4gaW5kZXggMDAw
MDAwMC4uYjliZDI5OQ0KPiA+IC0tLSAvZGV2L251bGwNCj4gPiArKysgYi9kcml2ZXJzL2dwdS9k
cm0vZnNsL2ZzbF9kY3VfZHJtX2ttcy5oDQo+ID4gQEAgLTAsMCArMSwxNyBAQA0KPiA+ICsvKg0K
PiA+ICsgKiBDb3B5cmlnaHQgMjAxNSBGcmVlc2NhbGUgU2VtaWNvbmR1Y3RvciwgSW5jLg0KPiA+
ICsgKg0KPiA+ICsgKiBGcmVlc2NhbGUgRENVIGRybSBkZXZpY2UgZHJpdmVyDQo+ID4gKyAqDQo+
ID4gKyAqIFRoaXMgcHJvZ3JhbSBpcyBmcmVlIHNvZnR3YXJlOyB5b3UgY2FuIHJlZGlzdHJpYnV0
ZSBpdCBhbmQvb3IgbW9kaWZ5DQo+ID4gKyAqIGl0IHVuZGVyIHRoZSB0ZXJtcyBvZiB0aGUgR05V
IEdlbmVyYWwgUHVibGljIExpY2Vuc2UgYXMgcHVibGlzaGVkIGJ5DQo+ID4gKyAqIHRoZSBGcmVl
IFNvZnR3YXJlIEZvdW5kYXRpb247IGVpdGhlciB2ZXJzaW9uIDIgb2YgdGhlIExpY2Vuc2UsIG9y
DQo+ID4gKyAqIChhdCB5b3VyIG9wdGlvbikgYW55IGxhdGVyIHZlcnNpb24uDQo+ID4gKyAqLw0K
PiA+ICsNCj4gPiArI2lmbmRlZiBfX0ZTTF9EQ1VfRFJNX0tNU19IX18NCj4gPiArI2RlZmluZSBf
X0ZTTF9EQ1VfRFJNX0tNU19IX18NCj4gPiArDQo+ID4gK2ludCBmc2xfZGN1X2RybV9tb2Rlc2V0
X2luaXQoc3RydWN0IGZzbF9kY3VfZHJtX2RldmljZSAqZnNsX2Rldik7DQo+ID4gKw0KPiA+ICsj
ZW5kaWYgLyogX19GU0xfRENVX0RSTV9LTVNfSF9fICovDQo+ID4gZGlmZiAtLWdpdCBhL2RyaXZl
cnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fcGxhbmUuYw0KPiA+IGIvZHJpdmVycy9ncHUvZHJt
L2ZzbC9mc2xfZGN1X2RybV9wbGFuZS5jDQo+ID4gbmV3IGZpbGUgbW9kZSAxMDA2NDQNCj4gPiBp
bmRleCAwMDAwMDAwLi42MTQ2ZTgwDQo+ID4gLS0tIC9kZXYvbnVsbA0KPiA+ICsrKyBiL2RyaXZl
cnMvZ3B1L2RybS9mc2wvZnNsX2RjdV9kcm1fcGxhbmUuYw0KPiA+IEBAIC0wLDAgKzEsMTkyIEBA
DQo+ID4gKy8qDQo+ID4gKyAqIENvcHlyaWdodCAyMDE1IEZyZWVzY2FsZSBTZW1pY29uZHVjdG9y
LCBJbmMuDQo+ID4gKyAqDQo+ID4gKyAqIEZyZWVzY2FsZSBEQ1UgZHJtIGRldmljZSBkcml2ZXIN
Cj4gPiArICoNCj4gPiArICogVGhpcyBwcm9ncmFtIGlzIGZyZWUgc29mdHdhcmU7IHlvdSBjYW4g
cmVkaXN0cmlidXRlIGl0IGFuZC9vciBtb2RpZnkNCj4gPiArICogaXQgdW5kZXIgdGhlIHRlcm1z
IG9mIHRoZSBHTlUgR2VuZXJhbCBQdWJsaWMgTGljZW5zZSBhcyBwdWJsaXNoZWQgYnkNCj4gPiAr
ICogdGhlIEZyZWUgU29mdHdhcmUgRm91bmRhdGlvbjsgZWl0aGVyIHZlcnNpb24gMiBvZiB0aGUg
TGljZW5zZSwgb3INCj4gPiArICogKGF0IHlvdXIgb3B0aW9uKSBhbnkgbGF0ZXIgdmVyc2lvbi4N
Cj4gPiArICovDQo+ID4gKw0KPiA+ICsjaW5jbHVkZSA8ZHJtL2RybVAuaD4NCj4gPiArI2luY2x1
ZGUgPGRybS9kcm1fY3J0Yy5oPg0KPiA+ICsjaW5jbHVkZSA8ZHJtL2RybV9jcnRjX2hlbHBlci5o
Pg0KPiA+ICsjaW5jbHVkZSA8ZHJtL2RybV9mYl9jbWFfaGVscGVyLmg+DQo+ID4gKyNpbmNsdWRl
IDxkcm0vZHJtX2dlbV9jbWFfaGVscGVyLmg+DQo+ID4gKyNpbmNsdWRlIDxsaW51eC9yZWdtYXAu
aD4NCj4gPiArI2luY2x1ZGUgPGRybS9kcm1fcGxhbmVfaGVscGVyLmg+DQo+ID4gKyNpbmNsdWRl
IDxkcm0vZHJtX2F0b21pY19oZWxwZXIuaD4NCj4gPiArDQo+ID4gKyNpbmNsdWRlICJmc2xfZGN1
X2RybV9kcnYuaCINCj4gPiArI2luY2x1ZGUgImZzbF9kY3VfZHJtX2ttcy5oIg0KPiA+ICsjaW5j
bHVkZSAiZnNsX2RjdV9kcm1fcGxhbmUuaCINCj4gPiArDQo+ID4gKyNkZWZpbmUgdG9fZnNsX2Rj
dV9wbGFuZShwbGFuZSkgXA0KPiA+ICsJY29udGFpbmVyX29mKHBsYW5lLCBzdHJ1Y3QgZnNsX2Rj
dV9kcm1fcGxhbmUsIHBsYW5lKQ0KPiA+ICsNCj4gPiArc3RhdGljIGludA0KPiA+ICtmc2xfZGN1
X2RybV9wbGFuZV9wcmVwYXJlX2ZiKHN0cnVjdCBkcm1fcGxhbmUgKnBsYW5lLA0KPiA+ICsJCQkg
ICAgIHN0cnVjdCBkcm1fZnJhbWVidWZmZXIgKmZiLA0KPiA+ICsJCQkgICAgIGNvbnN0IHN0cnVj
dCBkcm1fcGxhbmVfc3RhdGUgKm5ld19zdGF0ZSkNCj4gPiArew0KPiA+ICsJcmV0dXJuIDA7DQo+
ID4gK30NCj4gPiArDQo+ID4gK3N0YXRpYyB2b2lkDQo+ID4gK2ZzbF9kY3VfZHJtX3BsYW5lX2Ns
ZWFudXBfZmIoc3RydWN0IGRybV9wbGFuZSAqcGxhbmUsDQo+ID4gKwkJCSAgICAgc3RydWN0IGRy
bV9mcmFtZWJ1ZmZlciAqZmIsDQo+ID4gKwkJCSAgICAgY29uc3Qgc3RydWN0IGRybV9wbGFuZV9z
dGF0ZSAqbmV3X3N0YXRlKQ0KPiA+ICt7DQo+ID4gK30NCj4gPiArDQo+ID4gK3N0YXRpYyBpbnQg
ZnNsX2RjdV9kcm1fcGxhbmVfYXRvbWljX2NoZWNrKHN0cnVjdCBkcm1fcGxhbmUgKnBsYW5lLA0K
PiA+ICsJCQkJCSAgc3RydWN0IGRybV9wbGFuZV9zdGF0ZSAqc3RhdGUpDQo+ID4gK3sNCj4gPiAr
CXJldHVybiAwOw0KPiA+ICt9DQo+ID4gKw0KPiA+ICtzdGF0aWMgdm9pZCBmc2xfZGN1X2RybV9w
bGFuZV9hdG9taWNfZGlzYWJsZShzdHJ1Y3QgZHJtX3BsYW5lICpwbGFuZSwNCj4gPiArCQkJCQkg
ICAgIHN0cnVjdCBkcm1fcGxhbmVfc3RhdGUgKm9sZF9zdGF0ZSkNCj4gPiArew0KPiA+ICt9DQo+
ID4gKw0KPiA+ICt2b2lkIGZzbF9kY3VfZHJtX3BsYW5lX2F0b21pY191cGRhdGUoc3RydWN0IGRy
bV9wbGFuZSAqcGxhbmUsDQo+ID4gKwkJCQkgICAgIHN0cnVjdCBkcm1fcGxhbmVfc3RhdGUgKm9s
ZF9zdGF0ZSkNCj4gPiArew0KPiA+ICsJc3RydWN0IGZzbF9kY3VfZHJtX2RldmljZSAqZnNsX2Rl
diA9IHBsYW5lLT5kZXYtPmRldl9wcml2YXRlOw0KPiA+ICsJc3RydWN0IGRybV9wbGFuZV9zdGF0
ZSAqc3RhdGUgPSBwbGFuZS0+c3RhdGU7DQo+ID4gKwlzdHJ1Y3QgZHJtX2ZyYW1lYnVmZmVyICpm
YiA9IHBsYW5lLT5zdGF0ZS0+ZmI7DQo+ID4gKwl1MzIgaW5kZXgsIGFscGhhLCBicHA7DQo+ID4g
KwlzdHJ1Y3QgZHJtX2dlbV9jbWFfb2JqZWN0ICpnZW07DQo+ID4gKwlzdHJ1Y3QgZnNsX2RjdV9k
cm1fcGxhbmUgKmZzbF9wbGFuZSA9IHRvX2ZzbF9kY3VfcGxhbmUocGxhbmUpOw0KPiA+ICsNCj4g
PiArCWluZGV4ID0gZnNsX3BsYW5lLT5pbmRleDsNCj4gPiArCWdlbSA9IGRybV9mYl9jbWFfZ2V0
X2dlbV9vYmooZmIsIDApOw0KPiA+ICsNCj4gPiArCXN3aXRjaCAoZmItPnBpeGVsX2Zvcm1hdCkg
ew0KPiA+ICsJY2FzZSBEUk1fRk9STUFUX1JHQjU2NToNCj4gPiArCQlicHAgPSBGU0xfRENVX1JH
QjU2NTsNCj4gPiArCQlhbHBoYSA9IDB4ZmY7DQo+ID4gKwkJYnJlYWs7DQo+ID4gKwljYXNlIERS
TV9GT1JNQVRfUkdCODg4Og0KPiA+ICsJCWJwcCA9IEZTTF9EQ1VfUkdCODg4Ow0KPiA+ICsJCWFs
cGhhID0gMHhmZjsNCj4gPiArCQlicmVhazsNCj4gPiArCWNhc2UgRFJNX0ZPUk1BVF9BUkdCODg4
ODoNCj4gPiArCQlicHAgPSBGU0xfRENVX0FSR0I4ODg4Ow0KPiA+ICsJCWFscGhhID0gMHhmZjsN
Cj4gPiArCQlicmVhazsNCj4gPiArCWNhc2UgRFJNX0ZPUk1BVF9CR1JBNDQ0NDoNCj4gPiArCQli
cHAgPSBGU0xfRENVX0FSR0I0NDQ0Ow0KPiA+ICsJCWFscGhhID0gMHhmZjsNCj4gPiArCQlicmVh
azsNCj4gPiArCWNhc2UgRFJNX0ZPUk1BVF9BUkdCMTU1NToNCj4gPiArCQlicHAgPSBGU0xfRENV
X0FSR0IxNTU1Ow0KPiA+ICsJCWFscGhhID0gMHhmZjsNCj4gPiArCQlicmVhazsNCj4gPiArCWNh
c2UgRFJNX0ZPUk1BVF9ZVVY0MjI6DQo+ID4gKwkJYnBwID0gRlNMX0RDVV9ZVVY0MjI7DQo+ID4g
KwkJYWxwaGEgPSAweGZmOw0KPiA+ICsJCWJyZWFrOw0KPiA+ICsJZGVmYXVsdDoNCj4gPiArCQly
ZXR1cm47DQo+ID4gKwl9DQo+ID4gKw0KPiA+ICsJcmVnbWFwX3dyaXRlKGZzbF9kZXYtPnJlZ21h
cCwgRENVX0NUUkxERVNDTE5fMShpbmRleCksDQo+ID4gKwkJICAgICBEQ1VfQ1RSTERFU0NMTl8x
X0hFSUdIVChzdGF0ZS0+Y3J0Y19oKSB8DQo+ID4gKwkJICAgICBEQ1VfQ1RSTERFU0NMTl8xX1dJ
RFRIKHN0YXRlLT5jcnRjX3cpKTsNCj4gPiArCXJlZ21hcF93cml0ZShmc2xfZGV2LT5yZWdtYXAs
IERDVV9DVFJMREVTQ0xOXzIoaW5kZXgpLA0KPiA+ICsJCSAgICAgRENVX0NUUkxERVNDTE5fMl9Q
T1NZKHN0YXRlLT5jcnRjX3kpIHwNCj4gPiArCQkgICAgIERDVV9DVFJMREVTQ0xOXzJfUE9TWChz
dGF0ZS0+Y3J0Y194KSk7DQo+ID4gKwlyZWdtYXBfd3JpdGUoZnNsX2Rldi0+cmVnbWFwLCBEQ1Vf
Q1RSTERFU0NMTl8zKGluZGV4KSwgZ2VtLT5wYWRkcik7DQo+ID4gKwlyZWdtYXBfd3JpdGUoZnNs
X2Rldi0+cmVnbWFwLCBEQ1VfQ1RSTERFU0NMTl80KGluZGV4KSwNCj4gPiArCQkgICAgIERDVV9D
VFJMREVTQ0xOXzRfRU4gfA0KPiA+ICsJCSAgICAgRENVX0NUUkxERVNDTE5fNF9UUkFOUyhhbHBo
YSkgfA0KPiA+ICsJCSAgICAgRENVX0NUUkxERVNDTE5fNF9CUFAoYnBwKSB8DQo+ID4gKwkJICAg
ICBEQ1VfQ1RSTERFU0NMTl80X0FCKDApKTsNCj4gPiArCXJlZ21hcF93cml0ZShmc2xfZGV2LT5y
ZWdtYXAsIERDVV9DVFJMREVTQ0xOXzUoaW5kZXgpLA0KPiA+ICsJCSAgICAgRENVX0NUUkxERVND
TE5fNV9DS01BWF9SKDB4RkYpIHwNCj4gPiArCQkgICAgIERDVV9DVFJMREVTQ0xOXzVfQ0tNQVhf
RygweEZGKSB8DQo+ID4gKwkJICAgICBEQ1VfQ1RSTERFU0NMTl81X0NLTUFYX0IoMHhGRikpOw0K
PiA+ICsJcmVnbWFwX3dyaXRlKGZzbF9kZXYtPnJlZ21hcCwgRENVX0NUUkxERVNDTE5fNihpbmRl
eCksDQo+ID4gKwkJICAgICBEQ1VfQ1RSTERFU0NMTl82X0NLTUlOX1IoMCkgfA0KPiA+ICsJCSAg
ICAgRENVX0NUUkxERVNDTE5fNl9DS01JTl9HKDApIHwNCj4gPiArCQkgICAgIERDVV9DVFJMREVT
Q0xOXzZfQ0tNSU5fQigwKSk7DQo+ID4gKwlyZWdtYXBfd3JpdGUoZnNsX2Rldi0+cmVnbWFwLCBE
Q1VfQ1RSTERFU0NMTl83KGluZGV4KSwgMCk7DQo+ID4gKwlyZWdtYXBfd3JpdGUoZnNsX2Rldi0+
cmVnbWFwLCBEQ1VfQ1RSTERFU0NMTl84KGluZGV4KSwNCj4gPiArCQkgICAgIERDVV9DVFJMREVT
Q0xOXzhfRkdfRkNPTE9SKDApKTsNCj4gPiArCXJlZ21hcF93cml0ZShmc2xfZGV2LT5yZWdtYXAs
IERDVV9DVFJMREVTQ0xOXzkoaW5kZXgpLA0KPiA+ICsJCSAgICAgRENVX0NUUkxERVNDTE5fOV9C
R19CQ09MT1IoMCkpOw0KPiA+ICsJaWYgKG9mX2RldmljZV9pc19jb21wYXRpYmxlKGZzbF9kZXYt
Pm5wLCAiZnNsLGxzMTAyMWEtZGN1IikpDQo+ID4gKwkJcmVnbWFwX3dyaXRlKGZzbF9kZXYtPnJl
Z21hcCwgRENVX0NUUkxERVNDTE5fMTAoaW5kZXgpLA0KPiA+ICsJCQkgICAgIERDVV9DVFJMREVT
Q0xOXzEwX1BPU1RfU0tJUCgwKSB8DQo+ID4gKwkJCSAgICAgRENVX0NUUkxERVNDTE5fMTBfUFJF
X1NLSVAoMCkpOw0KPiA+ICsJcmVnbWFwX3VwZGF0ZV9iaXRzKGZzbF9kZXYtPnJlZ21hcCwgRENV
X0RDVV9NT0RFLA0KPiA+ICsJCQkgICBEQ1VfTU9ERV9EQ1VfTU9ERV9NQVNLLA0KPiA+ICsJCQkg
ICBEQ1VfTU9ERV9EQ1VfTU9ERShEQ1VfTU9ERV9OT1JNQUwpKTsNCj4gPiArCXJlZ21hcF93cml0
ZShmc2xfZGV2LT5yZWdtYXAsIERDVV9VUERBVEVfTU9ERSwNCj4gRENVX1VQREFURV9NT0RFX1JF
QURSRUcpOw0KPiA+ICt9DQo+ID4gKw0KPiA+ICtpbnQgZnNsX2RjdV9kcm1fcGxhbmVfZGlzYWJs
ZShzdHJ1Y3QgZHJtX3BsYW5lICpwbGFuZSkNCj4gPiArew0KPiA+ICsJcmV0dXJuIDA7DQo+ID4g
K30NCj4gPiArDQo+ID4gK3ZvaWQgZnNsX2RjdV9kcm1fcGxhbmVfZGVzdHJveShzdHJ1Y3QgZHJt
X3BsYW5lICpwbGFuZSkNCj4gPiArew0KPiA+ICsJZnNsX2RjdV9kcm1fcGxhbmVfZGlzYWJsZShw
bGFuZSk7DQo+ID4gKwlkcm1fcGxhbmVfY2xlYW51cChwbGFuZSk7DQo+ID4gK30NCj4gPiArDQo+
ID4gK3N0YXRpYyBjb25zdCB1aW50MzJfdCBmc2xfZGN1X2RybV9wbGFuZV9mb3JtYXRzW10gPSB7
DQo+ID4gKwlEUk1fRk9STUFUX1JHQjU2NSwNCj4gPiArCURSTV9GT1JNQVRfUkdCODg4LA0KPiA+
ICsJRFJNX0ZPUk1BVF9BUkdCODg4OCwNCj4gPiArCURSTV9GT1JNQVRfQVJHQjQ0NDQsDQo+ID4g
KwlEUk1fRk9STUFUX0FSR0IxNTU1LA0KPiA+ICsJRFJNX0ZPUk1BVF9ZVVY0MjIsDQo+ID4gK307
DQo+ID4gKw0KPiA+ICtzdGF0aWMgY29uc3Qgc3RydWN0IGRybV9wbGFuZV9mdW5jcyBmc2xfZGN1
X2RybV9wbGFuZV9mdW5jcyA9IHsNCj4gPiArCS51cGRhdGVfcGxhbmUgPSBkcm1fYXRvbWljX2hl
bHBlcl91cGRhdGVfcGxhbmUsDQo+ID4gKwkuZGlzYWJsZV9wbGFuZSA9IGRybV9hdG9taWNfaGVs
cGVyX2Rpc2FibGVfcGxhbmUsDQo+ID4gKwkuZGVzdHJveSA9IGZzbF9kY3VfZHJtX3BsYW5lX2Rl
c3Ryb3ksDQo+ID4gKwkuYXRvbWljX2R1cGxpY2F0ZV9zdGF0ZSA9IGRybV9hdG9taWNfaGVscGVy
X3BsYW5lX2R1cGxpY2F0ZV9zdGF0ZSwNCj4gPiArCS5hdG9taWNfZGVzdHJveV9zdGF0ZSA9IGRy
bV9hdG9taWNfaGVscGVyX3BsYW5lX2Rlc3Ryb3lfc3RhdGUsDQo+ID4gKwkucmVzZXQgPSBkcm1f
YXRvbWljX2hlbHBlcl9wbGFuZV9yZXNldCwNCj4gPiArfTsNCj4gPiArDQo+ID4gK3N0YXRpYyBj
b25zdCBzdHJ1Y3QgZHJtX3BsYW5lX2hlbHBlcl9mdW5jcw0KPiBmc2xfZGN1X2RybV9wbGFuZV9o
ZWxwZXJfZnVuY3MgPSB7DQo+ID4gKwkucHJlcGFyZV9mYiA9IGZzbF9kY3VfZHJtX3BsYW5lX3By
ZXBhcmVfZmIsDQo+ID4gKwkuY2xlYW51cF9mYiA9IGZzbF9kY3VfZHJtX3BsYW5lX2NsZWFudXBf
ZmIsDQo+ID4gKwkuYXRvbWljX2NoZWNrID0gZnNsX2RjdV9kcm1fcGxhbmVfYXRvbWljX2NoZWNr
LA0KPiA+ICsJLmF0b21pY191cGRhdGUgPSBmc2xfZGN1X2RybV9wbGFuZV9hdG9taWNfdXBkYXRl
LA0KPiA+ICsJLmF0b21pY19kaXNhYmxlID0gZnNsX2RjdV9kcm1fcGxhbmVfYXRvbWljX2Rpc2Fi
bGUsDQo+ID4gK307DQo+ID4gKw0KPiA+ICtzdHJ1Y3QgZHJtX3BsYW5lICpmc2xfZGN1X2RybV9w
cmltYXJ5X2NyZWF0ZV9wbGFuZShzdHJ1Y3QgZHJtX2RldmljZQ0KPiAqZGV2KQ0KPiA+ICt7DQo+
ID4gKwlzdHJ1Y3QgZHJtX3BsYW5lICpwcmltYXJ5Ow0KPiA+ICsJaW50IHJldDsNCj4gPiArDQo+
ID4gKwlwcmltYXJ5ID0ga3phbGxvYyhzaXplb2YoKnByaW1hcnkpLCBHRlBfS0VSTkVMKTsNCj4g
PiArCWlmICghcHJpbWFyeSkgew0KPiA+ICsJCURSTV9ERUJVR19LTVMoIkZhaWxlZCB0byBhbGxv
Y2F0ZSBwcmltYXJ5IHBsYW5lXG4iKTsNCj4gPiArCQlyZXR1cm4gTlVMTDsNCj4gPiArCX0NCj4g
PiArDQo+ID4gKwkvKiBwb3NzaWJsZV9jcnRjJ3Mgd2lsbCBiZSBmaWxsZWQgaW4gbGF0ZXIgYnkg
Y3J0Y19pbml0ICovDQo+ID4gKwlyZXQgPSBkcm1fdW5pdmVyc2FsX3BsYW5lX2luaXQoZGV2LCBw
cmltYXJ5LCAwLA0KPiA+ICsJCQkJICAgICAgICZmc2xfZGN1X2RybV9wbGFuZV9mdW5jcywNCj4g
PiArCQkJCSAgICAgICBmc2xfZGN1X2RybV9wbGFuZV9mb3JtYXRzLA0KPiA+ICsJCQkJICAgICAg
IEFSUkFZX1NJWkUoZnNsX2RjdV9kcm1fcGxhbmVfZm9ybWF0cyksDQo+ID4gKwkJCQkgICAgICAg
RFJNX1BMQU5FX1RZUEVfUFJJTUFSWSk7DQo+ID4gKwlpZiAocmV0KSB7DQo+ID4gKwkJa2ZyZWUo
cHJpbWFyeSk7DQo+ID4gKwkJcHJpbWFyeSA9IE5VTEw7DQo+ID4gKwl9DQo+ID4gKwlkcm1fcGxh
bmVfaGVscGVyX2FkZChwcmltYXJ5LCAmZnNsX2RjdV9kcm1fcGxhbmVfaGVscGVyX2Z1bmNzKTsN
Cj4gPiArDQo+ID4gKwlyZXR1cm4gcHJpbWFyeTsNCj4gPiArfQ0KPiA+IGRpZmYgLS1naXQgYS9k
cml2ZXJzL2dwdS9kcm0vZnNsL2ZzbF9kY3VfZHJtX3BsYW5lLmgNCj4gPiBiL2RyaXZlcnMvZ3B1
L2RybS9mc2wvZnNsX2RjdV9kcm1fcGxhbmUuaA0KPiA+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0DQo+
ID4gaW5kZXggMDAwMDAwMC4uY2NiZmE2MQ0KPiA+IC0tLSAvZGV2L251bGwNCj4gPiArKysgYi9k
cml2ZXJzL2dwdS9kcm0vZnNsL2ZzbF9kY3VfZHJtX3BsYW5lLmgNCj4gPiBAQCAtMCwwICsxLDIz
IEBADQo+ID4gKy8qDQo+ID4gKyAqIENvcHlyaWdodCAyMDE1IEZyZWVzY2FsZSBTZW1pY29uZHVj
dG9yLCBJbmMuDQo+ID4gKyAqDQo+ID4gKyAqIEZyZWVzY2FsZSBEQ1UgZHJtIGRldmljZSBkcml2
ZXINCj4gPiArICoNCj4gPiArICogVGhpcyBwcm9ncmFtIGlzIGZyZWUgc29mdHdhcmU7IHlvdSBj
YW4gcmVkaXN0cmlidXRlIGl0IGFuZC9vciBtb2RpZnkNCj4gPiArICogaXQgdW5kZXIgdGhlIHRl
cm1zIG9mIHRoZSBHTlUgR2VuZXJhbCBQdWJsaWMgTGljZW5zZSBhcyBwdWJsaXNoZWQgYnkNCj4g
PiArICogdGhlIEZyZWUgU29mdHdhcmUgRm91bmRhdGlvbjsgZWl0aGVyIHZlcnNpb24gMiBvZiB0
aGUgTGljZW5zZSwgb3INCj4gPiArICogKGF0IHlvdXIgb3B0aW9uKSBhbnkgbGF0ZXIgdmVyc2lv
bi4NCj4gPiArICovDQo+ID4gKw0KPiA+ICsjaWZuZGVmIF9fRlNMX0RDVV9EUk1fUExBTkVfSF9f
DQo+ID4gKyNkZWZpbmUgX19GU0xfRENVX0RSTV9QTEFORV9IX18NCj4gPiArDQo+ID4gK3N0cnVj
dCBmc2xfZGN1X2RybV9kZXZpY2U7DQo+ID4gK3N0cnVjdCBmc2xfZGN1X2RybV9wbGFuZSB7DQo+
ID4gKwlzdHJ1Y3QgZHJtX3BsYW5lIHBsYW5lOw0KPiA+ICsJdW5zaWduZWQgaW50IGluZGV4Ow0K
PiA+ICt9Ow0KPiA+ICsNCj4gPiArc3RydWN0IGRybV9wbGFuZSAqZnNsX2RjdV9kcm1fcHJpbWFy
eV9jcmVhdGVfcGxhbmUoc3RydWN0IGRybV9kZXZpY2UNCj4gKmRldik7DQo+ID4gKw0KPiA+ICsj
ZW5kaWYgLyogX19GU0xfRENVX0RSTV9QTEFORV9IX18gKi8NCg==

From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jianwei.Wang@freescale.com (Jianwei.Wang at freescale.com)
Date: Tue, 7 Apr 2015 06:44:47 +0000
Subject: [PATCH v3 1/4] drm/layerscape: Add Freescale DCU DRM driver
In-Reply-To: <a248211878c93298700ca1e39ab1812b@agner.ch>
References: <1427348225-40731-1-git-send-email-b52261@freescale.com>
 <a248211878c93298700ca1e39ab1812b@agner.ch>
Message-ID: <CY1PR0301MB12268B3F7505EFB85D874B499FFD0@CY1PR0301MB1226.namprd03.prod.outlook.com>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

Hi Stefan,

Thank you for your review and testing on Vybrid F610 device. This driver 
just implement the basic functions and it only support the exported 
framebuffer access. Some DRM interfaces are not implemented now. So your 
test result is normal. I will implement these interfaces with patches soon 
afterwards. I don't plan to add new features for the initial version driver,
otherwise it will be a long term for this version.

I tested on ls1021a using TFT panel, there are no flickers on the screen
when inserting a USB HID device. I will do more test if time permits.

By the way, could please give me some guidance on how X-Server use DRM 
Interface directly? Do you have some papers or webpage about this?

My reply below...

> 
> Hi Jianwei,
> 
> The driver worked on a Vybrid VF610 device using the exported
> framebuffer. However, when using X-Server through the DRM interface
> directly (by using the modesetting driver) I get just a black screen so
> far, still investigating the reason. What user-space interfaces did you
> test?
> 
> When using the FB device and insert a USB HID device, I get some
> flickers on the screen. I didn't had those on the dcufb driver, did you
> notice something like this too? Probably related to the resolution, I'm
> using VGA resolution.
> 
> Some comments below.
> 
> 
> On 2015-03-26 06:37, Jianwei Wang wrote:
> > This patch add support for Two Dimensional Animation and Compositing
> > Engine (2D-ACE) on the Freescale SoCs.
> >
> > 2D-ACE is a Freescale display controller. 2D-ACE describes
> > the functionality of the module extremely well its name is a value
> > that cannot be used as a token in programming languages.
> > Instead the valid token "DCU" is used to tag the register names and
> > function names.
> >
> > The Display Controller Unit (DCU) module is a system master that
> > fetches graphics stored in internal or external memory and displays
> > them on a TFT LCD panel. A wide range of panel sizes is supported
> > and the timing of the interface signals is highly configurable.
> > Graphics are read directly from memory and then blended in real-time,
> > which allows for dynamic content creation with minimal CPU
> > intervention.
> >
> > The features:
> > (1) Full RGB888 output to TFT LCD panel.
> > (2) For the current LCD panel, WQVGA "480x272" is supported.
> > (3) Blending of each pixel using up to 4 source layers
> > dependent on size of panel.
> 
> modetest only shows one layer currently...

Yes, only one plane and one framebuffer were created now, others
maybe create as user requirement or create all when initializing,
I'm not sure now. This describe the hardware feature

> 
> > (4) Each graphic layer can be placed with one pixel resolution
> > in either axis.
> > (5) Each graphic layer support RGB565 and RGB888 direct colors
> > without alpha channel
> > and BGRA8888 direct colors with an alpha channel.
> 
> The array fsl_dcu_drm_plane_formats below shows more formats, does this
> commit log needs updating?
> 

I agree with your suggestion, I will update this commit log

> > (6) Each graphic layer support alpha blending with 8-bit
> > resolution.
> >
> > This is a simplified version, only one primary plane, one
> > framebuffer created for fbdev, one crtc, one connector for
> > TFT LCD panel, an encoder.
> >
> > Signed-off-by: Alison Wang <b18965@freescale.com>
> > Signed-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com>
> > Signed-off-by: Jianwei Wang <b52261@freescale.com>
> > ---
> >
> > Changed in V3:
> >
> > - Test driver on Vybrid board and add compatible string
> > - Remove unused functions
> > - set default crtc for encoder
> > - replace legacy functions with atomic help functions
> > - Set the unique name of the DRM device
> > - Implement irq handle function for vblank interrupt
> >
> > Changed in v2:
> > - Add atomic support
> > - Modify bindings file
> > - Rename node for compatibility
> > - Move platform related code out for compatibility
> >
> >  .../devicetree/bindings/drm/fsl/fsl,dcu.txt        |  50 ++++
> >  drivers/gpu/drm/Kconfig                            |   2 +
> >  drivers/gpu/drm/Makefile                           |   1 +
> >  drivers/gpu/drm/fsl/Kconfig                        |  17 ++
> >  drivers/gpu/drm/fsl/Makefile                       |   8 +
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_connector.c        | 193 ++++++++++++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_connector.h        |  30 ++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.c             | 165 ++++++++++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.h             |  26 ++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c              | 331
> +++++++++++++++++++++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_drv.h              | 210 +++++++++++++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_fbdev.c            |  26 ++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_kms.c              |  42 +++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_kms.h              |  17 ++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_plane.c            | 192 ++++++++++++
> >  drivers/gpu/drm/fsl/fsl_dcu_drm_plane.h            |  23 ++
> >  16 files changed, 1333 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/drm/fsl/fsl,dcu.txt
> >  create mode 100644 drivers/gpu/drm/fsl/Kconfig
> >  create mode 100644 drivers/gpu/drm/fsl/Makefile
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_connector.c
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_connector.h
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.c
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.h
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_drv.h
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_fbdev.c
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_kms.c
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_kms.h
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_plane.c
> >  create mode 100644 drivers/gpu/drm/fsl/fsl_dcu_drm_plane.h
> >
> > diff --git a/Documentation/devicetree/bindings/drm/fsl/fsl,dcu.txt
> > b/Documentation/devicetree/bindings/drm/fsl/fsl,dcu.txt
> > new file mode 100644
> > index 0000000..bdc7d5b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/drm/fsl/fsl,dcu.txt
> > @@ -0,0 +1,50 @@
> > +Device Tree bindings for Freescale DCU DRM Driver
> > +
> > +Required properties:
> > +- compatible:           Should be one of
> > +	* "fsl,ls1021a-dcu".
> > +	* "fsl,vf610-dcu".
> 
> In the Vybrid reference manual, that IP is denoted as "DCU4". Any reason
> why you left out the DCU version? Is this different for LS1021a? On the
> other hand, with the SoC in the name, the IP should be specified clear
> enough.
> 

In the LS1021A reference manual, no DCU version related words. I asked
previous DCU owner, she told me that LS1021A use DCU5 and she also point
out that the same DCU version there may be differences between different 
SoCs. So I named compatible string with SoC name.

> > +- reg:                  Address and length of the register set for dcu.
> > +- clocks:               From common clock binding: handle to dcu clock.
> > +- clock-names:          From common clock binding: Shall be "dcu".
> > +- display:              The phandle to display node.
> > +
> > +Required properties:
> > +- bits-per-pixel:       <16> for RGB565,
> > +			<24> for RGB888,
> > +			<32> for RGB8888.
> > +
> > +Required timing node for dispplay sub-node:
> > +- display-timings:      Refer to binding doc display-timing.txt for
> details.
> > +
> > +Examples:
> > +dcu: dcu at 2ce0000 {
> > +	compatible = "fsl,ls1021a-dcu";
> > +	reg = <0x0 0x2ce0000 0x0 0x10000>;
> > +	clocks = <&platform_clk 0>;
> > +	clock-names = "dcu";
> > +	big-endian;
> > +	display = <&display>;
> > +
> > +	display: display at 0 {
> > +		bits-per-pixel = <24>;
> > +
> > +		display-timings {
> > +			native-mode = <&timing0>;
> > +			timing0: nl4827hc19 {
> > +				clock-frequency = <10870000>;
> > +				hactive = <480>;
> > +				vactive = <272>;
> > +				hback-porch = <2>;
> > +				hfront-porch = <2>;
> > +				vback-porch = <1>;
> > +				vfront-porch = <1>;
> > +				hsync-len = <41>;
> > +				vsync-len = <2>;
> > +				hsync-active = <1>;
> > +				vsync-active = <1>;
> > +			};
> > +		};
> > +	};
> > +};
> > +
> > diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
> > index 151a050..a6957aa 100644
> > --- a/drivers/gpu/drm/Kconfig
> > +++ b/drivers/gpu/drm/Kconfig
> > @@ -199,6 +199,8 @@ source "drivers/gpu/drm/bochs/Kconfig"
> >
> >  source "drivers/gpu/drm/msm/Kconfig"
> >
> > +source "drivers/gpu/drm/fsl/Kconfig"
> > +
> >  source "drivers/gpu/drm/tegra/Kconfig"
> >
> >  source "drivers/gpu/drm/panel/Kconfig"
> > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> > index 2c239b9..ab5b9ef 100644
> > --- a/drivers/gpu/drm/Makefile
> > +++ b/drivers/gpu/drm/Makefile
> > @@ -56,6 +56,7 @@ obj-$(CONFIG_DRM_UDL) += udl/
> >  obj-$(CONFIG_DRM_AST) += ast/
> >  obj-$(CONFIG_DRM_ARMADA) += armada/
> >  obj-$(CONFIG_DRM_ATMEL_HLCDC)	+= atmel-hlcdc/
> > +obj-$(CONFIG_DRM_FSL_DCU) += fsl/
> 
> Hm, I'm wondering whether it would be a good idea to store that driver
> under fsl-dcu/... Any opinion?
> 

I think it is good advice, I'll think about this

> >  obj-$(CONFIG_DRM_RCAR_DU) += rcar-du/
> >  obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
> >  obj-$(CONFIG_DRM_OMAP)	+= omapdrm/
> > diff --git a/drivers/gpu/drm/fsl/Kconfig b/drivers/gpu/drm/fsl/Kconfig
> > new file mode 100644
> > index 0000000..e4f8df0
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/Kconfig
> > @@ -0,0 +1,17 @@
> > +config DRM_FSL_DCU
> > +	tristate "DRM Support for Freescale DCU"
> > +	depends on DRM && OF && ARM
> > +	select DRM_KMS_HELPER
> > +	select DRM_KMS_CMA_HELPER
> > +	select VIDEOMODE_HELPERS
> > +	select BACKLIGHT_CLASS_DEVICE
> > +	select BACKLIGHT_LCD_SUPPORT
> > +	select REGMAP_MMIO
> > +	select DRM_KMS_FB_HELPER
> > +	select FB_SYS_FILLRECT
> > +	select FB_SYS_COPYAREA
> > +	select FB_SYS_IMAGEBLIT
> > +	select FB_SYS_FOPS
> > +	help
> > +	  Choose this option if you have an Freescale DCU chipset.
> > +	  If M is selected the module will be called fsl-dcu-drm.
> > diff --git a/drivers/gpu/drm/fsl/Makefile b/drivers/gpu/drm/fsl/Makefile
> > new file mode 100644
> > index 0000000..5f74aee
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/Makefile
> > @@ -0,0 +1,8 @@
> > +fsl-dcu-drm-y := fsl_dcu_drm_drv.o \
> > +	       fsl_dcu_drm_kms.o \
> > +	       fsl_dcu_drm_connector.o \
> > +	       fsl_dcu_drm_plane.o \
> > +	       fsl_dcu_drm_crtc.o \
> > +	       fsl_dcu_drm_fbdev.o \
> > +
> > +obj-$(CONFIG_DRM_FSL_DCU)	+= fsl-dcu-drm.o
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_connector.c
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_connector.c
> > new file mode 100644
> > index 0000000..4610647
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_connector.c
> > @@ -0,0 +1,193 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#include <linux/backlight.h>
> > +
> > +#include <drm/drmP.h>
> > +#include <drm/drm_atomic_helper.h>
> > +#include <video/of_display_timing.h>
> > +
> > +#include "fsl_dcu_drm_drv.h"
> > +#include "fsl_dcu_drm_connector.h"
> > +
> > +static void fsl_dcu_drm_encoder_dpms(struct drm_encoder *encoder, int
> mode)
> > +{
> > +}
> > +
> > +static void fsl_dcu_drm_encoder_mode_prepare(struct drm_encoder
> *encoder)
> > +{
> > +}
> > +
> > +static void fsl_dcu_drm_encoder_mode_set(struct drm_encoder *encoder,
> > +					 struct drm_display_mode *mode,
> > +					 struct drm_display_mode *adjusted_mode)
> > +{
> > +}
> > +
> > +static void fsl_dcu_drm_encoder_mode_commit(struct drm_encoder *encoder)
> > +{
> > +}
> > +
> > +static void fsl_dcu_drm_encoder_disable(struct drm_encoder *encoder)
> > +{
> > +}
> > +
> > +static int
> > +fsl_dcu_drm_encoder_atomic_check(struct drm_encoder *encoder,
> > +				 struct drm_crtc_state *crtc_state,
> > +				 struct drm_connector_state *conn_state)
> > +{
> > +	return 0;
> > +}
> > +
> > +static void fsl_dcu_drm_encoder_destroy(struct drm_encoder *encoder)
> > +{
> > +	drm_encoder_cleanup(encoder);
> > +}
> > +
> > +static const struct drm_encoder_helper_funcs encoder_helper_funcs = {
> > +	.dpms = fsl_dcu_drm_encoder_dpms,
> > +	.prepare = fsl_dcu_drm_encoder_mode_prepare,
> > +	.commit = fsl_dcu_drm_encoder_mode_commit,
> > +	.mode_set = fsl_dcu_drm_encoder_mode_set,
> > +	.disable = fsl_dcu_drm_encoder_disable,
> > +	.atomic_check = fsl_dcu_drm_encoder_atomic_check,
> > +};
> > +
> > +static const struct drm_encoder_funcs encoder_funcs = {
> > +	.destroy = fsl_dcu_drm_encoder_destroy,
> > +};
> > +
> > +int fsl_dcu_drm_encoder_create(struct fsl_dcu_drm_device *fsl_dev,
> > +			       struct fsl_dcu_drm_crtc *crtc)
> > +{
> > +	struct drm_encoder *encoder = &fsl_dev->encoder;
> > +	int ret;
> > +
> > +	ret = drm_encoder_init(fsl_dev->ddev, encoder, &encoder_funcs,
> > +			       DRM_MODE_ENCODER_LVDS);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	drm_encoder_helper_add(encoder, &encoder_helper_funcs);
> > +	encoder->crtc = &crtc->crtc;
> > +
> > +	return 0;
> > +}
> > +
> > +#define to_fsl_dcu_connector(connector) \
> > +	container_of(connector, struct fsl_dcu_drm_connector, connector)
> > +
> > +static int fsl_dcu_drm_connector_get_modes(struct drm_connector
> *connector)
> > +{
> > +	struct drm_device *dev = connector->dev;
> > +	struct device_node *display_np, *np = dev->dev->of_node;
> > +	struct drm_display_mode *mode = drm_mode_create(connector->dev);
> > +	int num_modes = 0;
> > +
> > +	if (np) {
> > +		display_np = of_parse_phandle(np, "display", 0);
> > +		if (!display_np) {
> > +			dev_err(dev->dev, "failed to find display phandle\n");
> > +			return num_modes;
> > +		}
> > +		of_get_drm_display_mode(display_np, mode, OF_USE_NATIVE_MODE);
> > +		mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
> > +		drm_mode_probed_add(connector, mode);
> > +		num_modes++;
> > +	}
> > +
> > +	return num_modes;
> > +}
> > +
> > +static int fsl_dcu_drm_connector_mode_valid(struct drm_connector
> *connector,
> > +					    struct drm_display_mode *mode)
> > +{
> > +	return MODE_OK;
> > +}
> > +
> > +static struct drm_encoder *
> > +fsl_dcu_drm_connector_best_encoder(struct drm_connector *connector)
> > +{
> > +	struct fsl_dcu_drm_connector *fsl_con =
> to_fsl_dcu_connector(connector);
> > +
> > +	return fsl_con->encoder;
> > +}
> > +
> > +static void fsl_dcu_drm_connector_destroy(struct drm_connector
> *connector)
> > +{
> > +	drm_connector_unregister(connector);
> > +	drm_connector_cleanup(connector);
> > +}
> > +
> > +static enum drm_connector_status
> > +fsl_dcu_drm_connector_detect(struct drm_connector *connector, bool
> force)
> > +{
> > +	return connector_status_connected;
> > +}
> > +
> > +static const struct drm_connector_funcs fsl_dcu_drm_connector_funcs = {
> > +	.dpms = drm_atomic_helper_connector_dpms,
> > +	.reset = drm_atomic_helper_connector_reset,
> > +	.detect = fsl_dcu_drm_connector_detect,
> > +	.fill_modes = drm_helper_probe_single_connector_modes,
> > +	.destroy = fsl_dcu_drm_connector_destroy,
> > +	.atomic_duplicate_state =
> drm_atomic_helper_connector_duplicate_state,
> > +	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> > +};
> > +
> > +static const struct drm_connector_helper_funcs connector_helper_funcs =
> {
> > +	.get_modes = fsl_dcu_drm_connector_get_modes,
> > +	.mode_valid = fsl_dcu_drm_connector_mode_valid,
> > +	.best_encoder = fsl_dcu_drm_connector_best_encoder,
> > +};
> > +
> > +int fsl_dcu_drm_connector_create(struct fsl_dcu_drm_device *fsl_dev,
> > +				 struct drm_encoder *encoder)
> > +{
> > +	struct drm_connector *connector = &fsl_dev->connector.connector;
> > +	int ret;
> > +
> > +	fsl_dev->connector.encoder = encoder;
> > +
> > +	connector->display_info.width_mm = 0;
> > +	connector->display_info.height_mm = 0;
> > +
> > +	ret = drm_connector_init(fsl_dev->ddev, connector,
> > +				 &fsl_dcu_drm_connector_funcs,
> > +				 DRM_MODE_CONNECTOR_LVDS);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	connector->dpms = DRM_MODE_DPMS_OFF;
> > +	drm_connector_helper_add(connector, &connector_helper_funcs);
> > +	ret = drm_connector_register(connector);
> > +	if (ret < 0)
> > +		goto err_cleanup;
> > +
> > +	ret = drm_mode_connector_attach_encoder(connector, encoder);
> > +	if (ret < 0)
> > +		goto err_sysfs;
> > +
> > +	connector->encoder = encoder;
> > +
> > +	drm_object_property_set_value
> > +		(&connector->base, fsl_dev->ddev->mode_config.dpms_property,
> > +		DRM_MODE_DPMS_OFF);
> > +
> > +	return 0;
> > +
> > +err_sysfs:
> > +	drm_connector_unregister(connector);
> > +err_cleanup:
> > +	drm_connector_cleanup(connector);
> > +	return ret;
> > +}
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_connector.h
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_connector.h
> > new file mode 100644
> > index 0000000..bbf6d38
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_connector.h
> > @@ -0,0 +1,30 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#ifndef __FSL_DCU_DRM_CONNECTOR_H__
> > +#define __FSL_DCU_DRM_CONNECTOR_H__
> > +
> > +#include <drm/drmP.h>
> > +#include <drm/drm_crtc.h>
> > +#include "fsl_dcu_drm_crtc.h"
> > +
> > +struct fsl_dcu_drm_device;
> > +struct fsl_dcu_drm_connector {
> > +	struct drm_connector connector;
> > +	struct drm_encoder *encoder;
> > +};
> > +
> > +int fsl_dcu_drm_encoder_create(struct fsl_dcu_drm_device *fsl_dev,
> > +			       struct fsl_dcu_drm_crtc *crtc);
> > +int fsl_dcu_drm_connector_create(struct fsl_dcu_drm_device *fsl_dev,
> > +				 struct drm_encoder *encoder);
> > +
> > +#endif /* __FSL_DCU_DRM_CONNECTOR_H__ */
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.c
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.c
> > new file mode 100644
> > index 0000000..076e273
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.c
> > @@ -0,0 +1,165 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#include <linux/regmap.h>
> > +#include <linux/clk.h>
> > +
> > +#include <drm/drmP.h>
> > +#include <drm/drm_atomic.h>
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_crtc.h>
> > +
> > +#include "fsl_dcu_drm_crtc.h"
> > +#include "fsl_dcu_drm_drv.h"
> > +#include "fsl_dcu_drm_plane.h"
> > +
> > +#define to_fsl_dcu_crtc(c)	container_of(c, struct fsl_dcu_drm_crtc,
> crtc)
> > +
> > +void fsl_dcu_drm_crtc_suspend(struct drm_crtc *crtc)
> > +{
> > +}
> > +
> > +static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
> > +{
> > +	struct drm_device *dev = crtc->dev;
> > +	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
> > +	struct drm_display_mode *mode = &crtc->state->mode;
> > +	uint32_t hbp, hfp, hsw, vbp, vfp, vsw, div, index;
> > +
> > +	DBG(": set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
> > +	    mode->base.id, mode->name,
> > +	    mode->vrefresh, mode->clock,
> > +	    mode->hdisplay, mode->hsync_start,
> > +	    mode->hsync_end, mode->htotal,
> > +	    mode->vdisplay, mode->vsync_start,
> > +	    mode->vsync_end, mode->vtotal,
> > +	    mode->type, mode->flags);
> > +
> > +	index = drm_crtc_index(crtc);
> > +	div = (uint32_t)clk_get_rate(fsl_dev->clk) / mode->clock / 1000;
> > +
> > +	/* Configure timings: */
> > +	hbp = mode->htotal - mode->hsync_end;
> > +	hfp = mode->hsync_start - mode->hdisplay;
> > +	hsw = mode->hsync_end - mode->hsync_start;
> > +	vbp = mode->vtotal - mode->vsync_end;
> > +	vfp = mode->vsync_start - mode->vdisplay;
> > +	vsw = mode->vsync_end - mode->vsync_start;
> > +
> > +	regmap_write(fsl_dev->regmap, DCU_HSYN_PARA,
> > +		     DCU_HSYN_PARA_BP(hbp) |
> > +		     DCU_HSYN_PARA_PW(hsw) |
> > +		     DCU_HSYN_PARA_FP(hfp));
> > +	regmap_write(fsl_dev->regmap, DCU_VSYN_PARA,
> > +		     DCU_VSYN_PARA_BP(vbp) |
> > +		     DCU_VSYN_PARA_PW(vsw) |
> > +		     DCU_VSYN_PARA_FP(vfp));
> > +	regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
> > +		     DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) |
> > +		     DCU_DISP_SIZE_DELTA_X(mode->hdisplay));
> > +	regmap_write(fsl_dev->regmap, DCU_DIV_RATIO, div);
> > +	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
> DCU_UPDATE_MODE_READREG);
> > +}
> > +
> > +static bool fsl_dcu_drm_crtc_mode_fixup(struct drm_crtc *crtc,
> > +					const struct drm_display_mode *mode,
> > +					struct drm_display_mode *adjusted_mode)
> > +{
> > +	return true;
> > +}
> > +
> > +static void fsl_dcu_drm_crtc_prepare(struct drm_crtc *crtc)
> > +{
> > +}
> > +
> > +/* Now enable the clocks, plane, pipe, and connectors that we set up.
> */
> > +static void fsl_dcu_drm_crtc_mode_commit(struct drm_crtc *crtc)
> > +{
> > +}
> > +
> > +static int fsl_dcu_drm_crtc_atomic_check(struct drm_crtc *crtc,
> > +					 struct drm_crtc_state *state)
> > +{
> > +	return 0;
> > +}
> > +
> > +static void fsl_dcu_drm_crtc_atomic_begin(struct drm_crtc *crtc)
> > +{
> > +}
> > +
> > +static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc)
> > +{
> > +}
> > +
> > +static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
> > +{
> > +}
> > +
> > +static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs = {
> > +	.page_flip = drm_atomic_helper_page_flip,
> > +	.set_config = drm_atomic_helper_set_config,
> > +	.destroy = drm_crtc_cleanup,
> > +	.reset = drm_atomic_helper_crtc_reset,
> > +	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
> > +	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
> > +};
> > +
> > +static void fsl_dcu_drm_crtc_dpms(struct drm_crtc *crtc, int mode)
> > +{
> > +}
> > +
> > +static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs
> = {
> > +	.disable = fsl_dcu_drm_disable_crtc,
> > +	.mode_fixup = fsl_dcu_drm_crtc_mode_fixup,
> > +	.mode_set = drm_helper_crtc_mode_set,
> > +	.mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb,
> > +	.mode_set_base = drm_helper_crtc_mode_set_base,
> > +	.prepare = fsl_dcu_drm_crtc_prepare,
> > +	.commit = fsl_dcu_drm_crtc_mode_commit,
> > +	.atomic_check = fsl_dcu_drm_crtc_atomic_check,
> > +	.atomic_begin = fsl_dcu_drm_crtc_atomic_begin,
> > +	.atomic_flush = fsl_dcu_drm_crtc_atomic_flush,
> > +	.dpms = fsl_dcu_drm_crtc_dpms,
> > +};
> > +
> > +int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
> > +{
> > +	struct drm_plane *primary;
> > +	struct drm_crtc *crtc = &fsl_dev->crtc.crtc;
> > +	int ret;
> > +
> > +	fsl_dev->crtc.dpms = DRM_MODE_DPMS_OFF;
> > +
> > +	primary = fsl_dcu_drm_primary_create_plane(fsl_dev->ddev);
> > +	ret = drm_crtc_init_with_planes(fsl_dev->ddev, crtc, primary, NULL,
> > +					&fsl_dcu_drm_crtc_funcs);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs);
> > +
> > +	regmap_write(fsl_dev->regmap, DCU_SYN_POL,
> > +		     DCU_SYN_POL_INV_VS_LOW | DCU_SYN_POL_INV_HS_LOW);
> > +	regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |
> > +		     DCU_BGND_G(0) | DCU_BGND_B(0));
> > +	regmap_write(fsl_dev->regmap, DCU_DCU_MODE,
> > +		     DCU_MODE_BLEND_ITER(1) | DCU_MODE_RASTER_EN);
> > +	regmap_write(fsl_dev->regmap, DCU_THRESHOLD,
> > +		     DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
> > +		     DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
> > +		     DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
> > +	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
> > +			   DCU_MODE_DCU_MODE_MASK,
> > +			   DCU_MODE_DCU_MODE(DCU_MODE_OFF));
> > +	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
> DCU_UPDATE_MODE_READREG);
> > +
> > +	return 0;
> > +}
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.h
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.h
> > new file mode 100644
> > index 0000000..d44b564
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_crtc.h
> > @@ -0,0 +1,26 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#ifndef __FSL_DCU_DRM_CRTC_H__
> > +#define __FSL_DCU_DRM_CRTC_H__
> > +
> > +#include <drm/drmP.h>
> > +#include <drm/drm_crtc.h>
> > +
> > +struct fsl_dcu_drm_device;
> > +struct fsl_dcu_drm_crtc {
> > +	struct drm_crtc crtc;
> > +	int dpms;
> > +};
> > +
> > +int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev);
> > +
> > +#endif /* __FSL_DCU_DRM_CRTC_H__ */
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c
> > new file mode 100644
> > index 0000000..d4a559a
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c
> > @@ -0,0 +1,331 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/io.h>
> > +#include <linux/mm.h>
> > +#include <linux/module.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/regmap.h>
> > +
> > +#include <drm/drmP.h>
> > +#include <linux/fsl/dcu.h>
> 
> This file seems to be missing in that patch.
> 
 
This file in patch 2/4, It's LS1021A platform related code.

> > +
> > +#include "fsl_dcu_drm_drv.h"
> > +#include "fsl_dcu_drm_kms.h"
> > +
> > +static int fsl_dcu_unload(struct drm_device *dev)
> > +{
> > +	drm_mode_config_cleanup(dev);
> > +	drm_vblank_cleanup(dev);
> > +	drm_irq_uninstall(dev);
> > +
> > +	dev->dev_private = NULL;
> > +
> > +	return 0;
> > +}
> > +
> > +static struct regmap_config fsl_dcu_regmap_config = {
> > +	.reg_bits = 32,
> > +	.reg_stride = 4,
> > +	.val_bits = 32,
> > +};
> > +
> > +static int fsl_dcu_bypass_tcon(struct fsl_dcu_drm_device *fsl_dev,
> > +			       struct device_node *np)
> > +{
> > +	struct device_node *tcon_np;
> > +	struct platform_device *pdev;
> > +	struct clk *tcon_clk;
> > +	struct resource *res;
> > +	void __iomem *base;
> > +
> > +	tcon_np = of_parse_phandle(np, "tcon-controller", 0);
> > +	if (!tcon_np)
> > +		return -EINVAL;
> > +
> > +	pdev = of_find_device_by_node(tcon_np);
> > +	if (!pdev)
> > +		return -EINVAL;
> > +
> > +	tcon_clk = devm_clk_get(&pdev->dev, "tcon");
> > +	if (IS_ERR(tcon_clk))
> > +		return PTR_ERR(tcon_clk);
> > +	clk_prepare_enable(tcon_clk);
> 
> You enable the clock explicitly...
> 
> > +
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	if (!res)
> > +		return -ENODEV;
> > +
> > +	base = devm_ioremap_resource(&pdev->dev, res);
> > +	if (IS_ERR(base))
> > +		return PTR_ERR(base);
> > +
> > +	fsl_dev->tcon_regmap = devm_regmap_init_mmio_clk(&pdev->dev,
> > +			"tcon", base, &fsl_dcu_regmap_config);
> 
> And implicitly using regmap. In a short test on Vybrid, the clock is
> actually not needed during operation, hence we could use the explicit
> enabling above, what do you think?
> 
> Also, the clock and tcon in general currently does not get handled by
> suspend/resume code...
> 

OK, I'll update code here

> > +	if (IS_ERR(fsl_dev->tcon_regmap)) {
> > +		dev_err(&pdev->dev, "regmap init failed\n");
> > +		return PTR_ERR(fsl_dev->tcon_regmap);
> > +	}
> > +
> > +	regmap_write(fsl_dev->tcon_regmap, TCON_CTRL1, TCON_BYPASS_ENABLE);
> > +	return 0;
> > +}
> > +
> > +static int fsl_dcu_drm_irq_init(struct drm_device *dev)
> > +{
> > +	struct platform_device *pdev = dev->platformdev;
> > +	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
> > +	unsigned int int_mask;
> > +	int ret;
> > +
> > +	ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
> > +	if (ret < 0)
> > +		dev_err(&pdev->dev, "failed to install IRQ handler\n");
> > +
> > +	dev->irq_enabled = true;
> > +	dev->vblank_disable_allowed = true;
> > +
> > +	regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0);
> > +	regmap_read(fsl_dev->regmap, DCU_INT_MASK, &int_mask);
> > +	regmap_write(fsl_dev->regmap, DCU_INT_MASK, int_mask &
> > +		     ~DCU_INT_MASK_VBLANK);
> > +	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
> DCU_UPDATE_MODE_READREG);
> > +
> > +	return 0;
> > +}
> > +
> > +static int fsl_dcu_load(struct drm_device *dev, unsigned long flags)
> > +{
> > +	struct platform_device *pdev = dev->platformdev;
> > +	struct fsl_dcu_drm_device *fsl_dev;
> > +	struct resource *res;
> > +	void __iomem *base;
> > +	int ret;
> > +
> > +	fsl_dev = devm_kzalloc(&pdev->dev, sizeof(*fsl_dev), GFP_KERNEL);
> > +	if (!fsl_dev)
> > +		return -ENOMEM;
> > +
> > +	fsl_dev->dev = &pdev->dev;
> > +	fsl_dev->ddev = dev;
> > +	fsl_dev->np = pdev->dev.of_node;
> > +	dev->dev_private = fsl_dev;
> > +	drm_dev_set_unique(dev, dev_name(dev->dev));
> > +
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	if (!res) {
> > +		dev_err(&pdev->dev, "could not get memory IO resource\n");
> > +		return -ENODEV;
> > +	}
> > +
> > +	base = devm_ioremap_resource(&pdev->dev, res);
> > +	if (IS_ERR(base)) {
> > +		ret = PTR_ERR(base);
> > +		return ret;
> > +	}
> > +
> > +	fsl_dev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL,
> > +			base, &fsl_dcu_regmap_config);
> > +	if (IS_ERR(fsl_dev->regmap)) {
> > +		dev_err(&pdev->dev, "regmap init failed\n");
> > +		return PTR_ERR(fsl_dev->regmap);
> > +	}
> > +
> > +	/* Put TCON in bypass mode, so the input signals from DCU are passed
> > +	 * through TCON unchanged */
> > +	fsl_dcu_bypass_tcon(fsl_dev, fsl_dev->np);
> > +	fsl_dev->clk = devm_clk_get(&pdev->dev, "dcu");
> > +	if (IS_ERR(fsl_dev->clk)) {
> > +		ret = PTR_ERR(fsl_dev->clk);
> > +		dev_err(&pdev->dev, "could not get clock\n");
> > +		return ret;
> > +	}
> > +	clk_prepare_enable(fsl_dev->clk);
> > +	dev_set_drvdata(dev->dev, fsl_dev);
> > +
> > +	ret = fsl_dcu_drm_modeset_init(fsl_dev);
> > +	if (ret < 0) {
> > +		dev_err(&pdev->dev, "failed to initialize mode setting\n");
> > +		return ret;
> > +	}
> > +
> > +	ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
> > +	if (ret < 0) {
> > +		dev_err(&pdev->dev, "failed to initialize vblank\n");
> > +		goto done;
> > +	}
> > +
> > +	ret = fsl_dcu_drm_irq_init(dev);
> > +	if (ret < 0)
> > +		goto done;
> > +
> > +	fsl_dcu_fbdev_init(dev);
> > +
> > +	return 0;
> > +done:
> > +	if (ret)
> > +		fsl_dcu_unload(dev);
> > +
> > +	return ret;
> > +}
> > +
> > +static void fsl_dcu_drm_preclose(struct drm_device *dev, struct
> drm_file *file)
> > +{
> > +	;
> > +}
> > +
> > +static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg)
> > +{
> > +	struct drm_device *dev = arg;
> > +	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
> > +	unsigned int int_status;
> > +
> > +	regmap_read(fsl_dev->regmap, DCU_INT_STATUS, &int_status);
> > +	if (int_status & DCU_INT_STATUS_VBLANK)
> > +		drm_handle_vblank(dev, 0);
> > +
> > +	regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0xffffffff);
> > +	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
> DCU_UPDATE_MODE_READREG);
> > +
> > +	return IRQ_HANDLED;
> > +}
> > +
> > +static int fsl_dcu_drm_enable_vblank(struct drm_device *dev, int crtc)
> > +{
> > +	return 0;
> > +}
> > +
> > +static void fsl_dcu_drm_disable_vblank(struct drm_device *dev, int crtc)
> > +{
> > +	;
> > +}
> > +
> > +static const struct file_operations fsl_dcu_drm_fops = {
> > +	.owner		= THIS_MODULE,
> > +	.open		= drm_open,
> > +	.release	= drm_release,
> > +	.unlocked_ioctl	= drm_ioctl,
> > +#ifdef CONFIG_COMPAT
> > +	.compat_ioctl	= drm_compat_ioctl,
> > +#endif
> > +	.poll		= drm_poll,
> > +	.read		= drm_read,
> > +	.llseek		= no_llseek,
> > +	.mmap		= drm_gem_cma_mmap,
> > +};
> > +
> > +static struct drm_driver fsl_dcu_drm_driver = {
> > +	.driver_features	= DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET
> > +				| DRIVER_PRIME,
> > +	.load			= fsl_dcu_load,
> > +	.unload			= fsl_dcu_unload,
> > +	.preclose		= fsl_dcu_drm_preclose,
> > +	.irq_handler		= fsl_dcu_drm_irq,
> > +	.get_vblank_counter	= drm_vblank_count,
> > +	.enable_vblank		= fsl_dcu_drm_enable_vblank,
> > +	.disable_vblank		= fsl_dcu_drm_disable_vblank,
> > +	.gem_free_object	= drm_gem_cma_free_object,
> > +	.gem_vm_ops		= &drm_gem_cma_vm_ops,
> > +	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
> > +	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
> > +	.gem_prime_import	= drm_gem_prime_import,
> > +	.gem_prime_export	= drm_gem_prime_export,
> > +	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
> > +	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> > +	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
> > +	.gem_prime_vunmap	= drm_gem_cma_prime_vunmap,
> > +	.gem_prime_mmap		= drm_gem_cma_prime_mmap,
> > +	.dumb_create		= drm_gem_cma_dumb_create,
> > +	.dumb_map_offset	= drm_gem_cma_dumb_map_offset,
> > +	.dumb_destroy		= drm_gem_dumb_destroy,
> > +	.fops			= &fsl_dcu_drm_fops,
> > +	.name			= "fsl-dcu-drm",
> > +	.desc			= "Freescale DCU DRM",
> > +	.date			= "20150213",
> > +	.major			= 1,
> > +	.minor			= 0,
> > +};
> > +
> > +#ifdef CONFIG_PM_SLEEP
> > +static int fsl_dcu_drm_pm_suspend(struct device *dev)
> > +{
> > +	struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
> > +
> > +	if (of_device_is_compatible(fsl_dev->np, "fsl,ls1021a-dcu"))
> > +		dcu_pixclk_disable();
> > +
> > +	drm_kms_helper_poll_disable(fsl_dev->ddev);
> > +	fsl_dcu_drm_crtc_suspend(&fsl_dev->crtc);
> 
> I get
> 
> drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c: In function
> 'fsl_dcu_drm_pm_suspend':
> drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c:270:2: error: implicit declaration
> of function 'fsl_dcu_drm_crtc_suspend'
> [-Werror=implicit-function-declaration]
>   fsl_dcu_drm_crtc_suspend(&fsl_dev->crtc);
>   ^
> drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c: In function
> 'fsl_dcu_drm_pm_resume':
> drivers/gpu/drm/fsl/fsl_dcu_drm_drv.c:280:2: error: implicit declaration
> of function 'fsl_dcu_drm_crtc_resume'
> [-Werror=implicit-function-declaration]
>   fsl_dcu_drm_crtc_resume(&fsl_dev->crtc);
>   ^
> 
> The function fsl_dcu_drm_crtc_suspend seems to be part of
> fsl_dcu_drm_crtc.c, but is empty. While the other is missing
> completely... Please fix/remove as appropriate.
> 

OK, I'll fix it

Regards
Jianwei
> > +
> > +	return 0;
> > +}
> > +
> > +static int fsl_dcu_drm_pm_resume(struct device *dev)
> > +{
> > +	struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
> > +
> > +	drm_modeset_lock_all(fsl_dev->ddev);
> > +	fsl_dcu_drm_crtc_resume(&fsl_dev->crtc);
> > +	drm_modeset_unlock_all(fsl_dev->ddev);
> > +	drm_kms_helper_poll_enable(fsl_dev->ddev);
> > +
> > +	if (of_device_is_compatible(fsl_dev->np, "fsl,ls1021a-dcu"))
> > +		dcu_pixclk_enable();
> > +
> > +	return 0;
> > +}
> > +#endif
> > +
> > +static const struct dev_pm_ops fsl_dcu_drm_pm_ops = {
> > +	SET_SYSTEM_SLEEP_PM_OPS(fsl_dcu_drm_pm_suspend,
> fsl_dcu_drm_pm_resume)
> > +};
> > +
> > +static int fsl_dcu_drm_probe(struct platform_device *pdev)
> > +{
> > +	return drm_platform_init(&fsl_dcu_drm_driver, pdev);
> > +}
> > +
> > +static int fsl_dcu_drm_remove(struct platform_device *pdev)
> > +{
> > +	struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
> > +
> > +	drm_put_dev(fsl_dev->ddev);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct of_device_id fsl_dcu_of_match[] = {
> > +		{ .compatible = "fsl,ls1021a-dcu", },
> > +		{ .compatible = "fsl,vf610-dcu", },
> > +		{ },
> > +};
> > +MODULE_DEVICE_TABLE(of, fsl_dcu_of_match);
> > +
> > +static struct platform_driver fsl_dcu_drm_platform_driver = {
> > +	.probe		= fsl_dcu_drm_probe,
> > +	.remove		= fsl_dcu_drm_remove,
> > +	.driver		= {
> > +		.owner	= THIS_MODULE,
> > +		.name	= "fsl,dcu",
> > +		.pm	= &fsl_dcu_drm_pm_ops,
> > +		.of_match_table = fsl_dcu_of_match,
> > +	},
> > +};
> > +
> > +module_platform_driver(fsl_dcu_drm_platform_driver);
> > +
> > +MODULE_ALIAS("platform:fsl-dcu-drm");
> > +MODULE_DESCRIPTION("Freescale DCU DRM Driver");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_drv.h
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_drv.h
> > new file mode 100644
> > index 0000000..27226109
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_drv.h
> > @@ -0,0 +1,210 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#ifndef __FSL_DCU_DRM_DRV_H__
> > +#define __FSL_DCU_DRM_DRV_H__
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/spinlock.h>
> > +#include <stddef.h>
> > +#include <drm/drm.h>
> > +#include <drm/drmP.h>
> > +#include <drm/drm_fb_helper.h>
> > +#include <drm/drm_crtc_helper.h>
> > +#include <drm/drm_gem_cma_helper.h>
> > +#include <drm/drm_fb_cma_helper.h>
> > +
> > +#include "fsl_dcu_drm_crtc.h"
> > +#include "fsl_dcu_drm_plane.h"
> > +#include "fsl_dcu_drm_connector.h"
> > +#define DRIVER_NAME			"fsl-dcu-drm"
> > +
> > +#define DCU_DCU_MODE			0x0010
> > +#define DCU_MODE_BLEND_ITER(x)		((x) << 20)
> > +#define DCU_MODE_RASTER_EN		BIT(14)
> > +#define DCU_MODE_DCU_MODE(x)		(x)
> > +#define DCU_MODE_DCU_MODE_MASK		0x03
> > +#define DCU_MODE_OFF			0
> > +#define DCU_MODE_NORMAL			1
> > +#define DCU_MODE_TEST			2
> > +#define DCU_MODE_COLORBAR		3
> > +
> > +#define DCU_BGND			0x0014
> > +#define DCU_BGND_R(x)			((x) << 16)
> > +#define DCU_BGND_G(x)			((x) << 8)
> > +#define DCU_BGND_B(x)			(x)
> > +
> > +#define DCU_DISP_SIZE			0x0018
> > +#define DCU_DISP_SIZE_DELTA_Y(x)	((x) << 16)
> > +/*Regisiter value 1/16 of horizontal resolution*/
> > +#define DCU_DISP_SIZE_DELTA_X(x)	((x) >> 4)
> > +
> > +#define DCU_HSYN_PARA			0x001c
> > +#define DCU_HSYN_PARA_BP(x)		((x) << 22)
> > +#define DCU_HSYN_PARA_PW(x)		((x) << 11)
> > +#define DCU_HSYN_PARA_FP(x)		(x)
> > +
> > +#define DCU_VSYN_PARA			0x0020
> > +#define DCU_VSYN_PARA_BP(x)		((x) << 22)
> > +#define DCU_VSYN_PARA_PW(x)		((x) << 11)
> > +#define DCU_VSYN_PARA_FP(x)		(x)
> > +
> > +#define DCU_SYN_POL			0x0024
> > +#define DCU_SYN_POL_INV_PXCK_FALL	(0 << 6)
> > +#define DCU_SYN_POL_NEG_REMAIN		(0 << 5)
> > +#define DCU_SYN_POL_INV_VS_LOW		BIT(1)
> > +#define DCU_SYN_POL_INV_HS_LOW		BIT(0)
> > +
> > +#define DCU_THRESHOLD			0x0028
> > +#define DCU_THRESHOLD_LS_BF_VS(x)	((x) << 16)
> > +#define DCU_THRESHOLD_OUT_BUF_HIGH(x)	((x) << 8)
> > +#define DCU_THRESHOLD_OUT_BUF_LOW(x)	(x)
> > +#define BF_VS_VAL			0x03
> > +#define BUF_MAX_VAL			0x78
> > +#define BUF_MIN_VAL			0x0a
> > +
> > +#define DCU_INT_STATUS			0x002C
> > +#define DCU_INT_STATUS_VSYNC		BIT(0)
> > +#define DCU_INT_STATUS_UNDRUN		BIT(1)
> > +#define DCU_INT_STATUS_LSBFVS		BIT(2)
> > +#define DCU_INT_STATUS_VBLANK		BIT(3)
> > +#define DCU_INT_STATUS_CRCREADY		BIT(4)
> > +#define DCU_INT_STATUS_CRCOVERFLOW	BIT(5)
> > +#define DCU_INT_STATUS_P1FIFOLO		BIT(6)
> > +#define DCU_INT_STATUS_P1FIFOHI		BIT(7)
> > +#define DCU_INT_STATUS_P2FIFOLO		BIT(8)
> > +#define DCU_INT_STATUS_P2FIFOHI		BIT(9)
> > +#define DCU_INT_STATUS_PROGEND		BIT(10)
> > +#define DCU_INT_STATUS_IPMERROR		BIT(11)
> > +#define DCU_INT_STATUS_LYRTRANS		BIT(12)
> > +#define DCU_INT_STATUS_DMATRANS		BIT(14)
> > +#define DCU_INT_STATUS_P3FIFOLO		BIT(16)
> > +#define DCU_INT_STATUS_P3FIFOHI		BIT(17)
> > +#define DCU_INT_STATUS_P4FIFOLO		BIT(18)
> > +#define DCU_INT_STATUS_P4FIFOHI		BIT(19)
> > +#define DCU_INT_STATUS_P1EMPTY		BIT(26)
> > +#define DCU_INT_STATUS_P2EMPTY		BIT(27)
> > +#define DCU_INT_STATUS_P3EMPTY		BIT(28)
> > +#define DCU_INT_STATUS_P4EMPTY		BIT(29)
> > +
> > +#define DCU_INT_MASK			0x0030
> > +#define DCU_INT_MASK_VSYNC		BIT(0)
> > +#define DCU_INT_MASK_UNDRUN		BIT(1)
> > +#define DCU_INT_MASK_LSBFVS		BIT(2)
> > +#define DCU_INT_MASK_VBLANK		BIT(3)
> > +#define DCU_INT_MASK_CRCREADY		BIT(4)
> > +#define DCU_INT_MASK_CRCOVERFLOW	BIT(5)
> > +#define DCU_INT_MASK_P1FIFOLO		BIT(6)
> > +#define DCU_INT_MASK_P1FIFOHI		BIT(7)
> > +#define DCU_INT_MASK_P2FIFOLO		BIT(8)
> > +#define DCU_INT_MASK_P2FIFOHI		BIT(9)
> > +#define DCU_INT_MASK_PROGEND		BIT(10)
> > +#define DCU_INT_MASK_IPMERROR		BIT(11)
> > +#define DCU_INT_MASK_LYRTRANS		BIT(12)
> > +#define DCU_INT_MASK_DMATRANS		BIT(14)
> > +#define DCU_INT_MASK_P3FIFOLO		BIT(16)
> > +#define DCU_INT_MASK_P3FIFOHI		BIT(17)
> > +#define DCU_INT_MASK_P4FIFOLO		BIT(18)
> > +#define DCU_INT_MASK_P4FIFOHI		BIT(19)
> > +#define DCU_INT_MASK_P1EMPTY		BIT(26)
> > +#define DCU_INT_MASK_P2EMPTY		BIT(27)
> > +#define DCU_INT_MASK_P3EMPTY		BIT(28)
> > +#define DCU_INT_MASK_P4EMPTY		BIT(29)
> > +
> > +#define DCU_DIV_RATIO			0x0054
> > +
> > +#define DCU_UPDATE_MODE			0x00cc
> > +#define DCU_UPDATE_MODE_MODE		BIT(31)
> > +#define DCU_UPDATE_MODE_READREG		BIT(30)
> > +
> > +#define DCU_DCFB_MAX			0x300
> > +
> > +#define DCU_CTRLDESCLN_1(x)		(0x200 + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_1_HEIGHT(x)	((x) << 16)
> > +#define DCU_CTRLDESCLN_1_WIDTH(x)	(x)
> > +
> > +#define DCU_CTRLDESCLN_2(x)		(0x204 + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_2_POSY(x)	((x) << 16)
> > +#define DCU_CTRLDESCLN_2_POSX(x)	(x)
> > +
> > +#define DCU_CTRLDESCLN_3(x)		(0x208 + (x) * 0x40)
> > +
> > +#define DCU_CTRLDESCLN_4(x)		(0x20c + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_4_EN		BIT(31)
> > +#define DCU_CTRLDESCLN_4_TILE_EN	BIT(30)
> > +#define DCU_CTRLDESCLN_4_DATA_SEL_CLUT	BIT(29)
> > +#define DCU_CTRLDESCLN_4_SAFETY_EN	BIT(28)
> > +#define DCU_CTRLDESCLN_4_TRANS(x)	((x) << 20)
> > +#define DCU_CTRLDESCLN_4_BPP(x)		((x) << 16)
> > +#define DCU_CTRLDESCLN_4_RLE_EN		BIT(15)
> > +#define DCU_CTRLDESCLN_4_LUOFFS(x)	((x) << 4)
> > +#define DCU_CTRLDESCLN_4_BB_ON		BIT(2)
> > +#define DCU_CTRLDESCLN_4_AB(x)		(x)
> > +
> > +#define DCU_CTRLDESCLN_5(x)		(0x210 + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_5_CKMAX_R(x)	((x) << 16)
> > +#define DCU_CTRLDESCLN_5_CKMAX_G(x)	((x) << 8)
> > +#define DCU_CTRLDESCLN_5_CKMAX_B(x)	(x)
> > +
> > +#define DCU_CTRLDESCLN_6(x)		(0x214 + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_6_CKMIN_R(x)	((x) << 16)
> > +#define DCU_CTRLDESCLN_6_CKMIN_G(x)	((x) << 8)
> > +#define DCU_CTRLDESCLN_6_CKMIN_B(x)	(x)
> > +
> > +#define DCU_CTRLDESCLN_7(x)		(0x218 + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_7_TILE_VER(x)	((x) << 16)
> > +#define DCU_CTRLDESCLN_7_TILE_HOR(x)	(x)
> > +
> > +#define DCU_CTRLDESCLN_8(x)		(0x21c + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_8_FG_FCOLOR(x)	(x)
> > +
> > +#define DCU_CTRLDESCLN_9(x)		(0x220 + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_9_BG_BCOLOR(x)	(x)
> > +
> > +#define DCU_CTRLDESCLN_10(x)		(0x224 + (x) * 0x40)
> > +#define DCU_CTRLDESCLN_10_POST_SKIP(x)	((x) << 16)
> > +#define DCU_CTRLDESCLN_10_PRE_SKIP(x)	(x)
> > +
> > +#define FSL_DCU_RGB565			4
> > +#define FSL_DCU_RGB888			5
> > +#define FSL_DCU_ARGB8888		6
> > +#define FSL_DCU_ARGB1555		11
> > +#define FSL_DCU_ARGB4444		12
> > +#define FSL_DCU_YUV422			14
> > +
> > +#define TCON_CTRL1			0x0000
> > +#define TCON_BYPASS_ENABLE		BIT(29)
> > +
> > +#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
> > +
> > +struct clk;
> > +struct device;
> > +struct drm_device;
> > +
> > +struct fsl_dcu_drm_device {
> > +	struct device *dev;
> > +	struct device_node *np;
> > +	struct regmap *regmap;
> > +	struct regmap *tcon_regmap;
> > +	unsigned int irq;
> > +	struct clk *clk;
> > +	/*protects hardware register*/
> > +	spinlock_t irq_lock;
> > +	struct drm_device *ddev;
> > +	struct drm_fbdev_cma *fbdev;
> > +	struct fsl_dcu_drm_crtc crtc;
> > +	struct drm_encoder encoder;
> > +	struct fsl_dcu_drm_connector connector;
> > +};
> > +
> > +void fsl_dcu_fbdev_init(struct drm_device *dev);
> > +
> > +#endif /* __FSL_DCU_DRM_DRV_H__ */
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_fbdev.c
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_fbdev.c
> > new file mode 100644
> > index 0000000..f8ef0e1
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_fbdev.c
> > @@ -0,0 +1,26 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> it
> > + * under the terms of the GNU General Public License version 2 as
> published by
> > + * the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful, but
> WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> or
> > + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
> License for
> > + * more details.
> > + *
> > + */
> > +
> > +#include <drm/drmP.h>
> > +#include <drm/drm_fb_cma_helper.h>
> > +
> > +#include "fsl_dcu_drm_drv.h"
> > +
> > +/* initialize fbdev helper */
> > +void fsl_dcu_fbdev_init(struct drm_device *dev)
> > +{
> > +	struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev->dev);
> > +
> > +	fsl_dev->fbdev = drm_fbdev_cma_init(dev, 24, 1, 1);
> > +}
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_kms.c
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_kms.c
> > new file mode 100644
> > index 0000000..0de21c6
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_kms.c
> > @@ -0,0 +1,42 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#include <drm/drmP.h>
> > +#include <drm/drm_atomic_helper.h>
> > +
> > +#include "fsl_dcu_drm_crtc.h"
> > +#include "fsl_dcu_drm_connector.h"
> > +#include "fsl_dcu_drm_drv.h"
> > +
> > +static const struct drm_mode_config_funcs fsl_dcu_drm_mode_config_funcs
> = {
> > +	.fb_create = drm_fb_cma_create,
> > +	.atomic_check = drm_atomic_helper_check,
> > +	.atomic_commit = drm_atomic_helper_commit,
> > +};
> > +
> > +int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev)
> > +{
> > +	drm_mode_config_init(fsl_dev->ddev);
> > +
> > +	fsl_dev->ddev->mode_config.min_width = 0;
> > +	fsl_dev->ddev->mode_config.min_height = 0;
> > +	fsl_dev->ddev->mode_config.max_width = 2031;
> > +	fsl_dev->ddev->mode_config.max_height = 2047;
> > +	fsl_dev->ddev->mode_config.funcs = &fsl_dcu_drm_mode_config_funcs;
> > +
> > +	drm_kms_helper_poll_init(fsl_dev->ddev);
> > +	fsl_dcu_drm_crtc_create(fsl_dev);
> > +	fsl_dcu_drm_encoder_create(fsl_dev, &fsl_dev->crtc);
> > +	fsl_dcu_drm_connector_create(fsl_dev, &fsl_dev->encoder);
> > +	drm_mode_config_reset(fsl_dev->ddev);
> > +
> > +	return 0;
> > +}
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_kms.h
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_kms.h
> > new file mode 100644
> > index 0000000..b9bd299
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_kms.h
> > @@ -0,0 +1,17 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#ifndef __FSL_DCU_DRM_KMS_H__
> > +#define __FSL_DCU_DRM_KMS_H__
> > +
> > +int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev);
> > +
> > +#endif /* __FSL_DCU_DRM_KMS_H__ */
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_plane.c
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_plane.c
> > new file mode 100644
> > index 0000000..6146e80
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_plane.c
> > @@ -0,0 +1,192 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#include <drm/drmP.h>
> > +#include <drm/drm_crtc.h>
> > +#include <drm/drm_crtc_helper.h>
> > +#include <drm/drm_fb_cma_helper.h>
> > +#include <drm/drm_gem_cma_helper.h>
> > +#include <linux/regmap.h>
> > +#include <drm/drm_plane_helper.h>
> > +#include <drm/drm_atomic_helper.h>
> > +
> > +#include "fsl_dcu_drm_drv.h"
> > +#include "fsl_dcu_drm_kms.h"
> > +#include "fsl_dcu_drm_plane.h"
> > +
> > +#define to_fsl_dcu_plane(plane) \
> > +	container_of(plane, struct fsl_dcu_drm_plane, plane)
> > +
> > +static int
> > +fsl_dcu_drm_plane_prepare_fb(struct drm_plane *plane,
> > +			     struct drm_framebuffer *fb,
> > +			     const struct drm_plane_state *new_state)
> > +{
> > +	return 0;
> > +}
> > +
> > +static void
> > +fsl_dcu_drm_plane_cleanup_fb(struct drm_plane *plane,
> > +			     struct drm_framebuffer *fb,
> > +			     const struct drm_plane_state *new_state)
> > +{
> > +}
> > +
> > +static int fsl_dcu_drm_plane_atomic_check(struct drm_plane *plane,
> > +					  struct drm_plane_state *state)
> > +{
> > +	return 0;
> > +}
> > +
> > +static void fsl_dcu_drm_plane_atomic_disable(struct drm_plane *plane,
> > +					     struct drm_plane_state *old_state)
> > +{
> > +}
> > +
> > +void fsl_dcu_drm_plane_atomic_update(struct drm_plane *plane,
> > +				     struct drm_plane_state *old_state)
> > +{
> > +	struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private;
> > +	struct drm_plane_state *state = plane->state;
> > +	struct drm_framebuffer *fb = plane->state->fb;
> > +	u32 index, alpha, bpp;
> > +	struct drm_gem_cma_object *gem;
> > +	struct fsl_dcu_drm_plane *fsl_plane = to_fsl_dcu_plane(plane);
> > +
> > +	index = fsl_plane->index;
> > +	gem = drm_fb_cma_get_gem_obj(fb, 0);
> > +
> > +	switch (fb->pixel_format) {
> > +	case DRM_FORMAT_RGB565:
> > +		bpp = FSL_DCU_RGB565;
> > +		alpha = 0xff;
> > +		break;
> > +	case DRM_FORMAT_RGB888:
> > +		bpp = FSL_DCU_RGB888;
> > +		alpha = 0xff;
> > +		break;
> > +	case DRM_FORMAT_ARGB8888:
> > +		bpp = FSL_DCU_ARGB8888;
> > +		alpha = 0xff;
> > +		break;
> > +	case DRM_FORMAT_BGRA4444:
> > +		bpp = FSL_DCU_ARGB4444;
> > +		alpha = 0xff;
> > +		break;
> > +	case DRM_FORMAT_ARGB1555:
> > +		bpp = FSL_DCU_ARGB1555;
> > +		alpha = 0xff;
> > +		break;
> > +	case DRM_FORMAT_YUV422:
> > +		bpp = FSL_DCU_YUV422;
> > +		alpha = 0xff;
> > +		break;
> > +	default:
> > +		return;
> > +	}
> > +
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_1(index),
> > +		     DCU_CTRLDESCLN_1_HEIGHT(state->crtc_h) |
> > +		     DCU_CTRLDESCLN_1_WIDTH(state->crtc_w));
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_2(index),
> > +		     DCU_CTRLDESCLN_2_POSY(state->crtc_y) |
> > +		     DCU_CTRLDESCLN_2_POSX(state->crtc_x));
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_3(index), gem->paddr);
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_4(index),
> > +		     DCU_CTRLDESCLN_4_EN |
> > +		     DCU_CTRLDESCLN_4_TRANS(alpha) |
> > +		     DCU_CTRLDESCLN_4_BPP(bpp) |
> > +		     DCU_CTRLDESCLN_4_AB(0));
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_5(index),
> > +		     DCU_CTRLDESCLN_5_CKMAX_R(0xFF) |
> > +		     DCU_CTRLDESCLN_5_CKMAX_G(0xFF) |
> > +		     DCU_CTRLDESCLN_5_CKMAX_B(0xFF));
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_6(index),
> > +		     DCU_CTRLDESCLN_6_CKMIN_R(0) |
> > +		     DCU_CTRLDESCLN_6_CKMIN_G(0) |
> > +		     DCU_CTRLDESCLN_6_CKMIN_B(0));
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_7(index), 0);
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_8(index),
> > +		     DCU_CTRLDESCLN_8_FG_FCOLOR(0));
> > +	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_9(index),
> > +		     DCU_CTRLDESCLN_9_BG_BCOLOR(0));
> > +	if (of_device_is_compatible(fsl_dev->np, "fsl,ls1021a-dcu"))
> > +		regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN_10(index),
> > +			     DCU_CTRLDESCLN_10_POST_SKIP(0) |
> > +			     DCU_CTRLDESCLN_10_PRE_SKIP(0));
> > +	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
> > +			   DCU_MODE_DCU_MODE_MASK,
> > +			   DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
> > +	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
> DCU_UPDATE_MODE_READREG);
> > +}
> > +
> > +int fsl_dcu_drm_plane_disable(struct drm_plane *plane)
> > +{
> > +	return 0;
> > +}
> > +
> > +void fsl_dcu_drm_plane_destroy(struct drm_plane *plane)
> > +{
> > +	fsl_dcu_drm_plane_disable(plane);
> > +	drm_plane_cleanup(plane);
> > +}
> > +
> > +static const uint32_t fsl_dcu_drm_plane_formats[] = {
> > +	DRM_FORMAT_RGB565,
> > +	DRM_FORMAT_RGB888,
> > +	DRM_FORMAT_ARGB8888,
> > +	DRM_FORMAT_ARGB4444,
> > +	DRM_FORMAT_ARGB1555,
> > +	DRM_FORMAT_YUV422,
> > +};
> > +
> > +static const struct drm_plane_funcs fsl_dcu_drm_plane_funcs = {
> > +	.update_plane = drm_atomic_helper_update_plane,
> > +	.disable_plane = drm_atomic_helper_disable_plane,
> > +	.destroy = fsl_dcu_drm_plane_destroy,
> > +	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
> > +	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
> > +	.reset = drm_atomic_helper_plane_reset,
> > +};
> > +
> > +static const struct drm_plane_helper_funcs
> fsl_dcu_drm_plane_helper_funcs = {
> > +	.prepare_fb = fsl_dcu_drm_plane_prepare_fb,
> > +	.cleanup_fb = fsl_dcu_drm_plane_cleanup_fb,
> > +	.atomic_check = fsl_dcu_drm_plane_atomic_check,
> > +	.atomic_update = fsl_dcu_drm_plane_atomic_update,
> > +	.atomic_disable = fsl_dcu_drm_plane_atomic_disable,
> > +};
> > +
> > +struct drm_plane *fsl_dcu_drm_primary_create_plane(struct drm_device
> *dev)
> > +{
> > +	struct drm_plane *primary;
> > +	int ret;
> > +
> > +	primary = kzalloc(sizeof(*primary), GFP_KERNEL);
> > +	if (!primary) {
> > +		DRM_DEBUG_KMS("Failed to allocate primary plane\n");
> > +		return NULL;
> > +	}
> > +
> > +	/* possible_crtc's will be filled in later by crtc_init */
> > +	ret = drm_universal_plane_init(dev, primary, 0,
> > +				       &fsl_dcu_drm_plane_funcs,
> > +				       fsl_dcu_drm_plane_formats,
> > +				       ARRAY_SIZE(fsl_dcu_drm_plane_formats),
> > +				       DRM_PLANE_TYPE_PRIMARY);
> > +	if (ret) {
> > +		kfree(primary);
> > +		primary = NULL;
> > +	}
> > +	drm_plane_helper_add(primary, &fsl_dcu_drm_plane_helper_funcs);
> > +
> > +	return primary;
> > +}
> > diff --git a/drivers/gpu/drm/fsl/fsl_dcu_drm_plane.h
> > b/drivers/gpu/drm/fsl/fsl_dcu_drm_plane.h
> > new file mode 100644
> > index 0000000..ccbfa61
> > --- /dev/null
> > +++ b/drivers/gpu/drm/fsl/fsl_dcu_drm_plane.h
> > @@ -0,0 +1,23 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * Freescale DCU drm device driver
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#ifndef __FSL_DCU_DRM_PLANE_H__
> > +#define __FSL_DCU_DRM_PLANE_H__
> > +
> > +struct fsl_dcu_drm_device;
> > +struct fsl_dcu_drm_plane {
> > +	struct drm_plane plane;
> > +	unsigned int index;
> > +};
> > +
> > +struct drm_plane *fsl_dcu_drm_primary_create_plane(struct drm_device
> *dev);
> > +
> > +#endif /* __FSL_DCU_DRM_PLANE_H__ */