I'm not sure what the specific features are that are causing issues. FWIW, the first KFDTest unit test that fails has the CPU wait for the GPU to signal 256 events using PM4ReleaseMemory packets. It uses IOMMUv2 for coherent memory access from the GPU. Regards, Felix From: Deucher, Alexander Sent: Monday, August 08, 2016 2:04 PM To: StDenis, Tom; Kuehling, Felix; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Subject: RE: [PATCH 09/14] drm/amd/amdgpu: Enable carrizo GFX PG I'm not sure gfx PG works properly with some of the kfd features. I know there were problems in the past. We probably need to add some sort of handshake for when we have kfd running in order to disable gfx PG when necessary. Alex From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf Of StDenis, Tom Sent: Monday, August 08, 2016 1:59 PM To: Kuehling, Felix; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Subject: Re: [PATCH 09/14] drm/amd/amdgpu: Enable carrizo GFX PG Hi Felix, Hmm, it's unfortunate because I haven't been able to reproduce any hangs on my AM4 based Carrizo. What specific tests are you running when it hangs? Cheers, Tom ________________________________ From: Kuehling, Felix Sent: Monday, August 8, 2016 13:57 To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; StDenis, Tom Subject: Re: [PATCH 09/14] drm/amd/amdgpu: Enable carrizo GFX PG We're reverting this commit on the KFD branch because it's causing hangs on a bunch of HSA compute tests on CZ. Regards, Felix On 16-07-28 10:19 AM, Tom St Denis wrote: > Signed-off-by: Tom St Denis > > --- > drivers/gpu/drm/amd/amdgpu/vi.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c > index 9ba64989f092..4fa9fea541a5 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vi.c > +++ b/drivers/gpu/drm/amd/amdgpu/vi.c > @@ -1578,7 +1578,13 @@ static int vi_common_early_init(void *handle) > AMD_CG_SUPPORT_HDP_LS | > AMD_CG_SUPPORT_SDMA_MGCG | > AMD_CG_SUPPORT_SDMA_LS; > + /* rev0 hardware requires workarounds to support PG */ > adev->pg_flags = 0; > + if (adev->rev_id != 0x00) { > + adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | > + AMD_PG_SUPPORT_GFX_SMG | > + AMD_PG_SUPPORT_GFX_PIPELINE; > + } > adev->external_rev_id = adev->rev_id + 0x1; > break; > case CHIP_STONEY: