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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CY4PR1101MB2166.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 02a8c76a-0a9f-4f97-ef8b-08dab92b458b X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Oct 2022 21:27:52.7721 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: N9IKsTO9ZQysP8Q322Vg6cOOG6BfHg68lBm6My00sRklIPjJt+MU4kZ1pPoyFa/UuQSh9WlMaZCxWjRSVmhoiI7swfJSlFg27RYvFGCqeWk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR11MB6026 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "intel-gfx@lists.freedesktop.org" , "Vivekanandan, Balasubramani" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" > -----Original Message----- > From: Ville Syrj=E4l=E4 > Sent: Friday, October 28, 2022 2:05 AM > To: Srivatsa, Anusha > Cc: intel-gfx@lists.freedesktop.org; Vivekanandan, Balasubramani > > Subject: Re: [PATCH 1/2] drm/i915/display: Do both crawl and squash when > changing cdclk >=20 > On Wed, Oct 26, 2022 at 04:22:56PM -0700, Anusha Srivatsa wrote: > > From: Ville Syrj=E4l=E4 > > > > For MTL, changing cdclk from between certain frequencies has both > > squash and crawl. Use the current cdclk config and the new(desired) > > cdclk config to construtc a mid cdclk config. > > Set the cdclk twice: > > - Current cdclk -> mid cdclk > > - mid cdclk -> desired cdclk > > > > v2: Add check in intel_modeset_calc_cdclk() to avoid cdclk change via > > modeset for platforms that support squash_crawl sequences(Ville) > > > > v3: Add checks for: > > - scenario where only slow clock is used and cdclk is actually 0 > > (bringing up display). > > - PLLs are on before looking up the waveform. > > - Squash and crawl capability checks.(Ville) > > > > v4: Rebase > > - Move checks to be more consistent (Ville) > > - Add comments (Bala) > > > > Cc: Balasubramani Vivekanandan > > > Signed-off-by: Anusha Srivatsa > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/display/intel_cdclk.c | 157 > > +++++++++++++++++---- > > 1 file changed, 129 insertions(+), 28 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > > b/drivers/gpu/drm/i915/display/intel_cdclk.c > > index eada931cb1c8..6a775367f02a 100644 > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > > @@ -1716,37 +1716,74 @@ static void dg2_cdclk_squash_program(struct > drm_i915_private *i915, > > intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl); } > > > > -static void bxt_set_cdclk(struct drm_i915_private *dev_priv, > > - const struct intel_cdclk_config *cdclk_config, > > - enum pipe pipe) > > +static int cdclk_squash_divider(u16 waveform) { > > + return hweight16(waveform ?: 0xffff); } > > + > > +static bool cdclk_crawl_and_squash(struct drm_i915_private *i915, > > + const struct intel_cdclk_config > *old_cdclk_config, > > + const struct intel_cdclk_config > *new_cdclk_config, > > + struct intel_cdclk_config *mid_cdclk_config) > { > > + u16 old_waveform, new_waveform, mid_waveform; > > + int size =3D 16; > > + int div =3D 2; > > + > > + /* Return if both Squash and Crawl are not present */ > > + if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) > > + return false; > > + > > + /* Return if Squash only or Crawl only is the desired action */ > > + if (old_cdclk_config->vco <=3D 0 || new_cdclk_config->vco <=3D 0 || > > + old_cdclk_config->vco =3D=3D new_cdclk_config->vco || > > + old_waveform =3D=3D new_waveform) >=20 > Those are not yet initialized. *facepalm* > > + return false; > > + > > + old_waveform =3D cdclk_squash_waveform(i915, old_cdclk_config- > >cdclk); > > + new_waveform =3D cdclk_squash_waveform(i915, new_cdclk_config- > >cdclk); > > + > > + *mid_cdclk_config =3D *new_cdclk_config; > > + > > + /* Populate the mid_cdclk_config accordingly. > > + * - If moving to a higher cdclk, the desired action is squashing. > > + * The mid cdclk config should have the new (squash) waveform. > > + * - If moving to a lower cdclk, the desired action is crawling. > > + * The mid cdclk config should have the new vco. > > + */ > > + > > + if (cdclk_squash_divider(new_waveform) > > cdclk_squash_divider(old_waveform)) { > > + mid_cdclk_config->vco =3D old_cdclk_config->vco; > > + mid_waveform =3D new_waveform; > > + } else { > > + mid_cdclk_config->vco =3D new_cdclk_config->vco; > > + mid_waveform =3D old_waveform; > > + } > > + > > + mid_cdclk_config->cdclk =3D > DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * > > + mid_cdclk_config->vco, size > * div); > > + > > + /* make sure the mid clock came out sane */ > > + > > + drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk < > > + min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); > > + drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk > > > + i915->display.cdclk.max_cdclk_freq); > > + drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, > mid_cdclk_config->cdclk) !=3D > > + mid_waveform); > > + > > + return true; > > +} > > + > > +static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, > > + const struct intel_cdclk_config *cdclk_config, > > + enum pipe pipe) > > { > > int cdclk =3D cdclk_config->cdclk; > > int vco =3D cdclk_config->vco; > > u32 val; > > u16 waveform; > > int clock; > > - int ret; > > - > > - /* Inform power controller of upcoming frequency change. */ > > - if (DISPLAY_VER(dev_priv) >=3D 11) > > - ret =3D skl_pcode_request(&dev_priv->uncore, > SKL_PCODE_CDCLK_CONTROL, > > - SKL_CDCLK_PREPARE_FOR_CHANGE, > > - SKL_CDCLK_READY_FOR_CHANGE, > > - SKL_CDCLK_READY_FOR_CHANGE, 3); > > - else > > - /* > > - * BSpec requires us to wait up to 150usec, but that leads to > > - * timeouts; the 2ms used here is based on experiment. > > - */ > > - ret =3D snb_pcode_write_timeout(&dev_priv->uncore, > > - > HSW_PCODE_DE_WRITE_FREQ_REQ, > > - 0x80000000, 150, 2); > > - if (ret) { > > - drm_err(&dev_priv->drm, > > - "Failed to inform PCU about cdclk change (err %d, > freq %d)\n", > > - ret, cdclk); > > - return; > > - } > > > > if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > > 0 && vco > 0) { > > if (dev_priv->display.cdclk.hw.vco !=3D vco) @@ -1781,6 > +1818,44 @@ > > static void bxt_set_cdclk(struct drm_i915_private *dev_priv, > > > > if (pipe !=3D INVALID_PIPE) > > > intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, > > pipe)); > > +} > > + > > +static void bxt_set_cdclk(struct drm_i915_private *dev_priv, > > + const struct intel_cdclk_config *cdclk_config, > > + enum pipe pipe) > > +{ > > + struct intel_cdclk_config mid_cdclk_config; > > + int cdclk =3D cdclk_config->cdclk; > > + int ret; > > + > > + /* Inform power controller of upcoming frequency change. */ > > + if (DISPLAY_VER(dev_priv) >=3D 11) > > + ret =3D skl_pcode_request(&dev_priv->uncore, > SKL_PCODE_CDCLK_CONTROL, > > + SKL_CDCLK_PREPARE_FOR_CHANGE, > > + SKL_CDCLK_READY_FOR_CHANGE, > > + SKL_CDCLK_READY_FOR_CHANGE, 3); > > + else > > + /* > > + * BSpec requires us to wait up to 150usec, but that leads to > > + * timeouts; the 2ms used here is based on experiment. > > + */ > > + ret =3D snb_pcode_write_timeout(&dev_priv->uncore, > > + > HSW_PCODE_DE_WRITE_FREQ_REQ, > > + 0x80000000, 150, 2); > > + if (ret) { > > + drm_err(&dev_priv->drm, > > + "Failed to inform PCU about cdclk change (err %d, > freq %d)\n", > > + ret, cdclk); > > + return; > > + } > > + > > + if (cdclk_crawl_and_squash(dev_priv, &dev_priv->display.cdclk.hw, > > + cdclk_config, &mid_cdclk_config)) { > > + _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe); > > + _bxt_set_cdclk(dev_priv, cdclk_config, pipe); > > + } else { > > + _bxt_set_cdclk(dev_priv, cdclk_config, pipe); > > + } > > > > if (DISPLAY_VER(dev_priv) >=3D 11) { > > ret =3D snb_pcode_write(&dev_priv->uncore, > SKL_PCODE_CDCLK_CONTROL, > > @@ -1953,6 +2028,27 @@ void intel_cdclk_uninit_hw(struct > drm_i915_private *i915) > > skl_cdclk_uninit_hw(i915); > > } > > > > +static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private > *i915, > > + const struct intel_cdclk_config *a, > > + const struct intel_cdclk_config *b) { > > + u16 old_waveform; > > + u16 new_waveform; > > + > > + if (a->vco =3D=3D 0 || b->vco =3D=3D 0) > > + return false; > > + > > + if (HAS_CDCLK_CRAWL(i915) && HAS_CDCLK_SQUASH(i915)) { > > + old_waveform =3D cdclk_squash_waveform(i915, a->cdclk); > > + new_waveform =3D cdclk_squash_waveform(i915, b->cdclk); > > + } else { > > + return false; > > + } >=20 > Still weird. Agreed. Changing this. Anusha=20 > > + > > + return a->vco !=3D b->vco && > > + old_waveform !=3D new_waveform; } > > + > > static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, > > const struct intel_cdclk_config *a, > > const struct intel_cdclk_config *b) @@ - > 2759,9 +2855,14 @@ int > > intel_modeset_calc_cdclk(struct intel_atomic_state *state) > > pipe =3D INVALID_PIPE; > > } > > > > - if (intel_cdclk_can_squash(dev_priv, > > - &old_cdclk_state->actual, > > - &new_cdclk_state->actual)) { > > + if (intel_cdclk_can_crawl_and_squash(dev_priv, > > + &old_cdclk_state->actual, > > + &new_cdclk_state->actual)) { > > + drm_dbg_kms(&dev_priv->drm, > > + "Can change cdclk via crawling and squashing\n"); > > + } else if (intel_cdclk_can_squash(dev_priv, > > + &old_cdclk_state->actual, > > + &new_cdclk_state->actual)) { > > drm_dbg_kms(&dev_priv->drm, > > "Can change cdclk via squashing\n"); > > } else if (intel_cdclk_can_crawl(dev_priv, > > -- > > 2.25.1 >=20 > -- > Ville Syrj=E4l=E4 > Intel