From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jiang, Sonny" Subject: Re: [PATCH v2] drm/amdgpu: update documentation for amdgpu_drv.c Date: Wed, 4 Jul 2018 16:12:05 +0000 Message-ID: References: <1530648395-17495-1-git-send-email-sonny.jiang@amd.com>, <5B3C539D.9020208@amd.com>, , Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1056686414==" Return-path: In-Reply-To: Content-Language: en-US List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: "Deucher, Alexander" , "Qu, Jim" , "Zhang, Jerry" , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" --===============1056686414== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_CY4PR12MB15115A371542EB485B6BADA7FD410CY4PR12MB1511namp_" --_000_CY4PR12MB15115A371542EB485B6BADA7FD410CY4PR12MB1511namp_ Content-Type: text/plain; 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Hi Alex,


IP blocks indexes are not fixed. = What's your idea to list them? By asic family?


enum amd_ip_block_type {
        AMD_IP_BLOCK_TYPE_COMMON,
        AMD_IP_BLOCK_TYPE_GMC,
        AMD_IP_BLOCK_TYPE_IH,
        AMD_IP_BLOCK_TYPE_SMC,
        AMD_IP_BLOCK_TYPE_PSP,
        AMD_IP_BLOCK_TYPE_DCE,
        AMD_IP_BLOCK_TYPE_GFX,
        AMD_IP_BLOCK_TYPE_SDMA,
        AMD_IP_BLOCK_TYPE_UVD,
        AMD_IP_BLOCK_TYPE_VCE,
        AMD_IP_BLOCK_TYPE_ACP,
        AMD_IP_BLOCK_TYPE_VCN
};

Thanks,

Sonny


From: Deucher, Alexander Sent: Wednesday, July 4, 2018 2:49:17 AM
To: Qu, Jim; Zhang, Jerry; Jiang, Sonny; amd-gfx-PD4FTy7X32lNgt0PjOBp93rCq3LdnpKM@public.gmane.org= rg
Subject: Re: [PATCH v2] drm/amdgpu: update documentation for amdgpu_= drv.c
 

yeah, that's a good idea.


Alex
From: amd-gfx <amd-gfx= -bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Qu, Jim <Jim.Qu-5C7GfCeVMHo@public.gmane.org&= gt;
Sent: Wednesday, July 4, 2018 1:14 AM
To: Zhang, Jerry; Jiang, Sonny; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: =B4=F0=B8=B4: [PATCH v2] drm/amdgpu: update documentation f= or amdgpu_drv.c
 
I always confuse any bits definiation about some= feature mask. such as ip_block_mask, pg_mask, cg_mask, pp_feature_mask. I = think other people who is not familiar with amdgpu driver may have the same= problem.

So, is it possible to detail every bit mask of features?

Thanks
JimQu

________________________________________
=B7=A2=BC=FE=C8=CB: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> = =B4=FA=B1=ED Zhang, Jerry (Junwei) <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
=B7=A2=CB=CD=CA=B1=BC=E4: 2018=C4=EA7=D4=C24=C8=D5 12:57:01
=CA=D5=BC=FE=C8=CB: Jiang, Sonny; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
=D6=F7=CC=E2: Re: [PATCH v2] drm/amdgpu: update documentation for amdgpu_dr= v.c

On 07/04/2018 04:06 AM, Sonny Jiang wrote:
> Signed-off-by: Sonny Jiang <sonny.jiang-5C7GfCeVMHo@public.gmane.org>
Acked-by: Junwei Zhang <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>

> ---
>   Documentation/gpu/amdgpu.rst     =        |   7 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 222 ++&#= 43;++++++++++++++&#= 43;+++++++++++++-
>   2 files changed, 222 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.r= st
> index 765c2a3..a740e49 100644
> --- a/Documentation/gpu/amdgpu.rst
> +++ b/Documentation/gpu/amdgpu.rst
> @@ -5,6 +5,13 @@
>   The drm/amdgpu driver supports all AMD Radeon GPUs based o= n the Graphics Core
>   Next (GCN) architecture.
>
> +Module Parameters
> +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> +
> +The amdgpu driver supports the following module parameters:
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +
>   Core Driver Infrastructure
>   =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm= /amd/amdgpu/amdgpu_drv.c
> index 963578c..caf81ce 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1,10 +1,3 @@
> -/**
> - * \file amdgpu_drv.c
> - * AMD Amdgpu driver
> - *
> - * \author Gareth Hughes <gareth-jCdQPDEk3idBDgjK7y7TUQ@public.gmane.org>
> - */
> -
>   /*
>    * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, = California.
>    * All Rights Reserved.
> @@ -136,102 +129,235 @@ int amdgpu_gpu_recovery =3D -1; /* auto */=
>   int amdgpu_emu_mode =3D 0;
>   uint amdgpu_smu_memory_pool_size =3D 0;
>
> +/**
> + * DOC: vramlimit (int)
> + * Restrict the total amount of VRAM in MiB for testing.  Th= e default is 0 (Use full VRAM).
> + */
>   MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testin= g, in megabytes");
>   module_param_named(vramlimit, amdgpu_vram_limit, int, 0600= );
>
> +/**
> + * DOC: vis_vramlimit (int)
> + * Restrict the amount of CPU visible VRAM in MiB for testing.&nb= sp; The default is 0 (Use full CPU visible VRAM).
> + */
>   MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRA= M for testing, in megabytes");
>   module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, i= nt, 0444);
>
> +/**
> + * DOC: gartsize (uint)
> + * Restrict the size of GART in Mib (32, 64, etc.) for testing. T= he default is -1 (The size depends on asic).
> + */
>   MODULE_PARM_DESC(gartsize, "Size of GART to setup in = megabytes (32, 64, etc., -1=3Dauto)");
>   module_param_named(gartsize, amdgpu_gart_size, uint, 0600)= ;
>
> +/**
> + * DOC: gttsize (int)
> + * Restrict the size of GTT domain in MiB for testing. The defaul= t is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
> + * otherwise 3/4 RAM size).
> + */
>   MODULE_PARM_DESC(gttsize, "Size of the GTT domain in = megabytes (-1 =3D auto)");
>   module_param_named(gttsize, amdgpu_gtt_size, int, 0600); >
> +/**
> + * DOC: moverate (int)
> + * Set maximum buffer migration rate in MB/s. The default is -1 (= 8 MB/s).
> + */
>   MODULE_PARM_DESC(moverate, "Maximum buffer migration = rate in MB/s. (32, 64, etc., -1=3Dauto, 0=3D1=3Ddisabled)");
>   module_param_named(moverate, amdgpu_moverate, int, 0600);<= br> >
> +/**
> + * DOC: benchmark (int)
> + * Run benchmarks. The default is 0 (Skip benchmarks).
> + */
>   MODULE_PARM_DESC(benchmark, "Run benchmark"); >   module_param_named(benchmark, amdgpu_benchmarking, int, 04= 44);
>
> +/**
> + * DOC: test (int)
> + * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default = is 0 (Skip test, only set 1 to run test).
> + */
>   MODULE_PARM_DESC(test, "Run tests");
>   module_param_named(test, amdgpu_testing, int, 0444);
>
> +/**
> + * DOC: audio (int)
> + * Set Audio. The default is -1 (Enabled), set 0 to disabled it.<= br> > + */
>   MODULE_PARM_DESC(audio, "Audio enable (-1 =3D auto, 0= =3D disable, 1 =3D enable)");
>   module_param_named(audio, amdgpu_audio, int, 0444);
>
> +/**
> + * DOC: disp_priority (int)
> + * Set display Priority (0 =3D auto, 1 =3D normal, 2 =3D high). T= he default is 0.
> + */
>   MODULE_PARM_DESC(disp_priority, "Display Priority (0 = =3D auto, 1 =3D normal, 2 =3D high)");
>   module_param_named(disp_priority, amdgpu_disp_priority, in= t, 0444);
>
> +/**
> + * DOC: hw_i2c (int)
> + * To enable hw i2c engine. The default is 0 (Disabled).
> + */
>   MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 =3D= disable)");
>   module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
>
> +/**
> + * DOC: pcie_gen2 (int)
> + * To disable PCIE Gen2 mode (0 =3D disable, 1 =3D enable). The d= efault is -1 (auto, enabled).
> + */
>   MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 =3D a= uto, 0 =3D disable, 1 =3D enable)");
>   module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444)= ;
>
> +/**
> + * DOC: msi (int)
> + * To disable MSI functionality (1 =3D enable, 0 =3D disable). Th= e default is -1 (auto, enabled).
> + */
>   MODULE_PARM_DESC(msi, "MSI support (1 =3D enable, 0 = =3D disable, -1 =3D auto)");
>   module_param_named(msi, amdgpu_msi, int, 0444);
>
> +/**
> + * DOC: lockup_timeout (int)
> + * Set GPU scheduler timeout value in ms. It must be > 0. = ; The default is 10000.
> + */
>   MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout = in ms > 0 (default 10000)");
>   module_param_named(lockup_timeout, amdgpu_lockup_timeout, = int, 0444);
>
> +/**
> + * DOC: dpm (int)
> + * Override for dynamic power management setting (1 =3D enable, 0= =3D disable). The default is -1 (auto).
> + */
>   MODULE_PARM_DESC(dpm, "DPM support (1 =3D enable, 0 = =3D disable, -1 =3D auto)");
>   module_param_named(dpm, amdgpu_dpm, int, 0444);
>
> +/**
> + * DOC: fw_load_type (int)
> + * Set different firmware loading type for debugging (0 =3D direc= t, 1 =3D SMU, 2 =3D PSP). The default is -1 (auto).
> + */
>   MODULE_PARM_DESC(fw_load_type, "firmware loading type= (0 =3D direct, 1 =3D SMU, 2 =3D PSP, -1 =3D auto)");
>   module_param_named(fw_load_type, amdgpu_fw_load_type, int,= 0444);
>
> +/**
> + * DOC: aspm (int)
> + * To disable ASPM (1 =3D enable, 0 =3D disable). The default is = -1 (auto, enabled).
> + */
>   MODULE_PARM_DESC(aspm, "ASPM support (1 =3D enable, 0= =3D disable, -1 =3D auto)");
>   module_param_named(aspm, amdgpu_aspm, int, 0444);
>
> +/**
> + * DOC: runpm (int)
> + * Override for runtime power management control for dGPUs in PX/= HG laptops. The amdgpu driver can dynamically power down
> + * the dGPU on PX/HG laptops when it is idle. The default is -1 (= auto enable). Setting the value to 0 disables this functionality.
> + */
>   MODULE_PARM_DESC(runpm, "PX runtime pm (1 =3D force e= nable, 0 =3D disable, -1 =3D PX only default)");
>   module_param_named(runpm, amdgpu_runtime_pm, int, 0444); >
> +/**
> + * DOC: ip_block_mask (uint)
> + * Override what IP blocks are enabled on the GPU.  Each GPU= is a collection of IP blocks (gfx, display, video, etc.).
> + * Use this parameter to disable specific blocks. Note that the I= P blocks do not have a fixed index (e.g., you might have a device
> + * with multiple instances of an IP block) so the mask is board s= pecific. The default is 0xffffffff (enable all blocks on a device).
> + */
>   MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all b= locks enabled (default))");
>   module_param_named(ip_block_mask, amdgpu_ip_block_mask, ui= nt, 0444);
>
> +/**
> + * DOC: bapm (int)
> + * To disable BAPM (0 =3D disable). The default -1 (auto, enabled= )
> + */
>   MODULE_PARM_DESC(bapm, "BAPM support (1 =3D enable, 0= =3D disable, -1 =3D auto)");
>   module_param_named(bapm, amdgpu_bapm, int, 0444);
>
> +/**
> + * DOC: deep_color (int)
> + * Set 1 to enable Deep Color support. The default is 0 (disabled= ).
> + */
>   MODULE_PARM_DESC(deep_color, "Deep Color support (1 = =3D enable, 0 =3D disable (default))");
>   module_param_named(deep_color, amdgpu_deep_color, int, 044= 4);
>
> +/**
> + * DOC: vm_size (int)
> + * Override the size of the GPU's per client virtual address spac= e in GiB.  The default is -1 (automatic for each asic).
> + */
>   MODULE_PARM_DESC(vm_size, "VM address space size in g= igabytes (default 64GB)");
>   module_param_named(vm_size, amdgpu_vm_size, int, 0444); >
> +/**
> + * DOC: vm_fragment_size (int)
> + * Override VM fragment size in bits (4, 5, etc. 4 =3D 64K, 9 =3D= 2M). The default is -1 (automatic for each asic).
> + */
>   MODULE_PARM_DESC(vm_fragment_size, "VM fragment size = in bits (4, 5, etc. 4 =3D 64K (default), Max 9 =3D 2M)");
>   module_param_named(vm_fragment_size, amdgpu_vm_fragment_si= ze, int, 0444);
>
> +/**
> + * DOC: vm_block_size (int)
> + * Override VM page table size in bits (default depending on vm_s= ize and hw setup). The default is -1 (automatic for each asic).
> + */
>   MODULE_PARM_DESC(vm_block_size, "VM page table size i= n bits (default depending on vm_size)");
>   module_param_named(vm_block_size, amdgpu_vm_block_size, in= t, 0444);
>
> +/**
> + * DOC: vm_fault_stop (int)
> + * Stop on VM fault for debugging (0 =3D never, 1 =3D print first= , 2 =3D always). The default is 0 (No stop).
> + */
>   MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = =3D never (default), 1 =3D print first, 2 =3D always)");
>   module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, in= t, 0444);
>
> +/**
> + * DOC: vm_debug (int)
> + * Debug VM handling (0 =3D disabled, 1 =3D enabled). The default= is 0 (Disabled).
> + */
>   MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 =3D = disabled (default), 1 =3D enabled)");
>   module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);<= br> >
> +/**
> + * DOC: vm_update_mode (int)
> + * Override VM update mode. VM updated by using CPU (0 =3D never,= 1 =3D Graphics only, 2 =3D Compute only, 3 =3D Both). The default
> + * is -1 (Only in large BAR(LB) systems Compute VM tables will be= updated by CPU, otherwise 0, never).
> + */
>   MODULE_PARM_DESC(vm_update_mode, "VM update using CPU= (0 =3D never (default except for large BAR(LB)), 1 =3D Graphics only, 2 = =3D Compute only (default for LB), 3 =3D Both");
>   module_param_named(vm_update_mode, amdgpu_vm_update_mode, = int, 0444);
>
> +/**
> + * DOC: vram_page_split (int)
> + * Override the number of pages after we split VRAM allocations (= default 512, -1 =3D disable). The default is 512.
> + */
>   MODULE_PARM_DESC(vram_page_split, "Number of pages af= ter we split VRAM allocations (default 512, -1 =3D disable)");
>   module_param_named(vram_page_split, amdgpu_vram_page_split= , int, 0444);
>
> +/**
> + * DOC: exp_hw_support (int)
> + * Enable experimental hw support (1 =3D enable). The default is = 0 (disabled).
> + */
>   MODULE_PARM_DESC(exp_hw_support, "experimental hw sup= port (1 =3D enable, 0 =3D disable (default))");
>   module_param_named(exp_hw_support, amdgpu_exp_hw_support, = int, 0444);
>
> +/**
> + * DOC: dc (int)
> + * Disable/Enable Display Core driver for debugging (1 =3D enable= , 0 =3D disable). The default is -1 (automatic for each asic).
> + */
>   MODULE_PARM_DESC(dc, "Display Core driver (1 =3D enab= le, 0 =3D disable, -1 =3D auto (default))");
>   module_param_named(dc, amdgpu_dc, int, 0444);
>
>   MODULE_PARM_DESC(dc_log, "Display Core Log Level (0 = =3D minimal (default), 1 =3D chatty");
>   module_param_named(dc_log, amdgpu_dc_log, int, 0444);
>
> +/**
> + * DOC: sched_jobs (int)
> + * Override the max number of jobs supported in the sw queue. The= default is 32.
> + */
>   MODULE_PARM_DESC(sched_jobs, "the max number of jobs = supported in the sw queue (default 32)");
>   module_param_named(sched_jobs, amdgpu_sched_jobs, int, 044= 4);
>
> +/**
> + * DOC: sched_hw_submission (int)
> + * Override the max number of HW submissions. The default is 2. > + */
>   MODULE_PARM_DESC(sched_hw_submission, "the max number= of HW submissions (default 2)");
>   module_param_named(sched_hw_submission, amdgpu_sched_hw_su= bmission, int, 0444);
>
> +/**
> + * DOC: ppfeaturemask (uint)
> + * Override what power features are enabled. The default is 0xfff= f3fff (gfxoff(bit 15), overdriver(bit 14) disabled).
> + */
>   MODULE_PARM_DESC(ppfeaturemask, "all power features e= nabled (default))");
>   module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, = uint, 0444);
>
> @@ -241,58 +367,129 @@ module_param_named(no_evict, amdgpu_no_evic= t, int, 0444);
>   MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in= megabytes (max 96MB)");
>   module_param_named(direct_gma_size, amdgpu_direct_gma_size= , int, 0444);
>
> +/**
> + * DOC: pcie_gen_cap (uint)
> + * Override PCIE gen speed capabilities. The default is 0 (automa= tic for each asic).
> + */
>   MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: aut= odetect (default))");
>   module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint= , 0444);
>
> +/**
> + * DOC: pcie_lane_cap (uint)
> + * Override PCIE lanes capabilities. The default is 0 (automatic = for each asic).
> + */
>   MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: a= utodetect (default))");
>   module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, ui= nt, 0444);
>
> +/**
> + * DOC: cg_mask (uint)
> + * Override what Clockgating features are enabled on GPU (0 =3D d= isable clock gating). The default is 0xffffffff (all enabled).
> + */
>   MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = =3D disable clock gating)");
>   module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); >
> +/**
> + * DOC: pg_mask (uint)
> + * Override what Powergating features are enabled on GPU (0 =3D d= isable power gating). The default is 0xffffffff (all enabled).
> + */
>   MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = =3D disable power gating)");
>   module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); >
> +/**
> + * DOC: sdma_phase_quantum (uint)
> + * Override SDMA context switch phase quantum (x 1K GPU clock cyc= les, 0 =3D no change). The default is 32.
> + */
>   MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context sw= itch phase quantum (x 1K GPU clock cycles, 0 =3D no change (default 32))&qu= ot;);
>   module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_q= uantum, uint, 0444);
>
> +/**
> + * DOC: disable_cu (charp)
> + * Set to disable CUs (It's set like se.sh.cu,...). The default i= s NULL.
> + */
>   MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,.= ..)");
>   module_param_named(disable_cu, amdgpu_disable_cu, charp, 0= 444);
>
> +/**
> + * DOC: virtual_display (charp)
> + * Set to enable virtual display feature. This feature provides a= virtual display hardware on headless boards
> + * or in virtualized environments. It will be set like xxxx:xx:xx= .x,x;xxxx:xx:xx.x,x. The default is NULL.
> + */
>   MODULE_PARM_DESC(virtual_display,
>            = ;    "Enable virtual display feature (the virtual_displ= ay will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
>   module_param_named(virtual_display, amdgpu_virtual_display= , charp, 0444);
>
> +/**
> + * DOC: ngg (int)
> + * Set to enable Next Generation Graphics (1 =3D enable). The def= ault is 0 (disabled).
> + */
>   MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = =3D enable, 0 =3D disable(default depending on gfx))");
>   module_param_named(ngg, amdgpu_ngg, int, 0444);
>
> +/**
> + * DOC: prim_buf_per_se (int)
> + * Override the size of Primitive Buffer per Shader Engine in Byt= e. The default is 0 (depending on gfx).
> + */
>   MODULE_PARM_DESC(prim_buf_per_se, "the size of Primit= ive Buffer per Shader Engine (default depending on gfx)");
>   module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se= , int, 0444);
>
> +/**
> + * DOC: pos_buf_per_se (int)
> + * Override the size of Position Buffer per Shader Engine in Byte= . The default is 0 (depending on gfx).
> + */
>   MODULE_PARM_DESC(pos_buf_per_se, "the size of Positio= n Buffer per Shader Engine (default depending on gfx)");
>   module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, = int, 0444);
>
> +/**
> + * DOC: cntl_sb_buf_per_se (int)
> + * Override the size of Control Sideband per Shader Engine in Byt= e. The default is 0 (depending on gfx).
> + */
>   MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Con= trol Sideband per Shader Engine (default depending on gfx)");
>   module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_= per_se, int, 0444);
>
> +/**
> + * DOC: param_buf_per_se (int)
> + * Override the size of Off-Chip Pramater Cache per Shader Engine= in Byte. The default is 0 (depending on gfx).
> + */
>   MODULE_PARM_DESC(param_buf_per_se, "the size of Off-C= hip Pramater Cache per Shader Engine (default depending on gfx)");
>   module_param_named(param_buf_per_se, amdgpu_param_buf_per_= se, int, 0444);
>
> +/**
> + * DOC: job_hang_limit (int)
> + * Set how much time allow a job hang and not drop it. The defaul= t is 0.
> + */
>   MODULE_PARM_DESC(job_hang_limit, "how much time allow= a job hang and not drop it (default 0)");
>   module_param_named(job_hang_limit, amdgpu_job_hang_limit, = int ,0444);
>
> +/**
> + * DOC: lbpw (int)
> + * Override Load Balancing Per Watt (LBPW) support (1 =3D enable,= 0 =3D disable). The default is -1 (auto, enabled).
> + */
>   MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW= ) support (1 =3D enable, 0 =3D disable, -1 =3D auto)");
>   module_param_named(lbpw, amdgpu_lbpw, int, 0444);
>
>   MODULE_PARM_DESC(compute_multipipe, "Force compute qu= eues to be spread across pipes (1 =3D enable, 0 =3D disable, -1 =3D auto)&q= uot;);
>   module_param_named(compute_multipipe, amdgpu_compute_multi= pipe, int, 0444);
>
> +/**
> + * DOC: gpu_recovery (int)
> + * Set to enable GPU recovery mechanism (1 =3D enable, 0 =3D disa= ble). The default is -1 (auto, disabled except SRIOV).
> + */
>   MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery m= echanism, (1 =3D enable, 0 =3D disable, -1 =3D auto)");
>   module_param_named(gpu_recovery, amdgpu_gpu_recovery, int,= 0444);
>
> +/**
> + * DOC: emu_mode (int)
> + * Set value 1 to enable emulation mode. The default is 0 (disabl= ed).
> + */
>   MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 =3D en= able, 0 =3D disable)");
>   module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);<= br> >
> +/**
> + * DOC: si_support (int)
> + * Set SI support driver. This parameter works after set config C= ONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
> + * set value 0 to use radeon driver, while set value 1 to use amd= gpu driver. The default is using radeon driver when it available,
> + * otherwise using amdgpu driver.
> + */
>   #ifdef CONFIG_DRM_AMDGPU_SI
>
>   #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEO= N_MODULE)
> @@ -306,6 +503,12 @@ MODULE_PARM_DESC(si_support, "SI support= (1 =3D enabled (default), 0 =3D disabled)")
>   module_param_named(si_support, amdgpu_si_support, int, 044= 4);
>   #endif
>
> +/**
> + * DOC: cik_support (int)
> + * Set CIK support driver. This parameter works after set config = CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
> + * set value 0 to use radeon driver, while set value 1 to use amd= gpu driver. The default is using radeon driver when it available,
> + * otherwise using amdgpu driver.
> + */
>   #ifdef CONFIG_DRM_AMDGPU_CIK
>
>   #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEO= N_MODULE)
> @@ -319,6 +522,11 @@ MODULE_PARM_DESC(cik_support, "CIK suppo= rt (1 =3D enabled (default), 0 =3D disabled)
>   module_param_named(cik_support, amdgpu_cik_support, int, 0= 444);
>   #endif
>
> +/**
> + * DOC: smu_memory_pool_size (uint)
> + * It is used to reserve gtt for smu debug usage, setting value 0= to disable it. The actual size is value * 256MiB.
> + * E.g. 0x1 =3D 256Mbyte, 0x2 =3D 512Mbyte, 0x4 =3D 1 Gbyte, 0x8 = =3D 2GByte. The default is 0 (disabled).
> + */
>   MODULE_PARM_DESC(smu_memory_pool_size,
>       "reserve gtt for smu debug us= age, 0 =3D disable,"
>            = ;   "0x1 =3D 256Mbyte, 0x2 =3D 512Mbyte, 0x4 =3D 1 Gbyte, 0x= 8 =3D 2GByte");
>
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