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* [PATCH 1/2] drm/amd/powerplay: add UMD P-state in powerplay.
@ 2017-08-29  9:14 Rex Zhu
       [not found] ` <1503998069-32488-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 4+ messages in thread
From: Rex Zhu @ 2017-08-29  9:14 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu

This feature is for UMD to run benchmark in a
power state that is as steady as possible. kmd
need to fix the power state as stable as possible.
now, kmd support four level:
profile_standard,peak,min_sclk,min_mclk

move common related code to amd_powerplay.c

Change-Id: Ie06c122199b7246f5b1951c354cf502bbed27485
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c      | 40 +++++++++++++++++++++-
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     | 24 +------------
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 25 +-------------
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 25 +-------------
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |  3 +-
 5 files changed, 44 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index f73e80c..310f34a 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -30,7 +30,7 @@
 #include "pp_instance.h"
 #include "power_state.h"
 #include "eventmanager.h"
-
+#include "eventtasks.h"
 
 static inline int pp_check(struct pp_instance *handle)
 {
@@ -324,12 +324,44 @@ static int pp_dpm_fw_loading_complete(void *handle)
 	return 0;
 }
 
+static void pp_dpm_en_umd_pstate(struct pp_hwmgr  *hwmgr,
+						enum amd_dpm_forced_level level)
+{
+	uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
+					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
+					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
+					AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
+
+	if (!(hwmgr->dpm_level & profile_mode_mask)) {
+		/* enter umd pstate, save current level, disable gfx cg*/
+		if (level & profile_mode_mask) {
+			hwmgr->saved_dpm_level = hwmgr->dpm_level;
+			hwmgr->en_umd_pstate = true;
+			cgs_set_clockgating_state(hwmgr->device,
+						AMD_IP_BLOCK_TYPE_GFX,
+						AMD_CG_STATE_UNGATE);
+		}
+	} else {
+		/* exit umd pstate, restore level, enable gfx cg*/
+		if (!(level & profile_mode_mask)) {
+			if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
+				level = hwmgr->saved_dpm_level;
+			hwmgr->en_umd_pstate = false;
+			cgs_set_clockgating_state(hwmgr->device,
+					AMD_IP_BLOCK_TYPE_GFX,
+					AMD_CG_STATE_GATE);
+		}
+	}
+	return;
+}
+
 static int pp_dpm_force_performance_level(void *handle,
 					enum amd_dpm_forced_level level)
 {
 	struct pp_hwmgr  *hwmgr;
 	struct pp_instance *pp_handle = (struct pp_instance *)handle;
 	int ret = 0;
+	struct pem_event_data data = { {0} };
 
 	ret = pp_check(pp_handle);
 
@@ -338,13 +370,19 @@ static int pp_dpm_force_performance_level(void *handle,
 
 	hwmgr = pp_handle->hwmgr;
 
+	if (level == hwmgr->dpm_level)
+		return 0;
+
 	if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
 		pr_info("%s was not implemented.\n", __func__);
 		return 0;
 	}
 
 	mutex_lock(&pp_handle->pp_lock);
+	pp_dpm_en_umd_pstate(hwmgr, level);
+	pem_task_adjust_power_state(pp_handle->eventmgr, &data);
 	hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
+
 	mutex_unlock(&pp_handle->pp_lock);
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index bc839ff..a125e30 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1355,31 +1355,9 @@ static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
 {
 	uint32_t sclk = 0;
 	int ret = 0;
-	uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
-					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
-					AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 
 	if (level == hwmgr->dpm_level)
-		return ret;
-
-	if (!(hwmgr->dpm_level & profile_mode_mask)) {
-		/* enter profile mode, save current level, disable gfx cg*/
-		if (level & profile_mode_mask) {
-			hwmgr->saved_dpm_level = hwmgr->dpm_level;
-			cgs_set_clockgating_state(hwmgr->device,
-						AMD_IP_BLOCK_TYPE_GFX,
-						AMD_CG_STATE_UNGATE);
-		}
-	} else {
-		/* exit profile mode, restore level, enable gfx cg*/
-		if (!(level & profile_mode_mask)) {
-			if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
-				level = hwmgr->saved_dpm_level;
-			cgs_set_clockgating_state(hwmgr->device,
-					AMD_IP_BLOCK_TYPE_GFX,
-					AMD_CG_STATE_GATE);
-		}
-	}
+		return 0;
 
 	switch (level) {
 	case AMD_DPM_FORCED_LEVEL_HIGH:
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index f7aa057..a917fc5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2577,32 +2577,9 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
 	uint32_t sclk_mask = 0;
 	uint32_t mclk_mask = 0;
 	uint32_t pcie_mask = 0;
-	uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
-					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
-					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
-					AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 
 	if (level == hwmgr->dpm_level)
-		return ret;
-
-	if (!(hwmgr->dpm_level & profile_mode_mask)) {
-		/* enter profile mode, save current level, disable gfx cg*/
-		if (level & profile_mode_mask) {
-			hwmgr->saved_dpm_level = hwmgr->dpm_level;
-			cgs_set_clockgating_state(hwmgr->device,
-						AMD_IP_BLOCK_TYPE_GFX,
-						AMD_CG_STATE_UNGATE);
-		}
-	} else {
-		/* exit profile mode, restore level, enable gfx cg*/
-		if (!(level & profile_mode_mask)) {
-			if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
-				level = hwmgr->saved_dpm_level;
-			cgs_set_clockgating_state(hwmgr->device,
-					AMD_IP_BLOCK_TYPE_GFX,
-					AMD_CG_STATE_GATE);
-		}
-	}
+		return 0;
 
 	switch (level) {
 	case AMD_DPM_FORCED_LEVEL_HIGH:
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 268fa24..f14047d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4536,32 +4536,9 @@ static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
 	uint32_t sclk_mask = 0;
 	uint32_t mclk_mask = 0;
 	uint32_t soc_mask = 0;
-	uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
-					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
-					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
-					AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 
 	if (level == hwmgr->dpm_level)
-		return ret;
-
-	if (!(hwmgr->dpm_level & profile_mode_mask)) {
-		/* enter profile mode, save current level, disable gfx cg*/
-		if (level & profile_mode_mask) {
-			hwmgr->saved_dpm_level = hwmgr->dpm_level;
-			cgs_set_clockgating_state(hwmgr->device,
-						AMD_IP_BLOCK_TYPE_GFX,
-						AMD_CG_STATE_UNGATE);
-		}
-	} else {
-		/* exit profile mode, restore level, enable gfx cg*/
-		if (!(level & profile_mode_mask)) {
-			if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
-				level = hwmgr->saved_dpm_level;
-			cgs_set_clockgating_state(hwmgr->device,
-					AMD_IP_BLOCK_TYPE_GFX,
-					AMD_CG_STATE_GATE);
-		}
-	}
+		return 0;
 
 	switch (level) {
 	case AMD_DPM_FORCED_LEVEL_HIGH:
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index eb2e277..d2224ed 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -802,12 +802,13 @@ struct pp_hwmgr {
 	struct amd_pp_display_configuration display_config;
 	uint32_t feature_mask;
 
-	/* power profile */
+	/* UMD Pstate */
 	struct amd_pp_profile gfx_power_profile;
 	struct amd_pp_profile compute_power_profile;
 	struct amd_pp_profile default_gfx_power_profile;
 	struct amd_pp_profile default_compute_power_profile;
 	enum amd_pp_profile_type current_power_profile;
+	bool en_umd_pstate;
 };
 
 extern int hwmgr_early_init(struct pp_instance *handle);
-- 
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [PATCH 2/2] drm/amd/powerplay: set uvd/vce/nb/mclk level as pstate requested
       [not found] ` <1503998069-32488-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-08-29  9:14   ` Rex Zhu
       [not found]     ` <1503998069-32488-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
  2017-08-29 13:56   ` [PATCH 1/2] drm/amd/powerplay: add UMD P-state in powerplay Deucher, Alexander
  1 sibling, 1 reply; 4+ messages in thread
From: Rex Zhu @ 2017-08-29  9:14 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu

Change-Id: Ibd74590c3fe9dbdeac924b697d18448bddbefcdb
---
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index a125e30..10bf687 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1359,6 +1359,11 @@ static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
 	if (level == hwmgr->dpm_level)
 		return 0;
 
+	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+		cz_nbdpm_pstate_enable_disable(hwmgr, false, false);
+	else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD)
+		cz_nbdpm_pstate_enable_disable(hwmgr, false, true);
+
 	switch (level) {
 	case AMD_DPM_FORCED_LEVEL_HIGH:
 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
@@ -1435,7 +1440,8 @@ int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
 	if (!bgate) {
 		/* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-					 PHM_PlatformCaps_StablePState)) {
+					 PHM_PlatformCaps_StablePState)
+			|| hwmgr->en_umd_pstate) {
 			cz_hwmgr->uvd_dpm.hard_min_clk =
 				   ptable->entries[ptable->count - 1].vclk;
 
@@ -1464,7 +1470,8 @@ int  cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
 
 	/* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-					 PHM_PlatformCaps_StablePState)) {
+					PHM_PlatformCaps_StablePState)
+					|| hwmgr->en_umd_pstate) {
 		cz_hwmgr->vce_dpm.hard_min_clk =
 				  ptable->entries[ptable->count - 1].ecclk;
 
-- 
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* RE: [PATCH 1/2] drm/amd/powerplay: add UMD P-state in powerplay.
       [not found] ` <1503998069-32488-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
  2017-08-29  9:14   ` [PATCH 2/2] drm/amd/powerplay: set uvd/vce/nb/mclk level as pstate requested Rex Zhu
@ 2017-08-29 13:56   ` Deucher, Alexander
  1 sibling, 0 replies; 4+ messages in thread
From: Deucher, Alexander @ 2017-08-29 13:56 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zhu, Rex

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Tuesday, August 29, 2017 5:14 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 1/2] drm/amd/powerplay: add UMD P-state in powerplay.
> 
> This feature is for UMD to run benchmark in a
> power state that is as steady as possible. kmd
> need to fix the power state as stable as possible.
> now, kmd support four level:
> profile_standard,peak,min_sclk,min_mclk
> 
> move common related code to amd_powerplay.c
> 
> Change-Id: Ie06c122199b7246f5b1951c354cf502bbed27485
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c      | 40
> +++++++++++++++++++++-
>  drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     | 24 +------------
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 25 +-------------
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 25 +------------
> -
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |  3 +-
>  5 files changed, 44 insertions(+), 73 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index f73e80c..310f34a 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -30,7 +30,7 @@
>  #include "pp_instance.h"
>  #include "power_state.h"
>  #include "eventmanager.h"
> -
> +#include "eventtasks.h"
> 
>  static inline int pp_check(struct pp_instance *handle)
>  {
> @@ -324,12 +324,44 @@ static int pp_dpm_fw_loading_complete(void
> *handle)
>  	return 0;
>  }
> 
> +static void pp_dpm_en_umd_pstate(struct pp_hwmgr  *hwmgr,
> +						enum
> amd_dpm_forced_level level)
> +{
> +	uint32_t profile_mode_mask =
> AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
> +
> 	AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
> +
> 	AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
> +
> 	AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
> +
> +	if (!(hwmgr->dpm_level & profile_mode_mask)) {
> +		/* enter umd pstate, save current level, disable gfx cg*/
> +		if (level & profile_mode_mask) {
> +			hwmgr->saved_dpm_level = hwmgr->dpm_level;
> +			hwmgr->en_umd_pstate = true;
> +			cgs_set_clockgating_state(hwmgr->device,
> +						AMD_IP_BLOCK_TYPE_GFX,
> +						AMD_CG_STATE_UNGATE);
> +		}
> +	} else {
> +		/* exit umd pstate, restore level, enable gfx cg*/
> +		if (!(level & profile_mode_mask)) {
> +			if (level ==
> AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
> +				level = hwmgr->saved_dpm_level;
> +			hwmgr->en_umd_pstate = false;
> +			cgs_set_clockgating_state(hwmgr->device,
> +					AMD_IP_BLOCK_TYPE_GFX,
> +					AMD_CG_STATE_GATE);
> +		}
> +	}
> +	return;

Can drop the return here.  With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> +}
> +
>  static int pp_dpm_force_performance_level(void *handle,
>  					enum amd_dpm_forced_level level)
>  {
>  	struct pp_hwmgr  *hwmgr;
>  	struct pp_instance *pp_handle = (struct pp_instance *)handle;
>  	int ret = 0;
> +	struct pem_event_data data = { {0} };
> 
>  	ret = pp_check(pp_handle);
> 
> @@ -338,13 +370,19 @@ static int pp_dpm_force_performance_level(void
> *handle,
> 
>  	hwmgr = pp_handle->hwmgr;
> 
> +	if (level == hwmgr->dpm_level)
> +		return 0;
> +
>  	if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
>  		pr_info("%s was not implemented.\n", __func__);
>  		return 0;
>  	}
> 
>  	mutex_lock(&pp_handle->pp_lock);
> +	pp_dpm_en_umd_pstate(hwmgr, level);
> +	pem_task_adjust_power_state(pp_handle->eventmgr, &data);
>  	hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
> +
>  	mutex_unlock(&pp_handle->pp_lock);
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> index bc839ff..a125e30 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> @@ -1355,31 +1355,9 @@ static int cz_dpm_force_dpm_level(struct
> pp_hwmgr *hwmgr,
>  {
>  	uint32_t sclk = 0;
>  	int ret = 0;
> -	uint32_t profile_mode_mask =
> AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
> -
> 	AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
> -
> 	AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
> 
>  	if (level == hwmgr->dpm_level)
> -		return ret;
> -
> -	if (!(hwmgr->dpm_level & profile_mode_mask)) {
> -		/* enter profile mode, save current level, disable gfx cg*/
> -		if (level & profile_mode_mask) {
> -			hwmgr->saved_dpm_level = hwmgr->dpm_level;
> -			cgs_set_clockgating_state(hwmgr->device,
> -						AMD_IP_BLOCK_TYPE_GFX,
> -						AMD_CG_STATE_UNGATE);
> -		}
> -	} else {
> -		/* exit profile mode, restore level, enable gfx cg*/
> -		if (!(level & profile_mode_mask)) {
> -			if (level ==
> AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
> -				level = hwmgr->saved_dpm_level;
> -			cgs_set_clockgating_state(hwmgr->device,
> -					AMD_IP_BLOCK_TYPE_GFX,
> -					AMD_CG_STATE_GATE);
> -		}
> -	}
> +		return 0;
> 
>  	switch (level) {
>  	case AMD_DPM_FORCED_LEVEL_HIGH:
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index f7aa057..a917fc5 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -2577,32 +2577,9 @@ static int smu7_force_dpm_level(struct
> pp_hwmgr *hwmgr,
>  	uint32_t sclk_mask = 0;
>  	uint32_t mclk_mask = 0;
>  	uint32_t pcie_mask = 0;
> -	uint32_t profile_mode_mask =
> AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
> -
> 	AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
> -
> 	AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
> -
> 	AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
> 
>  	if (level == hwmgr->dpm_level)
> -		return ret;
> -
> -	if (!(hwmgr->dpm_level & profile_mode_mask)) {
> -		/* enter profile mode, save current level, disable gfx cg*/
> -		if (level & profile_mode_mask) {
> -			hwmgr->saved_dpm_level = hwmgr->dpm_level;
> -			cgs_set_clockgating_state(hwmgr->device,
> -						AMD_IP_BLOCK_TYPE_GFX,
> -						AMD_CG_STATE_UNGATE);
> -		}
> -	} else {
> -		/* exit profile mode, restore level, enable gfx cg*/
> -		if (!(level & profile_mode_mask)) {
> -			if (level ==
> AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
> -				level = hwmgr->saved_dpm_level;
> -			cgs_set_clockgating_state(hwmgr->device,
> -					AMD_IP_BLOCK_TYPE_GFX,
> -					AMD_CG_STATE_GATE);
> -		}
> -	}
> +		return 0;
> 
>  	switch (level) {
>  	case AMD_DPM_FORCED_LEVEL_HIGH:
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 268fa24..f14047d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4536,32 +4536,9 @@ static int vega10_dpm_force_dpm_level(struct
> pp_hwmgr *hwmgr,
>  	uint32_t sclk_mask = 0;
>  	uint32_t mclk_mask = 0;
>  	uint32_t soc_mask = 0;
> -	uint32_t profile_mode_mask =
> AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
> -
> 	AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
> -
> 	AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
> -
> 	AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
> 
>  	if (level == hwmgr->dpm_level)
> -		return ret;
> -
> -	if (!(hwmgr->dpm_level & profile_mode_mask)) {
> -		/* enter profile mode, save current level, disable gfx cg*/
> -		if (level & profile_mode_mask) {
> -			hwmgr->saved_dpm_level = hwmgr->dpm_level;
> -			cgs_set_clockgating_state(hwmgr->device,
> -						AMD_IP_BLOCK_TYPE_GFX,
> -						AMD_CG_STATE_UNGATE);
> -		}
> -	} else {
> -		/* exit profile mode, restore level, enable gfx cg*/
> -		if (!(level & profile_mode_mask)) {
> -			if (level ==
> AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
> -				level = hwmgr->saved_dpm_level;
> -			cgs_set_clockgating_state(hwmgr->device,
> -					AMD_IP_BLOCK_TYPE_GFX,
> -					AMD_CG_STATE_GATE);
> -		}
> -	}
> +		return 0;
> 
>  	switch (level) {
>  	case AMD_DPM_FORCED_LEVEL_HIGH:
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index eb2e277..d2224ed 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -802,12 +802,13 @@ struct pp_hwmgr {
>  	struct amd_pp_display_configuration display_config;
>  	uint32_t feature_mask;
> 
> -	/* power profile */
> +	/* UMD Pstate */
>  	struct amd_pp_profile gfx_power_profile;
>  	struct amd_pp_profile compute_power_profile;
>  	struct amd_pp_profile default_gfx_power_profile;
>  	struct amd_pp_profile default_compute_power_profile;
>  	enum amd_pp_profile_type current_power_profile;
> +	bool en_umd_pstate;
>  };
> 
>  extern int hwmgr_early_init(struct pp_instance *handle);
> --
> 1.9.1
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread

* RE: [PATCH 2/2] drm/amd/powerplay: set uvd/vce/nb/mclk level as pstate requested
       [not found]     ` <1503998069-32488-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-08-29 13:58       ` Deucher, Alexander
  0 siblings, 0 replies; 4+ messages in thread
From: Deucher, Alexander @ 2017-08-29 13:58 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zhu, Rex

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Tuesday, August 29, 2017 5:14 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 2/2] drm/amd/powerplay: set uvd/vce/nb/mclk level as
> pstate requested
> 
> Change-Id: Ibd74590c3fe9dbdeac924b697d18448bddbefcdb

Missing your signed-off-by.

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> index a125e30..10bf687 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> @@ -1359,6 +1359,11 @@ static int cz_dpm_force_dpm_level(struct
> pp_hwmgr *hwmgr,
>  	if (level == hwmgr->dpm_level)
>  		return 0;
> 
> +	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> +		cz_nbdpm_pstate_enable_disable(hwmgr, false, false);
> +	else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD)
> +		cz_nbdpm_pstate_enable_disable(hwmgr, false, true);
> +

Do we need a default case here as well for the nbdpm to reset it back to normal when profiling mode is disabled?

Alex

>  	switch (level) {
>  	case AMD_DPM_FORCED_LEVEL_HIGH:
>  	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> @@ -1435,7 +1440,8 @@ int cz_dpm_update_uvd_dpm(struct pp_hwmgr
> *hwmgr, bool bgate)
>  	if (!bgate) {
>  		/* Stable Pstate is enabled and we need to set the UVD DPM
> to highest level */
>  		if (phm_cap_enabled(hwmgr-
> >platform_descriptor.platformCaps,
> -					 PHM_PlatformCaps_StablePState)) {
> +					 PHM_PlatformCaps_StablePState)
> +			|| hwmgr->en_umd_pstate) {
>  			cz_hwmgr->uvd_dpm.hard_min_clk =
>  				   ptable->entries[ptable->count - 1].vclk;
> 
> @@ -1464,7 +1470,8 @@ int  cz_dpm_update_vce_dpm(struct pp_hwmgr
> *hwmgr)
> 
>  	/* Stable Pstate is enabled and we need to set the VCE DPM to
> highest level */
>  	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> -					 PHM_PlatformCaps_StablePState)) {
> +					PHM_PlatformCaps_StablePState)
> +					|| hwmgr->en_umd_pstate) {
>  		cz_hwmgr->vce_dpm.hard_min_clk =
>  				  ptable->entries[ptable->count - 1].ecclk;
> 
> --
> 1.9.1
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2017-08-29 13:58 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-29  9:14 [PATCH 1/2] drm/amd/powerplay: add UMD P-state in powerplay Rex Zhu
     [not found] ` <1503998069-32488-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-08-29  9:14   ` [PATCH 2/2] drm/amd/powerplay: set uvd/vce/nb/mclk level as pstate requested Rex Zhu
     [not found]     ` <1503998069-32488-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-08-29 13:58       ` Deucher, Alexander
2017-08-29 13:56   ` [PATCH 1/2] drm/amd/powerplay: add UMD P-state in powerplay Deucher, Alexander

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