From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Zhu, Rex" Subject: Re: [PATCH 1/2] drm/amd/display: fix array lenth error. Date: Mon, 6 Feb 2017 15:36:54 +0000 Message-ID: References: <1486357719-7102-1-git-send-email-Rex.Zhu@amd.com>, Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0960274201==" Return-path: In-Reply-To: Content-Language: en-US List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: "Wentland, Harry" , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" --===============0960274201== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_CY4PR12MB168712DD6B6D2BA7E7861CB7FB400CY4PR12MB1687namp_" --_000_CY4PR12MB168712DD6B6D2BA7E7861CB7FB400CY4PR12MB1687namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable seems reasonable. but i think need to check num_levels can't be 0. in some case, there is on= ly one level of mclk, and higher than the max validation clocks.. and will = lead kernel panic. Best Regards Rex ________________________________ From: Wentland, Harry Sent: Monday, February 6, 2017 10:54:24 PM To: Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Subject: Re: [PATCH 1/2] drm/amd/display: fix array lenth error. On 2017-02-06 12:08 AM, Rex Zhu wrote: > Change-Id: I09011c5e6d5493db7e3d9a7ff7ab8c871a8db862 > Signed-off-by: Rex Zhu > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b= /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c > index 5af27aa..50576c6 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c > @@ -358,7 +358,7 @@ bool dm_pp_get_clock_levels_by_type( > * non-boosted one. */ > DRM_INFO("DM_PPLIB: reducing engine clock = level from %d to %d\n", > dc_clks->num_levels, i + 1= ); > - dc_clks->num_levels =3D i; > + dc_clks->num_levels =3D i + 1; It seems to me the DRM_INFO print is wrong here, not the actual assignment. We're setting num_levels to the current index if the clocks for that index are higher than the max validation clocks, hence this index now should become num_levels. > break; > } > } > @@ -367,7 +367,7 @@ bool dm_pp_get_clock_levels_by_type( > if (dc_clks->clocks_in_khz[i] > validation_clks.me= mory_max_clock) { > DRM_INFO("DM_PPLIB: reducing memory clock = level from %d to %d\n", > dc_clks->num_levels, i + 1= ); > - dc_clks->num_levels =3D i; > + dc_clks->num_levels =3D i + 1; > break; > } > } > Same comment as above. Harry --_000_CY4PR12MB168712DD6B6D2BA7E7861CB7FB400CY4PR12MB1687namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

seems reasonable.


but i think need to check num_levels  can't be 0. in some case, there is only on= e level of mclk, and higher than the ma= x validation clocks.. and will lead kernel panic.


Best Regards

Rex

From: Wentland, Harry
Sent: Monday, February 6, 2017 10:54:24 PM
To: Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 1/2] drm/amd/display: fix array lenth error.
 
On 2017-02-06 12:08 AM, Rex Zhu wrote:
> Change-Id: I09011c5e6d5493db7e3d9a7ff7ab8c871a8db862
> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 4 &= #43;+--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.= c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> index 5af27aa..50576c6 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_serv= ices.c
> @@ -358,7 +358,7 @@ bool dm_pp_get_clock_levels_by_type(
>            = ;            &n= bsp;        * non-boosted one. */
>            = ;            &n= bsp;       DRM_INFO("DM_PPLIB: reducing = engine clock level from %d to %d\n",
>            = ;            &n= bsp;            = ;           dc_clks->n= um_levels, i + 1);
> -           &nb= sp;            =      dc_clks->num_levels =3D i;
> +           = ;            &n= bsp;     dc_clks->num_levels =3D i + 1;

It seems to me the DRM_INFO print is wrong here, not the actual
assignment. We're setting num_levels to the current index if the clocks
for that index are higher than the max validation clocks, hence this
index now should become num_levels.

>            = ;            &n= bsp;       break;
>            = ;            }
>            = ;    }
> @@ -367,7 +367,7 @@ bool dm_pp_get_clock_levels_by_type(
>            = ;            if (dc_= clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
>            = ;            &n= bsp;       DRM_INFO("DM_PPLIB: reducing = memory clock level from %d to %d\n",
>            = ;            &n= bsp;            = ;           dc_clks->n= um_levels, i + 1);
> -           &nb= sp;            =      dc_clks->num_levels =3D i;
> +           = ;            &n= bsp;     dc_clks->num_levels =3D i + 1;
>            = ;            &n= bsp;       break;
>            = ;            }
>            = ;    }
>

Same comment as above.

Harry
 --_000_CY4PR12MB168712DD6B6D2BA7E7861CB7FB400CY4PR12MB1687namp_-- --===============0960274201== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KYW1kLWdmeCBt YWlsaW5nIGxpc3QKYW1kLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5m cmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9hbWQtZ2Z4Cg== --===============0960274201==--