[PATCH 1/3] drm/amd/pp: Delete duplicated interface in hwmgr_func

[PATCH 1/3] drm/amd/pp: Delete duplicated interface in hwmgr_func

[Rex Zhu]

gfx off support in smu can be via powergate_gfx interface.
so remove the gfx_off_control interface.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 1 -
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h         | 1 -
 2 files changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index a63e006..26d130a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1185,7 +1185,6 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
 	.dynamic_state_management_disable = smu10_disable_dpm_tasks,
 	.powergate_mmhub = smu10_powergate_mmhub,
 	.smus_notify_pwe = smu10_smus_notify_pwe,
-	.gfx_off_control = smu10_gfx_off_control,
 	.display_clock_voltage_request = smu10_display_clock_voltage_request,
 	.powergate_gfx = smu10_gfx_off_control,
 };
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 7e58a0d..88f4517 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -298,7 +298,6 @@ struct pp_hwmgr_func {
 	int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
 			struct pp_display_clock_request *clock);
 	int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
-	int (*gfx_off_control)(struct pp_hwmgr *hwmgr, bool enable);
 	int (*power_off_asic)(struct pp_hwmgr *hwmgr);
 	int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
 	int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
-- 
1.9.1

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[PATCH 2/3] drm/amd/pp: Export interface to help check hw power state

[Rex Zhu]

As more hw ip pg feature have been enabled(especial gfx off),
so need to check the hw power state before read/write registers
through mmio.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/include/kgd_pp_interface.h |  1 +
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 21 +++++++++++++++++++++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h      |  1 +
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 6a41b81..3b5b2de 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -269,6 +269,7 @@ struct amd_pm_funcs {
 	int (*get_display_mode_validation_clocks)(void *handle,
 		struct amd_pp_simple_clock_info *clocks);
 	int (*notify_smu_enable_pwe)(void *handle);
+	bool (*is_hw_ip_on)(void *handle, enum amd_ip_block_type client);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index da4ebff..c50164e 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1243,6 +1243,26 @@ static int pp_notify_smu_enable_pwe(void *handle)
 	return 0;
 }
 
+static bool pp_is_hw_ip_on(void *handle, enum amd_ip_block_type client)
+{
+	struct pp_hwmgr *hwmgr = handle;
+	bool ret;
+
+	if (!hwmgr || !hwmgr->pm_en)
+		return true;
+
+	if (hwmgr->hwmgr_func->is_hw_ip_on == NULL) {
+		pr_info("%s was not implemented.\n", __func__);
+		return true;
+	}
+
+	mutex_lock(&hwmgr->smu_lock);
+	ret = hwmgr->hwmgr_func->is_hw_ip_on(hwmgr, client);
+	mutex_unlock(&hwmgr->smu_lock);
+
+	return ret;
+}
+
 static const struct amd_pm_funcs pp_dpm_funcs = {
 	.load_firmware = pp_dpm_load_fw,
 	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
@@ -1274,6 +1294,7 @@ static int pp_notify_smu_enable_pwe(void *handle)
 	.odn_edit_dpm_table = pp_odn_edit_dpm_table,
 	.set_power_limit = pp_set_power_limit,
 	.get_power_limit = pp_get_power_limit,
+	.is_hw_ip_on = pp_is_hw_ip_on,
 /* export to DC */
 	.get_sclk = pp_dpm_get_sclk,
 	.get_mclk = pp_dpm_get_mclk,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 88f4517..3aca3a3 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -328,6 +328,7 @@ struct pp_hwmgr_func {
 	int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
 	int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
 	int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
+	bool (*is_hw_ip_on)(struct pp_hwmgr *hwmgr, enum amd_ip_block_type client);
 };
 
 struct pp_table_func {
-- 
1.9.1

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[PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12

[Rex Zhu]

As gfx off is supported on Rv/Vega12, so this check is
helpful and necessary when visit gfx regesiter via mmio.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  | 10 +++++++
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 31 +++++++++++++++++++++-
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 26d130a..da1be82 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -296,6 +296,15 @@ static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
 	return false;
 }
 
+static bool smu10_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+				enum amd_ip_block_type client)
+{
+	if (client == AMD_IP_BLOCK_TYPE_GFX)
+		return smu10_is_gfx_on(hwmgr);
+	else /* for other ip, to do */
+		return true;
+}
+
 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
 {
 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
@@ -1187,6 +1196,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
 	.smus_notify_pwe = smu10_smus_notify_pwe,
 	.display_clock_voltage_request = smu10_display_clock_voltage_request,
 	.powergate_gfx = smu10_gfx_off_control,
+	.is_hw_ip_on = smu10_is_hw_ip_on,
 };
 
 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 0789d64..ee44300 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -45,7 +45,7 @@
 #include "ppinterrupt.h"
 #include "pp_overdriver.h"
 #include "pp_thermal.h"
-
+#include "soc15_common.h"
 
 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
 		enum pp_clock_type type, uint32_t mask);
@@ -2320,6 +2320,34 @@ static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
+/* GFX HW Power Status can be queried from bits [1:0] of MP1_SMN_EXT_SCRATCH0
+ * 2'b00   GFX is OFF
+ * 2'b01   Transitioning out of GFXOFF state
+ * 2'b10   GFX is ON
+ * 2'b11   Transitioning into GFXOFF state
+*/
+
+static bool vega12_is_gfx_on(struct pp_hwmgr *hwmgr)
+{
+	uint32_t tmp;
+	struct amdgpu_device *adev = hwmgr->adev;
+
+	tmp = RREG32_SOC15(MP1, 0, mmMP1_SMN_EXT_SCRATCH0);
+	if (tmp == 1 || tmp == 2)
+		return true;
+	else
+		return false;
+}
+
+static bool vega12_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+				enum amd_ip_block_type client)
+{
+	if (client == AMD_IP_BLOCK_TYPE_GFX)
+		return vega12_is_gfx_on(hwmgr);
+	else /* for other ip, to do */
+		return true;
+}
+
 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
 {
 	struct vega12_hwmgr *data =
@@ -2402,6 +2430,7 @@ static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
 	.register_irq_handlers = smu9_register_irq_handlers,
 	.start_thermal_controller = vega12_start_thermal_controller,
 	.powergate_gfx = vega12_gfx_off_control,
+	.is_hw_ip_on = vega12_is_hw_ip_on,
 };
 
 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
-- 
1.9.1

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Re: [PATCH 1/3] drm/amd/pp: Delete duplicated interface in hwmgr_func

[Quan, Evan]

[-- Attachment #1.1: Type: text/plain, Size: 2513 bytes --]

Reviewed-by: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>

________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Rex Zhu <rex.zhu-5C7GfCeVMHo@public.gmane.org>
Sent: Sunday, July 29, 2018 7:42:25 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Zhu, Rex
Subject: [PATCH 1/3] drm/amd/pp: Delete duplicated interface in hwmgr_func

gfx off support in smu can be via powergate_gfx interface.
so remove the gfx_off_control interface.

Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 1 -
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h         | 1 -
 2 files changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index a63e006..26d130a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1185,7 +1185,6 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
         .dynamic_state_management_disable = smu10_disable_dpm_tasks,
         .powergate_mmhub = smu10_powergate_mmhub,
         .smus_notify_pwe = smu10_smus_notify_pwe,
-       .gfx_off_control = smu10_gfx_off_control,
         .display_clock_voltage_request = smu10_display_clock_voltage_request,
         .powergate_gfx = smu10_gfx_off_control,
 };
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 7e58a0d..88f4517 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -298,7 +298,6 @@ struct pp_hwmgr_func {
         int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
                         struct pp_display_clock_request *clock);
         int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
-       int (*gfx_off_control)(struct pp_hwmgr *hwmgr, bool enable);
         int (*power_off_asic)(struct pp_hwmgr *hwmgr);
         int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
         int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
--
1.9.1

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Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12

[Quan, Evan]

[-- Attachment #1.1: Type: text/plain, Size: 4322 bytes --]

Since the gfxoff is always in dynamic switch, i do not think the status reported to user is reliable. It means user was told the gfx is on but actually it may switches to gfxoff already.


Regards,

Evan


________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Rex Zhu <rex.zhu-5C7GfCeVMHo@public.gmane.org>
Sent: Sunday, July 29, 2018 7:42:27 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Zhu, Rex
Subject: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12

As gfx off is supported on Rv/Vega12, so this check is
helpful and necessary when visit gfx regesiter via mmio.

Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  | 10 +++++++
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 31 +++++++++++++++++++++-
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 26d130a..da1be82 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -296,6 +296,15 @@ static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
         return false;
 }

+static bool smu10_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+                               enum amd_ip_block_type client)
+{
+       if (client == AMD_IP_BLOCK_TYPE_GFX)
+               return smu10_is_gfx_on(hwmgr);
+       else /* for other ip, to do */
+               return true;
+}
+
 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
 {
         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
@@ -1187,6 +1196,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
         .smus_notify_pwe = smu10_smus_notify_pwe,
         .display_clock_voltage_request = smu10_display_clock_voltage_request,
         .powergate_gfx = smu10_gfx_off_control,
+       .is_hw_ip_on = smu10_is_hw_ip_on,
 };

 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 0789d64..ee44300 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -45,7 +45,7 @@
 #include "ppinterrupt.h"
 #include "pp_overdriver.h"
 #include "pp_thermal.h"
-
+#include "soc15_common.h"

 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
                 enum pp_clock_type type, uint32_t mask);
@@ -2320,6 +2320,34 @@ static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
         return 0;
 }

+/* GFX HW Power Status can be queried from bits [1:0] of MP1_SMN_EXT_SCRATCH0
+ * 2'b00   GFX is OFF
+ * 2'b01   Transitioning out of GFXOFF state
+ * 2'b10   GFX is ON
+ * 2'b11   Transitioning into GFXOFF state
+*/
+
+static bool vega12_is_gfx_on(struct pp_hwmgr *hwmgr)
+{
+       uint32_t tmp;
+       struct amdgpu_device *adev = hwmgr->adev;
+
+       tmp = RREG32_SOC15(MP1, 0, mmMP1_SMN_EXT_SCRATCH0);
+       if (tmp == 1 || tmp == 2)
+               return true;
+       else
+               return false;
+}
+
+static bool vega12_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+                               enum amd_ip_block_type client)
+{
+       if (client == AMD_IP_BLOCK_TYPE_GFX)
+               return vega12_is_gfx_on(hwmgr);
+       else /* for other ip, to do */
+               return true;
+}
+
 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
 {
         struct vega12_hwmgr *data =
@@ -2402,6 +2430,7 @@ static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
         .register_irq_handlers = smu9_register_irq_handlers,
         .start_thermal_controller = vega12_start_thermal_controller,
         .powergate_gfx = vega12_gfx_off_control,
+       .is_hw_ip_on = vega12_is_hw_ip_on,
 };

 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
--
1.9.1

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Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12

[Zhu, Rex]

[-- Attachment #1.1: Type: text/plain, Size: 5212 bytes --]

> It means user was told the gfx is on but actually it may switches to gfxoff already.


Correct.

So if the gfx is off, user should disable gfx off feature before they read/write the registers via mmio.

if gfx is on, that is not mean the gfx off feature is disabled. it  doesn't mean it is safe to visit the registers through mmio.


Best Regards

Rex

________________________________
From: Quan, Evan
Sent: Monday, July 30, 2018 9:31 AM
To: Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12


Since the gfxoff is always in dynamic switch, i do not think the status reported to user is reliable. It means user was told the gfx is on but actually it may switches to gfxoff already.


Regards,

Evan


________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Rex Zhu <rex.zhu-5C7GfCeVMHo@public.gmane.org>
Sent: Sunday, July 29, 2018 7:42:27 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Zhu, Rex
Subject: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12

As gfx off is supported on Rv/Vega12, so this check is
helpful and necessary when visit gfx regesiter via mmio.

Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  | 10 +++++++
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 31 +++++++++++++++++++++-
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 26d130a..da1be82 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -296,6 +296,15 @@ static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
         return false;
 }

+static bool smu10_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+                               enum amd_ip_block_type client)
+{
+       if (client == AMD_IP_BLOCK_TYPE_GFX)
+               return smu10_is_gfx_on(hwmgr);
+       else /* for other ip, to do */
+               return true;
+}
+
 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
 {
         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
@@ -1187,6 +1196,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
         .smus_notify_pwe = smu10_smus_notify_pwe,
         .display_clock_voltage_request = smu10_display_clock_voltage_request,
         .powergate_gfx = smu10_gfx_off_control,
+       .is_hw_ip_on = smu10_is_hw_ip_on,
 };

 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 0789d64..ee44300 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -45,7 +45,7 @@
 #include "ppinterrupt.h"
 #include "pp_overdriver.h"
 #include "pp_thermal.h"
-
+#include "soc15_common.h"

 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
                 enum pp_clock_type type, uint32_t mask);
@@ -2320,6 +2320,34 @@ static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
         return 0;
 }

+/* GFX HW Power Status can be queried from bits [1:0] of MP1_SMN_EXT_SCRATCH0
+ * 2'b00   GFX is OFF
+ * 2'b01   Transitioning out of GFXOFF state
+ * 2'b10   GFX is ON
+ * 2'b11   Transitioning into GFXOFF state
+*/
+
+static bool vega12_is_gfx_on(struct pp_hwmgr *hwmgr)
+{
+       uint32_t tmp;
+       struct amdgpu_device *adev = hwmgr->adev;
+
+       tmp = RREG32_SOC15(MP1, 0, mmMP1_SMN_EXT_SCRATCH0);
+       if (tmp == 1 || tmp == 2)
+               return true;
+       else
+               return false;
+}
+
+static bool vega12_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+                               enum amd_ip_block_type client)
+{
+       if (client == AMD_IP_BLOCK_TYPE_GFX)
+               return vega12_is_gfx_on(hwmgr);
+       else /* for other ip, to do */
+               return true;
+}
+
 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
 {
         struct vega12_hwmgr *data =
@@ -2402,6 +2430,7 @@ static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
         .register_irq_handlers = smu9_register_irq_handlers,
         .start_thermal_controller = vega12_start_thermal_controller,
         .powergate_gfx = vega12_gfx_off_control,
+       .is_hw_ip_on = vega12_is_hw_ip_on,
 };

 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
--
1.9.1

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Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12

[Zhu, Rex]

[-- Attachment #1.1: Type: text/plain, Size: 5767 bytes --]

Hi Alex,


Is it necessary to export an interface as "is_gfx_on" in powerplay to amdgpu?

It can show the current power state of gfx ip.



Best Regards

Rex


________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Zhu, Rex <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Sent: Monday, July 30, 2018 11:39 AM
To: Quan, Evan; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12


> It means user was told the gfx is on but actually it may switches to gfxoff already.


Correct.

So if the gfx is off, user should disable gfx off feature before they read/write the registers via mmio.

if gfx is on, that is not mean the gfx off feature is disabled. it  doesn't mean it is safe to visit the registers through mmio.


Best Regards

Rex

________________________________
From: Quan, Evan
Sent: Monday, July 30, 2018 9:31 AM
To: Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12


Since the gfxoff is always in dynamic switch, i do not think the status reported to user is reliable. It means user was told the gfx is on but actually it may switches to gfxoff already.


Regards,

Evan


________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Rex Zhu <rex.zhu-5C7GfCeVMHo@public.gmane.org>
Sent: Sunday, July 29, 2018 7:42:27 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Zhu, Rex
Subject: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12

As gfx off is supported on Rv/Vega12, so this check is
helpful and necessary when visit gfx regesiter via mmio.

Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  | 10 +++++++
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 31 +++++++++++++++++++++-
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 26d130a..da1be82 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -296,6 +296,15 @@ static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
         return false;
 }

+static bool smu10_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+                               enum amd_ip_block_type client)
+{
+       if (client == AMD_IP_BLOCK_TYPE_GFX)
+               return smu10_is_gfx_on(hwmgr);
+       else /* for other ip, to do */
+               return true;
+}
+
 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
 {
         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
@@ -1187,6 +1196,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
         .smus_notify_pwe = smu10_smus_notify_pwe,
         .display_clock_voltage_request = smu10_display_clock_voltage_request,
         .powergate_gfx = smu10_gfx_off_control,
+       .is_hw_ip_on = smu10_is_hw_ip_on,
 };

 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 0789d64..ee44300 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -45,7 +45,7 @@
 #include "ppinterrupt.h"
 #include "pp_overdriver.h"
 #include "pp_thermal.h"
-
+#include "soc15_common.h"

 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
                 enum pp_clock_type type, uint32_t mask);
@@ -2320,6 +2320,34 @@ static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
         return 0;
 }

+/* GFX HW Power Status can be queried from bits [1:0] of MP1_SMN_EXT_SCRATCH0
+ * 2'b00   GFX is OFF
+ * 2'b01   Transitioning out of GFXOFF state
+ * 2'b10   GFX is ON
+ * 2'b11   Transitioning into GFXOFF state
+*/
+
+static bool vega12_is_gfx_on(struct pp_hwmgr *hwmgr)
+{
+       uint32_t tmp;
+       struct amdgpu_device *adev = hwmgr->adev;
+
+       tmp = RREG32_SOC15(MP1, 0, mmMP1_SMN_EXT_SCRATCH0);
+       if (tmp == 1 || tmp == 2)
+               return true;
+       else
+               return false;
+}
+
+static bool vega12_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+                               enum amd_ip_block_type client)
+{
+       if (client == AMD_IP_BLOCK_TYPE_GFX)
+               return vega12_is_gfx_on(hwmgr);
+       else /* for other ip, to do */
+               return true;
+}
+
 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
 {
         struct vega12_hwmgr *data =
@@ -2402,6 +2430,7 @@ static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
         .register_irq_handlers = smu9_register_irq_handlers,
         .start_thermal_controller = vega12_start_thermal_controller,
         .powergate_gfx = vega12_gfx_off_control,
+       .is_hw_ip_on = vega12_is_hw_ip_on,
 };

 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
--
1.9.1

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Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12

[Alex Deucher]

[-- Attachment #1.1: Type: text/plain, Size: 6367 bytes --]

Does anything use it?  Might be useful for debugging, but I guess you'd
probably use something like umr in that case.

Alex

On Tue, Jul 31, 2018 at 9:15 PM, Zhu, Rex <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> wrote:

> Hi Alex,
>
>
> Is it necessary to export an interface as "is_gfx_on" in powerplay to
> amdgpu?
>
> It can show the current power state of gfx ip.
>
>
>
> Best Regards
>
> Rex
>
>
> ------------------------------
> *From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Zhu,
> Rex <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
> *Sent:* Monday, July 30, 2018 11:39 AM
> *To:* Quan, Evan; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
>
> *Subject:* Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support
> on Rv/Vega12
>
>
> > It means user was told the gfx is on but actually it may switches to
> gfxoff already.
>
>
> Correct.
>
> So if the gfx is off, user should disable gfx off feature before they
> read/write the registers via mmio.
>
> if gfx is on, that is not mean the gfx off feature is disabled. it
> doesn't mean it is safe to visit the registers through mmio.
>
>
> Best Regards
>
> Rex
>
> ------------------------------
> *From:* Quan, Evan
> *Sent:* Monday, July 30, 2018 9:31 AM
> *To:* Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> *Subject:* Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support
> on Rv/Vega12
>
>
> Since the gfxoff is always in dynamic switch, i do not think the status
> reported to user is reliable. It means user was told the gfx is on but
> actually it may switches to gfxoff already.
>
>
> Regards,
>
> Evan
>
>
> ------------------------------
> *From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Rex
> Zhu <rex.zhu-5C7GfCeVMHo@public.gmane.org>
> *Sent:* Sunday, July 29, 2018 7:42:27 PM
> *To:* amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> *Cc:* Zhu, Rex
> *Subject:* [PATCH 3/3] drm/amd/pp: Add gfx power status check support on
> Rv/Vega12
>
> As gfx off is supported on Rv/Vega12, so this check is
> helpful and necessary when visit gfx regesiter via mmio.
>
> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  | 10 +++++++
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 31
> +++++++++++++++++++++-
>  2 files changed, 40 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index 26d130a..da1be82 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -296,6 +296,15 @@ static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
>          return false;
>  }
>
> +static bool smu10_is_hw_ip_on(struct pp_hwmgr *hwmgr,
> +                               enum amd_ip_block_type client)
> +{
> +       if (client == AMD_IP_BLOCK_TYPE_GFX)
> +               return smu10_is_gfx_on(hwmgr);
> +       else /* for other ip, to do */
> +               return true;
> +}
> +
>  static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
>  {
>          struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr
> *)(hwmgr->backend);
> @@ -1187,6 +1196,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr
> *hwmgr, bool bgate)
>          .smus_notify_pwe = smu10_smus_notify_pwe,
>          .display_clock_voltage_request = smu10_display_clock_voltage_
> request,
>          .powergate_gfx = smu10_gfx_off_control,
> +       .is_hw_ip_on = smu10_is_hw_ip_on,
>  };
>
>  int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 0789d64..ee44300 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -45,7 +45,7 @@
>  #include "ppinterrupt.h"
>  #include "pp_overdriver.h"
>  #include "pp_thermal.h"
> -
> +#include "soc15_common.h"
>
>  static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
>                  enum pp_clock_type type, uint32_t mask);
> @@ -2320,6 +2320,34 @@ static int vega12_get_thermal_temperature_range(struct
> pp_hwmgr *hwmgr,
>          return 0;
>  }
>
> +/* GFX HW Power Status can be queried from bits [1:0] of
> MP1_SMN_EXT_SCRATCH0
> + * 2'b00   GFX is OFF
> + * 2'b01   Transitioning out of GFXOFF state
> + * 2'b10   GFX is ON
> + * 2'b11   Transitioning into GFXOFF state
> +*/
> +
> +static bool vega12_is_gfx_on(struct pp_hwmgr *hwmgr)
> +{
> +       uint32_t tmp;
> +       struct amdgpu_device *adev = hwmgr->adev;
> +
> +       tmp = RREG32_SOC15(MP1, 0, mmMP1_SMN_EXT_SCRATCH0);
> +       if (tmp == 1 || tmp == 2)
> +               return true;
> +       else
> +               return false;
> +}
> +
> +static bool vega12_is_hw_ip_on(struct pp_hwmgr *hwmgr,
> +                               enum amd_ip_block_type client)
> +{
> +       if (client == AMD_IP_BLOCK_TYPE_GFX)
> +               return vega12_is_gfx_on(hwmgr);
> +       else /* for other ip, to do */
> +               return true;
> +}
> +
>  static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
>  {
>          struct vega12_hwmgr *data =
> @@ -2402,6 +2430,7 @@ static int vega12_gfx_off_control(struct pp_hwmgr
> *hwmgr, bool enable)
>          .register_irq_handlers = smu9_register_irq_handlers,
>          .start_thermal_controller = vega12_start_thermal_controller,
>          .powergate_gfx = vega12_gfx_off_control,
> +       .is_hw_ip_on = vega12_is_hw_ip_on,
>  };
>
>  int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> amd-gfx Info Page - freedesktop.org
> <https://lists.freedesktop.org/mailman/listinfo/amd-gfx>
> lists.freedesktop.org
> Subscribing to amd-gfx: Subscribe to amd-gfx by filling out the following
> form. Use of all freedesktop.org lists is subject to our Code of Conduct.
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>

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Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12

[Zhu, Rex]

[-- Attachment #1.1: Type: text/plain, Size: 7293 bytes --]

Currently, there is no use case except for debug.

So I will keep the patches in my local.

Thanks.



Best Regards

Rex



________________________________
From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Wednesday, August 1, 2018 11:13 PM
To: Zhu, Rex
Cc: Deucher, Alexander; Quan, Evan; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12

Does anything use it?  Might be useful for debugging, but I guess you'd probably use something like umr in that case.

Alex

On Tue, Jul 31, 2018 at 9:15 PM, Zhu, Rex <Rex.Zhu-5C7GfCeVMHo@public.gmane.org<mailto:Rex.Zhu@amd.com>> wrote:

Hi Alex,


Is it necessary to export an interface as "is_gfx_on" in powerplay to amdgpu?

It can show the current power state of gfx ip.



Best Regards

Rex


________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of Zhu, Rex <Rex.Zhu-5C7GfCeVMHo@public.gmane.org<mailto:Rex.Zhu-5C7GfCeVMHo@public.gmane.org>>
Sent: Monday, July 30, 2018 11:39 AM
To: Quan, Evan; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lzq7FAFJ/aeQ@public.gmane.orgtop.org>

Subject: Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12


> It means user was told the gfx is on but actually it may switches to gfxoff already.


Correct.

So if the gfx is off, user should disable gfx off feature before they read/write the registers via mmio.

if gfx is on, that is not mean the gfx off feature is disabled. it  doesn't mean it is safe to visit the registers through mmio.


Best Regards

Rex

________________________________
From: Quan, Evan
Sent: Monday, July 30, 2018 9:31 AM
To: Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9w@public.gmane.orgp.org>
Subject: Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12


Since the gfxoff is always in dynamic switch, i do not think the status reported to user is reliable. It means user was told the gfx is on but actually it may switches to gfxoff already.


Regards,

Evan


________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of Rex Zhu <rex.zhu-5C7GfCeVMHo@public.gmane.org<mailto:rex.zhu-5C7GfCeVMHo@public.gmane.org>>
Sent: Sunday, July 29, 2018 7:42:27 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Zhu, Rex
Subject: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12

As gfx off is supported on Rv/Vega12, so this check is
helpful and necessary when visit gfx regesiter via mmio.

Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org<mailto:Rex.Zhu-5C7GfCeVMHo@public.gmane.org>>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  | 10 +++++++
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 31 +++++++++++++++++++++-
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 26d130a..da1be82 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -296,6 +296,15 @@ static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
         return false;
 }

+static bool smu10_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+                               enum amd_ip_block_type client)
+{
+       if (client == AMD_IP_BLOCK_TYPE_GFX)
+               return smu10_is_gfx_on(hwmgr);
+       else /* for other ip, to do */
+               return true;
+}
+
 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
 {
         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
@@ -1187,6 +1196,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
         .smus_notify_pwe = smu10_smus_notify_pwe,
         .display_clock_voltage_request = smu10_display_clock_voltage_request,
         .powergate_gfx = smu10_gfx_off_control,
+       .is_hw_ip_on = smu10_is_hw_ip_on,
 };

 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 0789d64..ee44300 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -45,7 +45,7 @@
 #include "ppinterrupt.h"
 #include "pp_overdriver.h"
 #include "pp_thermal.h"
-
+#include "soc15_common.h"

 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
                 enum pp_clock_type type, uint32_t mask);
@@ -2320,6 +2320,34 @@ static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
         return 0;
 }

+/* GFX HW Power Status can be queried from bits [1:0] of MP1_SMN_EXT_SCRATCH0
+ * 2'b00   GFX is OFF
+ * 2'b01   Transitioning out of GFXOFF state
+ * 2'b10   GFX is ON
+ * 2'b11   Transitioning into GFXOFF state
+*/
+
+static bool vega12_is_gfx_on(struct pp_hwmgr *hwmgr)
+{
+       uint32_t tmp;
+       struct amdgpu_device *adev = hwmgr->adev;
+
+       tmp = RREG32_SOC15(MP1, 0, mmMP1_SMN_EXT_SCRATCH0);
+       if (tmp == 1 || tmp == 2)
+               return true;
+       else
+               return false;
+}
+
+static bool vega12_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+                               enum amd_ip_block_type client)
+{
+       if (client == AMD_IP_BLOCK_TYPE_GFX)
+               return vega12_is_gfx_on(hwmgr);
+       else /* for other ip, to do */
+               return true;
+}
+
 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
 {
         struct vega12_hwmgr *data =
@@ -2402,6 +2430,7 @@ static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
         .register_irq_handlers = smu9_register_irq_handlers,
         .start_thermal_controller = vega12_start_thermal_controller,
         .powergate_gfx = vega12_gfx_off_control,
+       .is_hw_ip_on = vega12_is_hw_ip_on,
 };

 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
--
1.9.1

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Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12

[Alex Deucher]

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If you use them enough for debugging that you think it's better to have
them in tree, feel free to commit them.  Maybe just add a note that they
are just for debugging and add a note about the race condition.

Alex


On Thu, Aug 2, 2018 at 6:22 AM, Zhu, Rex <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> wrote:

> Currently, there is no use case except for debug.
>
> So I will keep the patches in my local.
>
> Thanks.
>
>
>
> Best Regards
>
> Rex
>
>
>
>
> ------------------------------
> *From:* Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> *Sent:* Wednesday, August 1, 2018 11:13 PM
> *To:* Zhu, Rex
> *Cc:* Deucher, Alexander; Quan, Evan; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
>
> *Subject:* Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support
> on Rv/Vega12
>
> Does anything use it?  Might be useful for debugging, but I guess you'd
> probably use something like umr in that case.
>
> Alex
>
> On Tue, Jul 31, 2018 at 9:15 PM, Zhu, Rex <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> wrote:
>
> Hi Alex,
>
>
> Is it necessary to export an interface as "is_gfx_on" in powerplay to
> amdgpu?
>
> It can show the current power state of gfx ip.
>
>
>
> Best Regards
>
> Rex
>
>
> ------------------------------
> *From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Zhu,
> Rex <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
> *Sent:* Monday, July 30, 2018 11:39 AM
> *To:* Quan, Evan; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
>
> *Subject:* Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support
> on Rv/Vega12
>
>
> > It means user was told the gfx is on but actually it may switches to
> gfxoff already.
>
>
> Correct.
>
> So if the gfx is off, user should disable gfx off feature before they
> read/write the registers via mmio.
>
> if gfx is on, that is not mean the gfx off feature is disabled. it
> doesn't mean it is safe to visit the registers through mmio.
>
>
> Best Regards
>
> Rex
>
> ------------------------------
> *From:* Quan, Evan
> *Sent:* Monday, July 30, 2018 9:31 AM
> *To:* Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> *Subject:* Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support
> on Rv/Vega12
>
>
> Since the gfxoff is always in dynamic switch, i do not think the status
> reported to user is reliable. It means user was told the gfx is on but
> actually it may switches to gfxoff already.
>
>
> Regards,
>
> Evan
>
>
> ------------------------------
> *From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Rex
> Zhu <rex.zhu-5C7GfCeVMHo@public.gmane.org>
> *Sent:* Sunday, July 29, 2018 7:42:27 PM
> *To:* amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> *Cc:* Zhu, Rex
> *Subject:* [PATCH 3/3] drm/amd/pp: Add gfx power status check support on
> Rv/Vega12
>
> As gfx off is supported on Rv/Vega12, so this check is
> helpful and necessary when visit gfx regesiter via mmio.
>
> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  | 10 +++++++
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 31
> +++++++++++++++++++++-
>  2 files changed, 40 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index 26d130a..da1be82 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -296,6 +296,15 @@ static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
>          return false;
>  }
>
> +static bool smu10_is_hw_ip_on(struct pp_hwmgr *hwmgr,
> +                               enum amd_ip_block_type client)
> +{
> +       if (client == AMD_IP_BLOCK_TYPE_GFX)
> +               return smu10_is_gfx_on(hwmgr);
> +       else /* for other ip, to do */
> +               return true;
> +}
> +
>  static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
>  {
>          struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr
> *)(hwmgr->backend);
> @@ -1187,6 +1196,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr
> *hwmgr, bool bgate)
>          .smus_notify_pwe = smu10_smus_notify_pwe,
>          .display_clock_voltage_request = smu10_display_clock_voltage_re
> quest,
>          .powergate_gfx = smu10_gfx_off_control,
> +       .is_hw_ip_on = smu10_is_hw_ip_on,
>  };
>
>  int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 0789d64..ee44300 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -45,7 +45,7 @@
>  #include "ppinterrupt.h"
>  #include "pp_overdriver.h"
>  #include "pp_thermal.h"
> -
> +#include "soc15_common.h"
>
>  static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
>                  enum pp_clock_type type, uint32_t mask);
> @@ -2320,6 +2320,34 @@ static int vega12_get_thermal_temperature_range(struct
> pp_hwmgr *hwmgr,
>          return 0;
>  }
>
> +/* GFX HW Power Status can be queried from bits [1:0] of
> MP1_SMN_EXT_SCRATCH0
> + * 2'b00   GFX is OFF
> + * 2'b01   Transitioning out of GFXOFF state
> + * 2'b10   GFX is ON
> + * 2'b11   Transitioning into GFXOFF state
> +*/
> +
> +static bool vega12_is_gfx_on(struct pp_hwmgr *hwmgr)
> +{
> +       uint32_t tmp;
> +       struct amdgpu_device *adev = hwmgr->adev;
> +
> +       tmp = RREG32_SOC15(MP1, 0, mmMP1_SMN_EXT_SCRATCH0);
> +       if (tmp == 1 || tmp == 2)
> +               return true;
> +       else
> +               return false;
> +}
> +
> +static bool vega12_is_hw_ip_on(struct pp_hwmgr *hwmgr,
> +                               enum amd_ip_block_type client)
> +{
> +       if (client == AMD_IP_BLOCK_TYPE_GFX)
> +               return vega12_is_gfx_on(hwmgr);
> +       else /* for other ip, to do */
> +               return true;
> +}
> +
>  static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
>  {
>          struct vega12_hwmgr *data =
> @@ -2402,6 +2430,7 @@ static int vega12_gfx_off_control(struct pp_hwmgr
> *hwmgr, bool enable)
>          .register_irq_handlers = smu9_register_irq_handlers,
>          .start_thermal_controller = vega12_start_thermal_controller,
>          .powergate_gfx = vega12_gfx_off_control,
> +       .is_hw_ip_on = vega12_is_hw_ip_on,
>  };
>
>  int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
> --
> 1.9.1
>
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