From mboxrd@z Thu Jan 1 00:00:00 1970 From: "StDenis, Tom" Subject: Re: [PATCH 1/2] drm/amd/powerplay: Add read_sensor() callback to hwmgr (v3) Date: Mon, 19 Sep 2016 15:54:59 +0000 Message-ID: References: <20160919131023.30064-1-tom.stdenis@amd.com> <20160919131023.30064-2-tom.stdenis@amd.com>, Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0321915723==" Return-path: In-Reply-To: Content-Language: en-US List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: Alex Deucher Cc: amd-gfx list --===============0321915723== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_CY4PR12MB17688AA3886A61A51BE31262F7F40CY4PR12MB1768namp_" --_000_CY4PR12MB17688AA3886A61A51BE31262F7F40CY4PR12MB1768namp_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi Alex, Would you prefer I re-write #1 to avoid churn in the tree? Cheers, Tom ________________________________ From: Alex Deucher Sent: Monday, September 19, 2016 11:53 To: Tom St Denis Cc: amd-gfx list; StDenis, Tom Subject: Re: [PATCH 1/2] drm/amd/powerplay: Add read_sensor() callback to h= wmgr (v3) On Mon, Sep 19, 2016 at 9:10 AM, Tom St Denis wrote: > Provides standardized interface to read various sensors. > The API is extensible (by adding to the end of the > amd_pp_sensors enumeration list. > > Support has been added to Carrizo/smu7 > > (v2) Squashed the two sensor patches into one. > (v3) Updated to apply to smu7_hwmgr instead > > Signed-off-by: Tom St Denis > --- > drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 20 +++++ > drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 96 +++++++++++++++++= ++++++ > drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 36 +++++++++ > drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 12 +++ > drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 + > 5 files changed, 165 insertions(+) > > diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/= drm/amd/powerplay/amd_powerplay.c > index b1d19409bf86..ee0368381e82 100644 > --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > @@ -894,6 +894,25 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t= value) > return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value); > } > > +static int pp_dpm_read_sensor(void *handle, int idx, int32_t *value) > +{ > + struct pp_hwmgr *hwmgr; > + > + if (!handle) > + return -EINVAL; > + > + hwmgr =3D ((struct pp_instance *)handle)->hwmgr; > + > + PP_CHECK_HW(hwmgr); > + > + if (hwmgr->hwmgr_func->read_sensor =3D=3D NULL) { > + printk(KERN_INFO "%s was not implemented.\n", __func__); > + return 0; > + } > + > + return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value); > +} > + > const struct amd_powerplay_funcs pp_dpm_funcs =3D { > .get_temperature =3D pp_dpm_get_temperature, > .load_firmware =3D pp_dpm_load_fw, > @@ -920,6 +939,7 @@ const struct amd_powerplay_funcs pp_dpm_funcs =3D { > .set_sclk_od =3D pp_dpm_set_sclk_od, > .get_mclk_od =3D pp_dpm_get_mclk_od, > .set_mclk_od =3D pp_dpm_set_mclk_od, > + .read_sensor =3D pp_dpm_read_sensor, As a future patch it would be nice to hook up this sensor interface to the existing amdgpu_pm_info code and make that asic indpendent. Series is: Reviewed-by: Alex Deucher Alex > }; > > static int amd_pp_instance_init(struct amd_pp_init *pp_init, > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu= /drm/amd/powerplay/hwmgr/cz_hwmgr.c > index 5ecef1732e20..9f3c5a8a903c 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c > @@ -1857,6 +1857,101 @@ static int cz_get_max_high_clocks(struct pp_hwmgr= *hwmgr, struct amd_pp_simple_c > return 0; > } > > +static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *valu= e) > +{ > + struct cz_hwmgr *cz_hwmgr =3D (struct cz_hwmgr *)(hwmgr->backend)= ; > + > + struct phm_clock_voltage_dependency_table *table =3D > + hwmgr->dyn_state.vddc_dependency_on_sclk; > + > + struct phm_vce_clock_voltage_dependency_table *vce_table =3D > + hwmgr->dyn_state.vce_clock_voltage_dependency_table; > + > + struct phm_uvd_clock_voltage_dependency_table *uvd_table =3D > + hwmgr->dyn_state.uvd_clock_voltage_dependency_table; > + > + uint32_t sclk_index =3D PHM_GET_FIELD(cgs_read_ind_register(hwmgr= ->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX), > + TARGET_AND_CURRENT_PROFILE_INDEX,= CURR_SCLK_INDEX); > + uint32_t uvd_index =3D PHM_GET_FIELD(cgs_read_ind_register(hwmgr-= >device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2), > + TARGET_AND_CURRENT_PROFILE_INDEX_= 2, CURR_UVD_INDEX); > + uint32_t vce_index =3D PHM_GET_FIELD(cgs_read_ind_register(hwmgr-= >device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2), > + TARGET_AND_CURRENT_PROFILE_INDEX_= 2, CURR_VCE_INDEX); > + > + uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; > + uint16_t vddnb, vddgfx; > + int result; > + > + switch (idx) { > + case AMDGPU_PP_SENSOR_GFX_SCLK: > + if (sclk_index < NUM_SCLK_LEVELS) { > + sclk =3D table->entries[sclk_index].clk; > + *value =3D sclk; > + return 0; > + } > + return -EINVAL; > + case AMDGPU_PP_SENSOR_VDDNB: > + tmp =3D (cgs_read_ind_register(hwmgr->device, CGS_IND_REG= __SMC, ixSMUSVI_NB_CURRENTVID) & > + CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT; > + vddnb =3D cz_convert_8Bit_index_to_voltage(hwmgr, tmp); > + *value =3D vddnb; > + return 0; > + case AMDGPU_PP_SENSOR_VDDGFX: > + tmp =3D (cgs_read_ind_register(hwmgr->device, CGS_IND_REG= __SMC, ixSMUSVI_GFX_CURRENTVID) & > + CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT; > + vddgfx =3D cz_convert_8Bit_index_to_voltage(hwmgr, (u16)t= mp); > + *value =3D vddgfx; > + return 0; > + case AMDGPU_PP_SENSOR_UVD_VCLK: > + if (!cz_hwmgr->uvd_power_gated) { > + if (uvd_index >=3D CZ_MAX_HARDWARE_POWERLEVELS) { > + return -EINVAL; > + } else { > + vclk =3D uvd_table->entries[uvd_index].vc= lk; > + *value =3D vclk; > + return 0; > + } > + } > + *value =3D 0; > + return 0; > + case AMDGPU_PP_SENSOR_UVD_DCLK: > + if (!cz_hwmgr->uvd_power_gated) { > + if (uvd_index >=3D CZ_MAX_HARDWARE_POWERLEVELS) { > + return -EINVAL; > + } else { > + dclk =3D uvd_table->entries[uvd_index].dc= lk; > + *value =3D dclk; > + return 0; > + } > + } > + *value =3D 0; > + return 0; > + case AMDGPU_PP_SENSOR_VCE_ECCLK: > + if (!cz_hwmgr->vce_power_gated) { > + if (vce_index >=3D CZ_MAX_HARDWARE_POWERLEVELS) { > + return -EINVAL; > + } else { > + ecclk =3D vce_table->entries[vce_index].e= cclk; > + *value =3D ecclk; > + return 0; > + } > + } > + *value =3D 0; > + return 0; > + case AMDGPU_PP_SENSOR_GPU_LOAD: > + result =3D smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_= GetAverageGraphicsActivity); > + if (0 =3D=3D result) { > + activity_percent =3D cgs_read_register(hwmgr->dev= ice, mmSMU_MP1_SRBM2P_ARG_0); > + activity_percent =3D activity_percent > 100 ? 100= : activity_percent; > + } else { > + activity_percent =3D 50; > + } > + *value =3D activity_percent; > + return 0; > + default: > + return -EINVAL; > + } > +} > + > static const struct pp_hwmgr_func cz_hwmgr_funcs =3D { > .backend_init =3D cz_hwmgr_backend_init, > .backend_fini =3D cz_hwmgr_backend_fini, > @@ -1882,6 +1977,7 @@ static const struct pp_hwmgr_func cz_hwmgr_funcs = =3D { > .get_current_shallow_sleep_clocks =3D cz_get_current_shallow_slee= p_clocks, > .get_clock_by_type =3D cz_get_clock_by_type, > .get_max_high_clocks =3D cz_get_max_high_clocks, > + .read_sensor =3D cz_read_sensor, > }; > > int cz_hwmgr_init(struct pp_hwmgr *hwmgr) > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/g= pu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > index f67e1e260b30..07a7d046d6f6 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > @@ -3144,6 +3144,41 @@ smu7_print_current_perforce_level(struct pp_hwmgr = *hwmgr, struct seq_file *m) > seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" := "en"); > } > > +static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *va= lue) > +{ > + uint32_t sclk, mclk, activity_percent; > + uint32_t offset; > + struct smu7_hwmgr *data =3D (struct smu7_hwmgr *)(hwmgr->backend)= ; > + > + switch (idx) { > + case AMDGPU_PP_SENSOR_GFX_SCLK: > + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclk= Frequency); > + sclk =3D cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0= ); > + *value =3D sclk; > + return 0; > + case AMDGPU_PP_SENSOR_GFX_MCLK: > + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclk= Frequency); > + mclk =3D cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0= ); > + *value =3D mclk; > + return 0; > + case AMDGPU_PP_SENSOR_GPU_LOAD: > + offset =3D data->soft_regs_start + smum_get_offsetof(hwmg= r->smumgr, > + SMU_SoftR= egisters, > + AverageGr= aphicsActivity); > + > + activity_percent =3D cgs_read_ind_register(hwmgr->device,= CGS_IND_REG__SMC, offset); > + activity_percent +=3D 0x80; > + activity_percent >>=3D 8; > + *value =3D activity_percent > 100 ? 100 : activity_percen= t; > + return 0; > + case AMDGPU_PP_SENSOR_GPU_TEMP: > + *value =3D smu7_thermal_get_temperature(hwmgr); > + return 0; > + default: > + return -EINVAL; > + } > +} > + > static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwm= gr, const void *input) > { > const struct phm_set_power_state_input *states =3D > @@ -4315,6 +4350,7 @@ static struct pp_hwmgr_func smu7_hwmgr_funcs =3D { > .get_mclk_od =3D smu7_get_mclk_od, > .set_mclk_od =3D smu7_set_mclk_od, > .get_clock_by_type =3D smu7_get_clock_by_type, > + .read_sensor =3D smu7_read_sensor, > }; > > uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, > diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/= gpu/drm/amd/powerplay/inc/amd_powerplay.h > index f941acf563a9..dfa0f38a5e76 100644 > --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h > +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h > @@ -29,6 +29,17 @@ > #include "amd_shared.h" > #include "cgs_common.h" > > +enum amd_pp_sensors { > + AMDGPU_PP_SENSOR_GFX_SCLK =3D 0, > + AMDGPU_PP_SENSOR_VDDNB, > + AMDGPU_PP_SENSOR_VDDGFX, > + AMDGPU_PP_SENSOR_UVD_VCLK, > + AMDGPU_PP_SENSOR_UVD_DCLK, > + AMDGPU_PP_SENSOR_VCE_ECCLK, > + AMDGPU_PP_SENSOR_GPU_LOAD, > + AMDGPU_PP_SENSOR_GFX_MCLK, > + AMDGPU_PP_SENSOR_GPU_TEMP, > +}; > > enum amd_pp_event { > AMD_PP_EVENT_INITIALIZE =3D 0, > @@ -347,6 +358,7 @@ struct amd_powerplay_funcs { > int (*set_sclk_od)(void *handle, uint32_t value); > int (*get_mclk_od)(void *handle); > int (*set_mclk_od)(void *handle, uint32_t value); > + int (*read_sensor)(void *handle, int idx, int32_t *value); > }; > > struct amd_powerplay { > diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/= amd/powerplay/inc/hwmgr.h > index c9628b4db2c3..fcd45452380d 100644 > --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h > +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h > @@ -359,6 +359,7 @@ struct pp_hwmgr_func { > int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); > int (*get_mclk_od)(struct pp_hwmgr *hwmgr); > int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); > + int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, int32_t *valu= e); > }; > > struct pp_table_func { > -- > 2.10.0 > > _______________________________________________ > amd-gfx mailing list > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx amd-gfx Info Page - lists.freedesktop.org lists.freedesktop.org To see the collection of prior postings to the list, visit the amd-gfx Arch= ives. Using amd-gfx: To post a message to all the list members, send email = ... --_000_CY4PR12MB17688AA3886A61A51BE31262F7F40CY4PR12MB1768namp_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Hi Alex,


Would you prefer I re-write #1 to avoid churn in the tree?


Cheers,

Tom



From: Alex Deucher <al= exdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Monday, September 19, 2016 11:53
To: Tom St Denis
Cc: amd-gfx list; StDenis, Tom
Subject: Re: [PATCH 1/2] drm/amd/powerplay: Add read_sensor() callba= ck to hwmgr (v3)
 
On Mon, Sep 19, 2016 at 9:10 AM, Tom St Denis <= tstdenis82-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Provides standardized interface to read various sensors.
> The API is extensible (by adding to the end of the
> amd_pp_sensors enumeration list.
>
> Support has been added to Carrizo/smu7
>
> (v2) Squashed the two sensor patches into one.
> (v3) Updated to apply to smu7_hwmgr instead
>
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c   &= nbsp; | 20 +++++
>  drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c   = | 96 ++++++++++++++= ;+++++++++
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c  | 36 += ;++++++++
>  drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 12 ++= ;+
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h    = ;     |  1 +
>  5 files changed, 165 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/g= pu/drm/amd/powerplay/amd_powerplay.c
> index b1d19409bf86..ee0368381e82 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -894,6 +894,25 @@ static int pp_dpm_set_mclk_od(void *handle, u= int32_t value)
>         return hwmgr->hwmgr= _func->set_mclk_od(hwmgr, value);
>  }
>
> +static int pp_dpm_read_sensor(void *handle, int idx, int32_t *val= ue)
> +{
> +       struct pp_hwmgr *hwmgr;
> +
> +       if (!handle)
> +           = ;    return -EINVAL;
> +
> +       hwmgr =3D ((struct pp_instan= ce *)handle)->hwmgr;
> +
> +       PP_CHECK_HW(hwmgr);
> +
> +       if (hwmgr->hwmgr_func->= ;read_sensor =3D=3D NULL) {
> +           = ;    printk(KERN_INFO "%s was not implemented.\n",= __func__);
> +           = ;    return 0;
> +       }
> +
> +       return hwmgr->hwmgr_func-= >read_sensor(hwmgr, idx, value);
> +}
> +
>  const struct amd_powerplay_funcs pp_dpm_funcs =3D {
>         .get_temperature =3D p= p_dpm_get_temperature,
>         .load_firmware =3D pp_= dpm_load_fw,
> @@ -920,6 +939,7 @@ const struct amd_powerplay_funcs pp_dpm_funcs = =3D {
>         .set_sclk_od =3D pp_dp= m_set_sclk_od,
>         .get_mclk_od =3D pp_dp= m_get_mclk_od,
>         .set_mclk_od =3D pp_dp= m_set_mclk_od,
> +       .read_sensor =3D pp_dpm_read= _sensor,

As a future patch it would be nice to hook up this sensor interface to
the existing amdgpu_pm_info code and make that asic indpendent.

Series is:
Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>

Alex


>  };
>
>  static int amd_pp_instance_init(struct amd_pp_init *pp_init,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/= gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> index 5ecef1732e20..9f3c5a8a903c 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> @@ -1857,6 +1857,101 @@ static int cz_get_max_high_clocks(struct p= p_hwmgr *hwmgr, struct amd_pp_simple_c
>         return 0;
>  }
>
> +static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_= t *value)
> +{
> +       struct cz_hwmgr *cz_hwmgr = =3D (struct cz_hwmgr *)(hwmgr->backend);
> +
> +       struct phm_clock_voltage_dep= endency_table *table =3D
> +           = ;            &n= bsp;       hwmgr->dyn_state.vddc_dependenc= y_on_sclk;
> +
> +       struct phm_vce_clock_voltage= _dependency_table *vce_table =3D
> +           = ;    hwmgr->dyn_state.vce_clock_voltage_dependency_table;=
> +
> +       struct phm_uvd_clock_voltage= _dependency_table *uvd_table =3D
> +           = ;    hwmgr->dyn_state.uvd_clock_voltage_dependency_table;=
> +
> +       uint32_t sclk_index =3D PHM_= GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGE= T_AND_CURRENT_PROFILE_INDEX),
> +           = ;            &n= bsp;            = ;   TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
> +       uint32_t uvd_index =3D PHM_G= ET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET= _AND_CURRENT_PROFILE_INDEX_2),
> +           = ;            &n= bsp;            = ;   TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
> +       uint32_t vce_index =3D PHM_G= ET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET= _AND_CURRENT_PROFILE_INDEX_2),
> +           = ;            &n= bsp;            = ;   TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
> +
> +       uint32_t sclk, vclk, dclk, e= cclk, tmp, activity_percent;
> +       uint16_t vddnb, vddgfx;
> +       int result;
> +
> +       switch (idx) {
> +       case AMDGPU_PP_SENSOR_GFX_SC= LK:
> +           = ;    if (sclk_index < NUM_SCLK_LEVELS) {
> +           = ;            sclk = =3D table->entries[sclk_index].clk;
> +           = ;            *value = =3D sclk;
> +           = ;            return = 0;
> +           = ;    }
> +           = ;    return -EINVAL;
> +       case AMDGPU_PP_SENSOR_VDDNB:=
> +           = ;    tmp =3D (cgs_read_ind_register(hwmgr->device, CGS_IN= D_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
> +           = ;            CURRENT= _NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
> +           = ;    vddnb =3D cz_convert_8Bit_index_to_voltage(hwmgr, tmp);=
> +           = ;    *value =3D vddnb;
> +           = ;    return 0;
> +       case AMDGPU_PP_SENSOR_VDDGFX= :
> +           = ;    tmp =3D (cgs_read_ind_register(hwmgr->device, CGS_IN= D_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
> +           = ;            CURRENT= _GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
> +           = ;    vddgfx =3D cz_convert_8Bit_index_to_voltage(hwmgr, (u16= )tmp);
> +           = ;    *value =3D vddgfx;
> +           = ;    return 0;
> +       case AMDGPU_PP_SENSOR_UVD_VC= LK:
> +           = ;    if (!cz_hwmgr->uvd_power_gated) {
> +           = ;            if (uvd= _index >=3D CZ_MAX_HARDWARE_POWERLEVELS) {
> +           = ;            &n= bsp;       return -EINVAL;
> +           = ;            } else = {
> +           = ;            &n= bsp;       vclk =3D uvd_table->entries[uvd= _index].vclk;
> +           = ;            &n= bsp;       *value =3D vclk;
> +           = ;            &n= bsp;       return 0;
> +           = ;            }
> +           = ;    }
> +           = ;    *value =3D 0;
> +           = ;    return 0;
> +       case AMDGPU_PP_SENSOR_UVD_DC= LK:
> +           = ;    if (!cz_hwmgr->uvd_power_gated) {
> +           = ;            if (uvd= _index >=3D CZ_MAX_HARDWARE_POWERLEVELS) {
> +           = ;            &n= bsp;       return -EINVAL;
> +           = ;            } else = {
> +           = ;            &n= bsp;       dclk =3D uvd_table->entries[uvd= _index].dclk;
> +           = ;            &n= bsp;       *value =3D dclk;
> +           = ;            &n= bsp;       return 0;
> +           = ;            }
> +           = ;    }
> +           = ;    *value =3D 0;
> +           = ;    return 0;
> +       case AMDGPU_PP_SENSOR_VCE_EC= CLK:
> +           = ;    if (!cz_hwmgr->vce_power_gated) {
> +           = ;            if (vce= _index >=3D CZ_MAX_HARDWARE_POWERLEVELS) {
> +           = ;            &n= bsp;       return -EINVAL;
> +           = ;            } else = {
> +           = ;            &n= bsp;       ecclk =3D vce_table->entries[vc= e_index].ecclk;
> +           = ;            &n= bsp;       *value =3D ecclk;
> +           = ;            &n= bsp;       return 0;
> +           = ;            }
> +           = ;    }
> +           = ;    *value =3D 0;
> +           = ;    return 0;
> +       case AMDGPU_PP_SENSOR_GPU_LO= AD:
> +           = ;    result =3D smum_send_msg_to_smc(hwmgr->smumgr, PPSMC= _MSG_GetAverageGraphicsActivity);
> +           = ;    if (0 =3D=3D result) {
> +           = ;            activit= y_percent =3D cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);<= br> > +           = ;            activit= y_percent =3D activity_percent > 100 ? 100 : activity_percent;
> +           = ;    } else {
> +           = ;            activit= y_percent =3D 50;
> +           = ;    }
> +           = ;    *value =3D activity_percent;
> +           = ;    return 0;
> +       default:
> +           = ;    return -EINVAL;
> +       }
> +}
> +
>  static const struct pp_hwmgr_func cz_hwmgr_funcs =3D {
>         .backend_init =3D cz_h= wmgr_backend_init,
>         .backend_fini =3D cz_h= wmgr_backend_fini,
> @@ -1882,6 +1977,7 @@ static const struct pp_hwmgr_func cz_hwmgr_f= uncs =3D {
>         .get_current_shallow_s= leep_clocks =3D cz_get_current_shallow_sleep_clocks,
>         .get_clock_by_type =3D= cz_get_clock_by_type,
>         .get_max_high_clocks = =3D cz_get_max_high_clocks,
> +       .read_sensor =3D cz_read_sen= sor,
>  };
>
>  int cz_hwmgr_init(struct pp_hwmgr *hwmgr)
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/driver= s/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index f67e1e260b30..07a7d046d6f6 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3144,6 +3144,41 @@ smu7_print_current_perforce_level(struct pp= _hwmgr *hwmgr, struct seq_file *m)
>         seq_printf(m, "vc= e    %sabled\n", data->vce_power_gated ? "dis&q= uot; : "en");
>  }
>
> +static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, int3= 2_t *value)
> +{
> +       uint32_t sclk, mclk, activit= y_percent;
> +       uint32_t offset;
> +       struct smu7_hwmgr *data =3D = (struct smu7_hwmgr *)(hwmgr->backend);
> +
> +       switch (idx) {
> +       case AMDGPU_PP_SENSOR_GFX_SC= LK:
> +           = ;    smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_Ge= tSclkFrequency);
> +           = ;    sclk =3D cgs_read_register(hwmgr->device, mmSMC_MSG_= ARG_0);
> +           = ;    *value =3D sclk;
> +           = ;    return 0;
> +       case AMDGPU_PP_SENSOR_GFX_MC= LK:
> +           = ;    smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_Ge= tMclkFrequency);
> +           = ;    mclk =3D cgs_read_register(hwmgr->device, mmSMC_MSG_= ARG_0);
> +           = ;    *value =3D mclk;
> +           = ;    return 0;
> +       case AMDGPU_PP_SENSOR_GPU_LO= AD:
> +           = ;    offset =3D data->soft_regs_start + smum_get_offs= etof(hwmgr->smumgr,
> +           = ;            &n= bsp;            = ;            &n= bsp;            = ;  SMU_SoftRegisters,
> +           = ;            &n= bsp;            = ;            &n= bsp;            = ;  AverageGraphicsActivity);
> +
> +           = ;    activity_percent =3D cgs_read_ind_register(hwmgr->de= vice, CGS_IND_REG__SMC, offset);
> +           = ;    activity_percent +=3D 0x80;
> +           = ;    activity_percent >>=3D 8;
> +           = ;    *value =3D activity_percent > 100 ? 100 : activity_p= ercent;
> +           = ;    return 0;
> +       case AMDGPU_PP_SENSOR_GPU_TE= MP:
> +           = ;    *value =3D smu7_thermal_get_temperature(hwmgr);
> +           = ;    return 0;
> +       default:
> +           = ;    return -EINVAL;
> +       }
> +}
> +
>  static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hw= mgr *hwmgr, const void *input)
>  {
>         const struct phm_set_p= ower_state_input *states =3D
> @@ -4315,6 +4350,7 @@ static struct pp_hwmgr_func smu7_hwmgr_funcs= =3D {
>         .get_mclk_od =3D smu7_= get_mclk_od,
>         .set_mclk_od =3D smu7_= set_mclk_od,
>         .get_clock_by_type =3D= smu7_get_clock_by_type,
> +       .read_sensor =3D smu7_read_s= ensor,
>  };
>
>  uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drive= rs/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> index f941acf563a9..dfa0f38a5e76 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h > @@ -29,6 +29,17 @@
>  #include "amd_shared.h"
>  #include "cgs_common.h"
>
> +enum amd_pp_sensors {
> +       AMDGPU_PP_SENSOR_GFX_SCLK = =3D 0,
> +       AMDGPU_PP_SENSOR_VDDNB,
> +       AMDGPU_PP_SENSOR_VDDGFX,
> +       AMDGPU_PP_SENSOR_UVD_VCLK, > +       AMDGPU_PP_SENSOR_UVD_DCLK, > +       AMDGPU_PP_SENSOR_VCE_ECCLK,<= br> > +       AMDGPU_PP_SENSOR_GPU_LOAD, > +       AMDGPU_PP_SENSOR_GFX_MCLK, > +       AMDGPU_PP_SENSOR_GPU_TEMP, > +};
>
>  enum amd_pp_event {
>         AMD_PP_EVENT_INITIALIZ= E =3D 0,
> @@ -347,6 +358,7 @@ struct amd_powerplay_funcs {
>         int (*set_sclk_od)(voi= d *handle, uint32_t value);
>         int (*get_mclk_od)(voi= d *handle);
>         int (*set_mclk_od)(voi= d *handle, uint32_t value);
> +       int (*read_sensor)(void *han= dle, int idx, int32_t *value);
>  };
>
>  struct amd_powerplay {
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/d= rm/amd/powerplay/inc/hwmgr.h
> index c9628b4db2c3..fcd45452380d 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -359,6 +359,7 @@ struct pp_hwmgr_func {
>         int (*set_sclk_od)(str= uct pp_hwmgr *hwmgr, uint32_t value);
>         int (*get_mclk_od)(str= uct pp_hwmgr *hwmgr);
>         int (*set_mclk_od)(str= uct pp_hwmgr *hwmgr, uint32_t value);
> +       int (*read_sensor)(struct pp= _hwmgr *hwmgr, int idx, int32_t *value);
>  };
>
>  struct pp_table_func {
> --
> 2.10.0
>
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