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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: QTSg2S2EKRNA8apdDfqzK/2RbzyIvm2HFPs7iQJCPFhXylCgzqrSzpzW1RVZ/+8/kmkORUKUZqe61XiVrLm4iHi3CcIp/+4Cpsj1GBN/RpykJ8WWBnhDYTV9BjlNbuayoUD5wT2oj/3OFPlhae+/ELgmwos7BIsq5YRE8e9HiW22sfT4AIv/87eZpf0iLyUJAf/oQTTQq8Z5ouuR4dgSLPy5tXslE/3u9VCSVuDSgZa2o2ztcrhwzI4YymY8Cb+8ET70vICgMQhnn4GiZxo1ndSavck7i6igN6SWNmqcobceiH2/75qQvBCDw7PXgupdDwbwFRUgr+i2AZFyaTo5oSjkn+7sNJ2Vpei19HcUKPG62JY75WEv9nqFKyew87h6maSDsnzXxO179ObTttoN8x+oM1jSftEkwh2A7sLCTKw= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: c470ad1e-e923-4fca-66aa-08d6bdc00103 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Apr 2019 14:22:46.6533 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1801MB2054 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-10_06:, , signatures=0 Subject: Re: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >-----Original Message----- >From: Yongseok Koh >Sent: Wednesday, April 10, 2019 7:45 AM >To: jerinjacobk@gmail.com; Pavan Nikhilesh Bhagavatula > >Cc: Thomas Monjalon ; dev ; Jerin >Jacob Kollanukkaran >Subject: [EXT] Re: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support >machine specific flags > >External Email > >---------------------------------------------------------------------- > >> On Apr 9, 2019, at 5:40 PM, Yongseok Koh wrote: >> >>> >>> On Apr 6, 2019, at 7:27 AM, jerinjacobk@gmail.com wrote: >>> >>> From: Pavan Nikhilesh >>> >>> Currently, RTE_* flags are set based on the implementer ID but there >>> might be some micro arch specific differences from the same vendor >>> eg. CACHE_LINESIZE. Add support to set micro arch specific flags. >>> >>> Signed-off-by: Pavan Nikhilesh >>> Signed-off-by: Jerin Jacob >>> --- >>> config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++----- >>> 1 file changed, 32 insertions(+), 5 deletions(-) >>> >>> diff --git a/config/arm/meson.build b/config/arm/meson.build index >>> 170a4981a..8de3f3e3a 100644 >>> --- a/config/arm/meson.build >>> +++ b/config/arm/meson.build >>> @@ -52,12 +52,10 @@ flags_generic =3D [ >>> ['RTE_USE_C11_MEM_MODEL', true], >>> ['RTE_CACHE_LINE_SIZE', 128]] >>> flags_cavium =3D [ >>> - ['RTE_MACHINE', '"thunderx"'], >>> ['RTE_CACHE_LINE_SIZE', 128], >>> ['RTE_MAX_NUMA_NODES', 2], >>> ['RTE_MAX_LCORE', 96], >>> - ['RTE_MAX_VFIO_GROUPS', 128], >>> - ['RTE_USE_C11_MEM_MODEL', false]] >>> + ['RTE_MAX_VFIO_GROUPS', 128]] >>> flags_dpaa =3D [ >>> ['RTE_MACHINE', '"dpaa"'], >>> ['RTE_USE_C11_MEM_MODEL', true], >>> @@ -71,6 +69,27 @@ flags_dpaa2 =3D [ >>> ['RTE_MAX_NUMA_NODES', 1], >>> ['RTE_MAX_LCORE', 16], >>> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] >>> +flags_default_extra =3D [] >>> +flags_thunderx_extra =3D [ >>> + ['RTE_MACHINE', '"thunderx"'], >>> + ['RTE_USE_C11_MEM_MODEL', false]] >>> + >>> +machine_args_generic =3D [ >>> + ['default', ['-march=3Darmv8-a+crc+crypto']], >>> + ['native', ['-march=3Dnative']], >>> + ['0xd03', ['-mcpu=3Dcortex-a53']], >>> + ['0xd04', ['-mcpu=3Dcortex-a35']], >>> + ['0xd07', ['-mcpu=3Dcortex-a57']], >>> + ['0xd08', ['-mcpu=3Dcortex-a72']], >>> + ['0xd09', ['-mcpu=3Dcortex-a73']], >>> + ['0xd0a', ['-mcpu=3Dcortex-a75']]] >>> + >>> +machine_args_cavium =3D [ >>> + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >>> + ['native', ['-march=3Dnative']], >>> + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], >>> + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], >>> + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >> >> Looks like there's a mistake in rebasing it? Seems so will send out v8. >> You should've removed machine_args_generic and machine_args_cavium in >> the beginning of this file. >> >> Other than that, it looks good to me. >> >> BTW, thanks for the patch. I raised this issue before and I was >> supposed to make the change but you have taken it. >> >> Yongseok >> >>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page >>> G7-5321) impl_generic =3D ['Generic armv8', flags_generic, >>> machine_args_generic] @@ -157,8 +176,16 @@ else >>> endif >>> foreach marg: machine[2] >>> if marg[0] =3D=3D impl_pn >>> - foreach f: marg[1] >>> - machine_args +=3D f >>> + foreach flag: marg[1] >>> + if cc.has_argument(flag) >>> + machine_args +=3D flag >>> + endif >>> + endforeach >>> + # Apply any extra machine specific flags. >>> + foreach flag: marg.get(2, flags_default_extra) >>> + if flag.length() > 0 >>> + dpdk_conf.set(flag[0], flag[1]) >>> + endif > >And setting the extra flags doesn't work well with gcc < 7 because of the >following, Extra flags aren't set in this case as the third variable in the list is m= issing when 'native' or 'default' is selected generic=3D=20 ['default', ['-march=3Darmv8-a+crc+crypto']], ['native', ['-march=3Dnative']] cavium=3D ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], ['native', ['-march=3Dnative']] And marg.get falls back to flags_default_extra =3D []. > > # Primary part number based mcpu flags are supported > # for gcc versions > 7 > if cc.version().version_compare( > '<7.0') or cmd_output.length() =3D=3D 0 > if not meson.is_cross_build() and arm_force_native_march = =3D=3D true > impl_pn =3D 'native' > else > impl_pn =3D 'default' > endif > endif > >Thanks, >Yongseok > >>> endforeach >>> endif >>> endforeach >>> -- >>> 2.21.0