From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Wang, Yipeng1" <yipeng1.wang@intel.com>
Subject: Re: [PATCH v3 4/7] hash: add memory ordering to avoid
 race conditions
Date: Sat, 13 Oct 2018 01:56:15 +0000
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References: <1539325918-125438-1-git-send-email-honnappa.nagarahalli@arm.com>
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When I applied this commit:
fatal: sha1 information is lacking or useless (lib/librte_hash/rte_cuckoo_h=
ash.c).
Please double check.

>-----Original Message-----
>From: Honnappa Nagarahalli [mailto:honnappa.nagarahalli@arm.com]
>Sent: Thursday, October 11, 2018 11:32 PM
>To: Richardson, Bruce <bruce.richardson@intel.com>; De Lara Guarch, Pablo =
<pablo.de.lara.guarch@intel.com>
>Cc: dev@dpdk.org; Wang, Yipeng1 <yipeng1.wang@intel.com>; honnappa.nagarah=
alli@arm.com; dharmik.thakkar@arm.com;
>gavin.hu@arm.com; nd@arm.com
>Subject: [PATCH v3 4/7] hash: add memory ordering to avoid race conditions
>
>Only race condition that can occur is -  using the key store element
>before the key write is completed. Hence, while inserting the element
>the release memory order is used. Any other race condition is caught
>by the key comparison. Memory orderings are added only where needed.
>For ex: reads in the writer's context do not need memory ordering
>as there is a single writer.
[Wang, Yipeng]=20
I remember we discussed that this commit itself does not fix any bug/issue,=
 or enabling feature, it is supposed to work with the following patches
to enable lock-free read-write concurrency. You separated the commits for e=
asier review.

If you plan to merge these commits and change the commit message it would b=
e fine. Otherwise the current message title and content
Is misleading. It sounds like a bug fix but actually not.