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x-originating-ip: [2607:fb90:9e4d:a2f5:7c7d:af93:6799:77fe] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d3d3fb38-b60b-42d0-67da-08d6e3a43ed2 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:BYAPR04MB6101; x-ms-traffictypediagnostic: BYAPR04MB6101: wdcipoutbound: EOP-TRUE x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:5797; x-forefront-prvs: 00514A2FE6 x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(136003)(396003)(346002)(366004)(39860400002)(376002)(189003)(199004)(53754006)(68736007)(36756003)(7736002)(305945005)(76116006)(91956017)(82746002)(256004)(4326008)(6246003)(46003)(54906003)(2501003)(66946007)(66476007)(66556008)(33656002)(6486002)(25786009)(53936002)(73956011)(110136005)(64756008)(66446008)(186003)(476003)(229853002)(446003)(2616005)(486006)(11346002)(81166006)(316002)(53546011)(102836004)(72206003)(83716004)(478600001)(81156014)(86362001)(76176011)(71190400001)(14454004)(5660300002)(8676002)(6116002)(2906002)(71200400001)(6436002)(6512007)(99286004)(6506007)(8936002);DIR:OUT;SFP:1102;SCL:1;SRVR:BYAPR04MB6101;H:BYAPR04MB3782.namprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: /LUGS4mxWdKS+kChM5P8Xl/etz/qCq3fWYReMI2IJsx1K/tEqLec/bUnB754tzRQySAHt/WzaKB8mzZ/rE1hgnPPbi9izd5yhIkAUHfCcZwP4oB5RUoeptlc437Orfx1pqXgpzrcyFmIAs85WUWcXHhvgCBVdudZoUlCiNN+L/K8/9kKX9pN1EKJ1VQ5bc3cYjFjs7HpIWeLgSXdQUxv696WByKZ5ELRNLiAMzXPo+tnFWUJ4KHXFEizSVERZECm7sBA7OEx09TAXVQNYqK8q8mcaK5vpCqEF6Jn5SRLs0xM6JW/eJoks4v8q16zHlLKfp73jAQpmdgAbS+oOrRj0L0Y5BdMB/rHpoWf88kYRLkI2+5tK7BaM1sO1yKxSuYtbZDJcMTUd4t3a3gxfhqD5xSOocUFa3nR4lY2RkXrm9U= Content-Type: text/plain; charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: d3d3fb38-b60b-42d0-67da-08d6e3a43ed2 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 May 2019 19:39:48.6112 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Atish.Patra@wdc.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR04MB6101 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On 5/28/19 10:47 AM, Palmer Dabbelt wrote: >> On Mon, 20 May 2019 01:05:22 PDT (-0700), anup@brainfault.org wrote: >>> On Wed, May 15, 2019 at 12:00 PM Anup Patel wrote: >>>=20 >>> This patch enables NO_HZ_IDLE (idle dynamic ticks) and HIGH_RES_TIMERS >>> (hrtimers) in RV32 and RV64 defconfigs. >>>=20 >>> Both of the above options are enabled by default for architectures >>> such as x86, ARM, and ARM64. >>>=20 >>> The idle dynamic ticks helps use save power by stopping timer ticks >>> when the system is idle whereas hrtimers is a much improved timer >>> subsystem compared to the old "timer wheel" based system. >>>=20 >>> This patch is tested on SiFive Unleashed board and QEMU Virt machine. >>>=20 >>> Signed-off-by: Anup Patel >>> --- >>> arch/riscv/configs/defconfig | 2 ++ >>> arch/riscv/configs/rv32_defconfig | 2 ++ >>> 2 files changed, 4 insertions(+) >>>=20 >>> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfi= g >>> index 2fd3461e50ab..f254c352ec57 100644 >>> --- a/arch/riscv/configs/defconfig >>> +++ b/arch/riscv/configs/defconfig >>> @@ -1,5 +1,7 @@ >>> CONFIG_SYSVIPC=3Dy >>> CONFIG_POSIX_MQUEUE=3Dy >>> +CONFIG_NO_HZ_IDLE=3Dy >>> +CONFIG_HIGH_RES_TIMERS=3Dy >>> CONFIG_IKCONFIG=3Dy >>> CONFIG_IKCONFIG_PROC=3Dy >>> CONFIG_CGROUPS=3Dy >>> diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv3= 2_defconfig >>> index 1a911ed8e772..d5449ef805a3 100644 >>> --- a/arch/riscv/configs/rv32_defconfig >>> +++ b/arch/riscv/configs/rv32_defconfig >>> @@ -1,5 +1,7 @@ >>> CONFIG_SYSVIPC=3Dy >>> CONFIG_POSIX_MQUEUE=3Dy >>> +CONFIG_NO_HZ_IDLE=3Dy >>> +CONFIG_HIGH_RES_TIMERS=3Dy >>> CONFIG_IKCONFIG=3Dy >>> CONFIG_IKCONFIG_PROC=3Dy >>> CONFIG_CGROUPS=3Dy >>> -- >>> 2.17.1 >>=20 >> Hi All, >>=20 >> Any comments on this one? >>=20 >> @Palmer, It would be nice to have this in Linux-5.2 > My only issue here is testing: IIRC last time we tried this it ended up c= ausing > trouble. =20 Are you talking about the trouble with CONFIG_NO_HZ_IDLE we were seeing las= t year or something else ? CONFIG_NO_HZ_IDLE was well tested and fixed last year. I'm in the process of switching to Yocto right now for my tests, so > it'll be a bit slow. --=20 Regards, Atish From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,T_DKIMWL_WL_HIGH,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADA7FC04AB6 for ; Tue, 28 May 2019 19:40:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 83EA120B1F for ; Tue, 28 May 2019 19:40:00 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Tue, 28 May 2019 19:39:48 +0000 Received: from BYAPR04MB3782.namprd04.prod.outlook.com ([fe80::ce8:bf96:aaf8:d2b0]) by BYAPR04MB3782.namprd04.prod.outlook.com ([fe80::ce8:bf96:aaf8:d2b0%4]) with mapi id 15.20.1922.021; Tue, 28 May 2019 19:39:48 +0000 From: Atish Patra To: Palmer Dabbelt , "anup@brainfault.org" , Paul Walmsley Subject: Re: [PATCH] RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERS Thread-Topic: [PATCH] RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERS Thread-Index: AQHVCue2HEus4pRvEEGYJRX3qv0JO6Zzr7wAgA01ZYCAAB9GgA== Date: Tue, 28 May 2019 19:39:48 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Atish.Patra@wdc.com; x-originating-ip: [2607:fb90:9e4d:a2f5:7c7d:af93:6799:77fe] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d3d3fb38-b60b-42d0-67da-08d6e3a43ed2 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org > On 5/28/19 10:47 AM, Palmer Dabbelt wrote: >> On Mon, 20 May 2019 01:05:22 PDT (-0700), anup@brainfault.org wrote: >>> On Wed, May 15, 2019 at 12:00 PM Anup Patel wrote: >>> >>> This patch enables NO_HZ_IDLE (idle dynamic ticks) and HIGH_RES_TIMERS >>> (hrtimers) in RV32 and RV64 defconfigs. >>> >>> Both of the above options are enabled by default for architectures >>> such as x86, ARM, and ARM64. >>> >>> The idle dynamic ticks helps use save power by stopping timer ticks >>> when the system is idle whereas hrtimers is a much improved timer >>> subsystem compared to the old "timer wheel" based system. >>> >>> This patch is tested on SiFive Unleashed board and QEMU Virt machine. >>> >>> Signed-off-by: Anup Patel >>> --- >>> arch/riscv/configs/defconfig | 2 ++ >>> arch/riscv/configs/rv32_defconfig | 2 ++ >>> 2 files changed, 4 insertions(+) >>> >>> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig >>> index 2fd3461e50ab..f254c352ec57 100644 >>> --- a/arch/riscv/configs/defconfig >>> +++ b/arch/riscv/configs/defconfig >>> @@ -1,5 +1,7 @@ >>> CONFIG_SYSVIPC=y >>> CONFIG_POSIX_MQUEUE=y >>> +CONFIG_NO_HZ_IDLE=y >>> +CONFIG_HIGH_RES_TIMERS=y >>> CONFIG_IKCONFIG=y >>> CONFIG_IKCONFIG_PROC=y >>> CONFIG_CGROUPS=y >>> diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig >>> index 1a911ed8e772..d5449ef805a3 100644 >>> --- a/arch/riscv/configs/rv32_defconfig >>> +++ b/arch/riscv/configs/rv32_defconfig >>> @@ -1,5 +1,7 @@ >>> CONFIG_SYSVIPC=y >>> CONFIG_POSIX_MQUEUE=y >>> +CONFIG_NO_HZ_IDLE=y >>> +CONFIG_HIGH_RES_TIMERS=y >>> CONFIG_IKCONFIG=y >>> CONFIG_IKCONFIG_PROC=y >>> CONFIG_CGROUPS=y >>> -- >>> 2.17.1 >> >> Hi All, >> >> Any comments on this one? >> >> @Palmer, It would be nice to have this in Linux-5.2 > My only issue here is testing: IIRC last time we tried this it ended up causing > trouble. Are you talking about the trouble with CONFIG_NO_HZ_IDLE we were seeing last year or something else ? CONFIG_NO_HZ_IDLE was well tested and fixed last year. I'm in the process of switching to Yocto right now for my tests, so > it'll be a bit slow. -- Regards, Atish _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv