From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751926AbcF3D12 (ORCPT ); Wed, 29 Jun 2016 23:27:28 -0400 Received: from mail-db3on0060.outbound.protection.outlook.com ([157.55.234.60]:5710 "EHLO emea01-db3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751547AbcF3D1H convert rfc822-to-8bit (ORCPT ); Wed, 29 Jun 2016 23:27:07 -0400 X-Greylist: delayed 4663 seconds by postgrey-1.27 at vger.kernel.org; Wed, 29 Jun 2016 23:27:07 EDT From: Yunhui Cui To: Yunhui Cui , "dwmw2@infradead.org" , "computersforpeace@gmail.com" , "han.xu@freescale.com" CC: "linux-kernel@vger.kernel.org" , "linux-mtd@lists.infradead.org" , "linux-arm-kernel@lists.infradead.org" , Yao Yuan Subject: RE: [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Thread-Topic: [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Thread-Index: AQHRnGMVkiq9HlxCa0OGY063kZAKpaABqsMw Date: Thu, 30 Jun 2016 01:54:14 +0000 Message-ID: References: <1461307192-866-1-git-send-email-B56489@freescale.com> In-Reply-To: <1461307192-866-1-git-send-email-B56489@freescale.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yunhui.cui@nxp.com; x-originating-ip: [199.59.230.102] x-ms-office365-filtering-correlation-id: 8011e330-5742-401c-a5bd-08d3a0897080 x-microsoft-exchange-diagnostics: 1;DB6PR0401MB2408;6:3/rJnnAPXDcz65kQpYTXe+SXH5fpoyq9Ml1AJzdgc9He8jYDQL/z9WsumpZnK+zOm5L8j1lD6m3G9gAevGueJz5/n0QFJ+kCGN16jrxyGtiLy4TuUAqP29tFekfYxqrUQdgGg3Hg0lwwYdDbyP/EYyCdR3MoJo0guhMaNOFj7yrMhxytpzhVE3y4EfDB0kmaEVTl1z5Z4AfNhlo17zVCxkdBJrfIX4Lg4fAGrsgo3odGxeeJAAGbRW9RxegGzjvsgtwUTZ55DXJSgBFXUTWHL//kjYmHBkX7moN32/LwuU1GlWbA7r1byGoNbpH3OW94LUG75DTnlm2V2yqpOvR4f5SMppgD3wigy6LSlPqPdI8=;5:41199qoKd8Nuig2UatlwNz67imqoKg084kP0mo5MFmtdbM60W7Nm/zXjgPGBPPWqhSsl8eC19AAPGBZWA+jD+wEJNcS0mnJGsX2d8sbX3vEb5/UVhui4MRqUAFGmXPlHMgijlZoq4yLMJ0dQBHYlTQ==;24:RVYf9n4OmWlFP5tpORNNS73k8jjrGgPHUXJNOVNnhgKZxXc1FfHnsTDpsHjlJC4C06o9Yye0XXUyzjit1wMctLBy1FRAFthavU2YBBK1lEc=;7:+ihGfKMnI+cp07lS7qB3TWLj4KxtftbocybplWUP5XhUInc6byiKppyFBhL7lW7zUCalQFag9uBWhpdUxuqjIPuyrzBYXj1L9TJJZ5cEC9AJRkYZFj03PGRfuXnG2OxUoMbKNqdDBULok8v1q6/Z/MSpvCvogS3CG0ybOQuI0l09BomH8u+jqfTnvKkQxBefpjrVniaHxo/bIzTb6hp5lqF86/hMKQMQGM/Eb7R846XqDxUVrk3lWiokYXfKWgHupotdreasoDwM+wZQRTQ8Bg== x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DB6PR0401MB2408; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(9452136761055)(185117386973197)(101931422205132)(258649278758335); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001)(6055026);SRVR:DB6PR0401MB2408;BCL:0;PCL:0;RULEID:;SRVR:DB6PR0401MB2408; x-forefront-prvs: 0989A7979C x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(7916002)(189002)(199003)(377454003)(13464003)(2501003)(86362001)(74316001)(19580395003)(2201001)(5002640100001)(81166006)(87936001)(8676002)(11100500001)(3660700001)(2906002)(9686002)(4326007)(81156014)(3280700002)(66066001)(19580405001)(92566002)(68736007)(8666005)(105586002)(586003)(101416001)(50986999)(2950100001)(5003600100003)(7846002)(106356001)(77096005)(8936002)(2900100001)(97736004)(33656002)(10400500002)(76576001)(102836003)(3846002)(76176999)(54356999)(6116002)(5001770100001)(7696003)(106116001)(305945005)(7736002)(189998001)(122556002)(7059030);DIR:OUT;SFP:1101;SCL:1;SRVR:DB6PR0401MB2408;H:DB5PR0401MB1912.eurprd04.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;MX:1;A:1;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Jun 2016 01:54:14.6583 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0401MB2408 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Brian and Han, Could you please give me some comments about this patch set v2 ? Thanks > -----Original Message----- > From: Yunhui Cui [mailto:B56489@freescale.com] > Sent: Friday, April 22, 2016 2:40 PM > To: dwmw2@infradead.org; computersforpeace@gmail.com; > han.xu@freescale.com > Cc: linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org; linux- > arm-kernel@lists.infradead.org; Yao Yuan; Yunhui Cui > Subject: [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI- > NOR > > We can get the read/write/erase opcode from the spi nor framework > directly. This patch uses the information stored in the SPI-NOR to remove > the hardcode in the fsl_qspi_init_lut(). > > Signed-off-by: Yunhui Cui > Signed-off-by: Yunhui Cui > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 40 ++++++++++++--------------------- > ------ > 1 file changed, 12 insertions(+), 28 deletions(-) > > diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl- > quadspi.c > index 9ab2b51..517ffe2 100644 > --- a/drivers/mtd/spi-nor/fsl-quadspi.c > +++ b/drivers/mtd/spi-nor/fsl-quadspi.c > @@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > void __iomem *base = q->iobase; > int rxfifo = q->devtype_data->rxfifo; > u32 lut_base; > - u8 cmd, addrlen, dummy; > int i; > > + struct spi_nor *nor = &q->nor[0]; > + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT; > + u8 read_op = nor->read_opcode; > + u8 read_dm = nor->read_dummy; > + > fsl_qspi_unlock_lut(q); > > /* Clear all the LUT table */ > @@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Quad Read */ > lut_base = SEQID_QUAD_READ * 4; > > - if (q->nor_size <= SZ_16M) { > - cmd = SPINOR_OP_READ_1_1_4; > - addrlen = ADDR24BIT; > - dummy = 8; > - } else { > - /* use the 4-byte address */ > - cmd = SPINOR_OP_READ_1_1_4; > - addrlen = ADDR32BIT; > - dummy = 8; > - } > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > - qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, > rxfifo), > + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | > + LUT1(FSL_READ, PAD4, rxfifo), > base + QUADSPI_LUT(lut_base + 1)); > > /* Write enable */ > @@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Page Program */ > lut_base = SEQID_PP * 4; > > - if (q->nor_size <= SZ_16M) { > - cmd = SPINOR_OP_PP; > - addrlen = ADDR24BIT; > - } else { > - /* use the 4-byte address */ > - cmd = SPINOR_OP_PP; > - addrlen = ADDR32BIT; > - } > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) | > + LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0), > base + QUADSPI_LUT(lut_base + 1)); > @@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Erase a sector */ > lut_base = SEQID_SE * 4; > > - cmd = q->nor[0].erase_opcode; > - addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT; > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) | > + LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > > /* Erase the whole chip */ > -- > 2.1.0.27.g96db324 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yunhui Cui To: Yunhui Cui , "dwmw2@infradead.org" , "computersforpeace@gmail.com" , "han.xu@freescale.com" CC: "linux-kernel@vger.kernel.org" , "linux-mtd@lists.infradead.org" , "linux-arm-kernel@lists.infradead.org" , Yao Yuan Subject: RE: [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Date: Thu, 30 Jun 2016 01:54:14 +0000 Message-ID: References: <1461307192-866-1-git-send-email-B56489@freescale.com> In-Reply-To: <1461307192-866-1-git-send-email-B56489@freescale.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Hi Brian and Han, Could you please give me some comments about this patch set v2 ? Thanks > -----Original Message----- > From: Yunhui Cui [mailto:B56489@freescale.com] > Sent: Friday, April 22, 2016 2:40 PM > To: dwmw2@infradead.org; computersforpeace@gmail.com; > han.xu@freescale.com > Cc: linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org; linux- > arm-kernel@lists.infradead.org; Yao Yuan; Yunhui Cui > Subject: [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI- > NOR >=20 > We can get the read/write/erase opcode from the spi nor framework > directly. This patch uses the information stored in the SPI-NOR to remove > the hardcode in the fsl_qspi_init_lut(). >=20 > Signed-off-by: Yunhui Cui > Signed-off-by: Yunhui Cui > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 40 ++++++++++++--------------------- > ------ > 1 file changed, 12 insertions(+), 28 deletions(-) >=20 > diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl- > quadspi.c > index 9ab2b51..517ffe2 100644 > --- a/drivers/mtd/spi-nor/fsl-quadspi.c > +++ b/drivers/mtd/spi-nor/fsl-quadspi.c > @@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > void __iomem *base =3D q->iobase; > int rxfifo =3D q->devtype_data->rxfifo; > u32 lut_base; > - u8 cmd, addrlen, dummy; > int i; >=20 > + struct spi_nor *nor =3D &q->nor[0]; > + u8 addrlen =3D (nor->addr_width =3D=3D 3) ? ADDR24BIT : ADDR32BIT; > + u8 read_op =3D nor->read_opcode; > + u8 read_dm =3D nor->read_dummy; > + > fsl_qspi_unlock_lut(q); >=20 > /* Clear all the LUT table */ > @@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Quad Read */ > lut_base =3D SEQID_QUAD_READ * 4; >=20 > - if (q->nor_size <=3D SZ_16M) { > - cmd =3D SPINOR_OP_READ_1_1_4; > - addrlen =3D ADDR24BIT; > - dummy =3D 8; > - } else { > - /* use the 4-byte address */ > - cmd =3D SPINOR_OP_READ_1_1_4; > - addrlen =3D ADDR32BIT; > - dummy =3D 8; > - } > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > - qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, > rxfifo), > + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | > + LUT1(FSL_READ, PAD4, rxfifo), > base + QUADSPI_LUT(lut_base + 1)); >=20 > /* Write enable */ > @@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Page Program */ > lut_base =3D SEQID_PP * 4; >=20 > - if (q->nor_size <=3D SZ_16M) { > - cmd =3D SPINOR_OP_PP; > - addrlen =3D ADDR24BIT; > - } else { > - /* use the 4-byte address */ > - cmd =3D SPINOR_OP_PP; > - addrlen =3D ADDR32BIT; > - } > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) | > + LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0), > base + QUADSPI_LUT(lut_base + 1)); > @@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Erase a sector */ > lut_base =3D SEQID_SE * 4; >=20 > - cmd =3D q->nor[0].erase_opcode; > - addrlen =3D q->nor_size <=3D SZ_16M ? ADDR24BIT : ADDR32BIT; > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) | > + LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); >=20 > /* Erase the whole chip */ > -- > 2.1.0.27.g96db324 From mboxrd@z Thu Jan 1 00:00:00 1970 From: yunhui.cui@nxp.com (Yunhui Cui) Date: Thu, 30 Jun 2016 01:54:14 +0000 Subject: [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR In-Reply-To: <1461307192-866-1-git-send-email-B56489@freescale.com> References: <1461307192-866-1-git-send-email-B56489@freescale.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Brian and Han, Could you please give me some comments about this patch set v2 ? Thanks > -----Original Message----- > From: Yunhui Cui [mailto:B56489 at freescale.com] > Sent: Friday, April 22, 2016 2:40 PM > To: dwmw2 at infradead.org; computersforpeace at gmail.com; > han.xu at freescale.com > Cc: linux-kernel at vger.kernel.org; linux-mtd at lists.infradead.org; linux- > arm-kernel at lists.infradead.org; Yao Yuan; Yunhui Cui > Subject: [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI- > NOR > > We can get the read/write/erase opcode from the spi nor framework > directly. This patch uses the information stored in the SPI-NOR to remove > the hardcode in the fsl_qspi_init_lut(). > > Signed-off-by: Yunhui Cui > Signed-off-by: Yunhui Cui > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 40 ++++++++++++--------------------- > ------ > 1 file changed, 12 insertions(+), 28 deletions(-) > > diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl- > quadspi.c > index 9ab2b51..517ffe2 100644 > --- a/drivers/mtd/spi-nor/fsl-quadspi.c > +++ b/drivers/mtd/spi-nor/fsl-quadspi.c > @@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > void __iomem *base = q->iobase; > int rxfifo = q->devtype_data->rxfifo; > u32 lut_base; > - u8 cmd, addrlen, dummy; > int i; > > + struct spi_nor *nor = &q->nor[0]; > + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT; > + u8 read_op = nor->read_opcode; > + u8 read_dm = nor->read_dummy; > + > fsl_qspi_unlock_lut(q); > > /* Clear all the LUT table */ > @@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Quad Read */ > lut_base = SEQID_QUAD_READ * 4; > > - if (q->nor_size <= SZ_16M) { > - cmd = SPINOR_OP_READ_1_1_4; > - addrlen = ADDR24BIT; > - dummy = 8; > - } else { > - /* use the 4-byte address */ > - cmd = SPINOR_OP_READ_1_1_4; > - addrlen = ADDR32BIT; > - dummy = 8; > - } > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > - qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, > rxfifo), > + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | > + LUT1(FSL_READ, PAD4, rxfifo), > base + QUADSPI_LUT(lut_base + 1)); > > /* Write enable */ > @@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Page Program */ > lut_base = SEQID_PP * 4; > > - if (q->nor_size <= SZ_16M) { > - cmd = SPINOR_OP_PP; > - addrlen = ADDR24BIT; > - } else { > - /* use the 4-byte address */ > - cmd = SPINOR_OP_PP; > - addrlen = ADDR32BIT; > - } > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) | > + LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0), > base + QUADSPI_LUT(lut_base + 1)); > @@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Erase a sector */ > lut_base = SEQID_SE * 4; > > - cmd = q->nor[0].erase_opcode; > - addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT; > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) | > + LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > > /* Erase the whole chip */ > -- > 2.1.0.27.g96db324