From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753547AbcIIJ3M (ORCPT ); Fri, 9 Sep 2016 05:29:12 -0400 Received: from mail-db5eur01on0058.outbound.protection.outlook.com ([104.47.2.58]:37376 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753478AbcIIJ3I (ORCPT ); Fri, 9 Sep 2016 05:29:08 -0400 From: "S.H. Xie" To: Mark Rutland CC: "devicetree@vger.kernel.org" , "robh+dt@kernel.org" , "linux-arm-kernel@lists.infradead.org" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "shawnguo@kernel.org" , "linux-kernel@vger.kernel.org" , "arnd@arndb.de" , Vincent Hu , Horia Geanta Neag , "Mihai Emilian Bantea" , "C.H. Zhao" , "Q.Y. Gong" , "M.H. Lian" , "Z.Q. Hou" Subject: RE: [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support Thread-Topic: [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support Thread-Index: AQHSB15qtQrbpcpS5kasgZ0Wj8lByqBvltQAgAABXACAASVl0A== Date: Fri, 9 Sep 2016 06:55:30 +0000 Message-ID: References: <1473069695-33092-1-git-send-email-shh.xie@gmail.com> <1473069695-33092-4-git-send-email-shh.xie@gmail.com> <20160908131326.GE26570@leverpostej> <20160908131818.GF26570@leverpostej> In-Reply-To: <20160908131818.GF26570@leverpostej> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=shaohui.xie@nxp.com; x-originating-ip: [199.59.226.141] x-ms-office365-filtering-correlation-id: 51daa417-b0dc-4bb1-36df-08d3d87e49a3 x-microsoft-exchange-diagnostics: 1;AMSPR04MB0839;6:oadAwe+rmcu+fz1jBG8QIRQcPDSyjY7+7z+PGiXrvE0JzX3nBee4WpApdGZOsoRM9e3xk7bTSHfkRcgHFXk0XNG04ARYjgD6gP911AehcNppnUnEsKclS/c2hja6kc45tQw903w8q8JRUv74r6TEN5l00P2/iBdGBrGSZc2aCil1rhd2t9NvSoBGUpIfHjBo1G3xgcViBAq4/V7dVNOIysvKgRqE7MM5VDdYFznCHvot/uYHbIl4kiqRlquNp9iBfhS1RnAKOYGxI4lD8S2OzmQ17gZRzvfMy5ruTGSJqs5xkLDdG4Q+Q+U8nUATOVR7Fvg3G/XgmjVcMBu9Oa/yNQ==;5:gPc4JNi5oOiyuXr5I7DVA+Vg2a3B3CLAiXibfW4NLXRGKTl8qiNmli88qL6QJ2AoCGzxq0omdnm6v144e/4RbpFhdMfIRqPp3q8ukM64oqfo2+eSt6h5kknhnGrDhKiYg2iRd/m4JOQqMNBZIpZguA==;24:c6IypJm0WLlbgU9eo/4i56FnenyI75VgQVmGLxd0d1STLE4wMPBDm65bRUWWH7yALR91L6AaAlOqth/Zbh5kf5t2QduTBMpooZGuLluOdQA=;7:tv+16xDy3/+/pqe4abU1qR7kVbgZFQumEgOnB9KbkuNtJy7tmJhJoHcz3ekzGzD4d8VyAJK4J50laNkggUs8Rry+PqdGf6RLjS4An7rQH6ZnYQZfzvMBGNpCMCMYA8dR6lBYTg8BOXZ/eH7FOts+uGi5HQ62mMsI4L2WToP0IOowkmLH76Meal5+JeCGP28zr9gLIh3bKPYy8wofmpOycuspJDEPE6FXRlzuduwll5CN9uqRCMXGdeoUHC4IRi39 x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:AMSPR04MB0839; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040176)(601004)(2401047)(8121501046)(5005006)(10201501046)(3002001)(6055026);SRVR:AMSPR04MB0839;BCL:0;PCL:0;RULEID:;SRVR:AMSPR04MB0839; x-forefront-prvs: 00603B7EEF x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(7916002)(199003)(24454002)(189002)(2900100001)(86362001)(74316002)(3846002)(7736002)(7846002)(305945005)(6116002)(586003)(102836003)(76176999)(54356999)(3280700002)(7696004)(189998001)(122556002)(10400500002)(8936002)(5660300001)(92566002)(50986999)(8676002)(81166006)(68736007)(76576001)(81156014)(110136002)(66066001)(33656002)(5002640100001)(4326007)(2906002)(2950100001)(101416001)(93886004)(97736004)(106356001)(9686002)(87936001)(77096005)(106116001)(19580405001)(3660700001)(19580395003)(105586002)(11100500001);DIR:OUT;SFP:1101;SCL:1;SRVR:AMSPR04MB0839;H:DB5PR0401MB2183.eurprd04.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;A:1;MX:1;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Sep 2016 06:55:30.0882 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AMSPR04MB0839 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id u899TSgt030920 > On Thu, Sep 08, 2016 at 02:13:26PM +0100, Mark Rutland wrote: > > On Mon, Sep 05, 2016 at 06:01:31PM +0800, shh.xie@gmail.com wrote: > > > + cpus { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + cpu0: cpu@0 { > > > + device_type = "cpu"; > > > + compatible = "arm,cortex-a72"; > > > + reg = <0x0>; > > > + clocks = <&clockgen 1 0>; > > > + next-level-cache = <&l2>; > > > + cpu-idle-states = <&CPU_PH20>; > > > + }; > > > > [...] > > > > > + }; > > > + > > > + idle-states { > > > + entry-method = "arm,psci"; > > > + > > > + CPU_PH20: cpu-ph20 { > > > + compatible = "arm,idle-state"; > > > + idle-state-name = "PH20"; > > > + arm,psci-suspend-param = <0x00010000>; > > > + entry-latency-us = <1000>; > > > + exit-latency-us = <1000>; > > > + min-residency-us = <3000>; > > > + }; > > > + }; > > > > There's no PSCI node in this file, and none from am included file, so > > this doesn't look right. > > Looking again, none of the cpu nodes has an enable-method property, and > subsequent patches don't seem to add that to any cpu node. > > Has this DT actually been tested? [S.H] The PSCI node and the enable-method property are added by U-boot. U-boot can determine if using PSCI. If U-boot enables PSCI, it will add these missed parts in the dts. If not, it will not add these missed parts, so kernel will not use PSCI. In other words, the dts does not enable PSCI by default. It's U-boot which adds the missed part if it determines to use PSCI. Thanks, Shaohui From mboxrd@z Thu Jan 1 00:00:00 1970 From: "S.H. Xie" Subject: RE: [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support Date: Fri, 9 Sep 2016 06:55:30 +0000 Message-ID: References: <1473069695-33092-1-git-send-email-shh.xie@gmail.com> <1473069695-33092-4-git-send-email-shh.xie@gmail.com> <20160908131326.GE26570@leverpostej> <20160908131818.GF26570@leverpostej> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20160908131818.GF26570@leverpostej> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Mark Rutland Cc: "devicetree@vger.kernel.org" , Mihai Emilian Bantea , Horia Geanta Neag , "arnd@arndb.de" , "catalin.marinas@arm.com" , "Z.Q. Hou" , "will.deacon@arm.com" , "linux-kernel@vger.kernel.org" , "M.H. Lian" , "robh+dt@kernel.org" , Vincent Hu , "Q.Y. Gong" , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" , "C.H. Zhao" List-Id: devicetree@vger.kernel.org > On Thu, Sep 08, 2016 at 02:13:26PM +0100, Mark Rutland wrote: > > On Mon, Sep 05, 2016 at 06:01:31PM +0800, shh.xie@gmail.com wrote: > > > + cpus { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + cpu0: cpu@0 { > > > + device_type = "cpu"; > > > + compatible = "arm,cortex-a72"; > > > + reg = <0x0>; > > > + clocks = <&clockgen 1 0>; > > > + next-level-cache = <&l2>; > > > + cpu-idle-states = <&CPU_PH20>; > > > + }; > > > > [...] > > > > > + }; > > > + > > > + idle-states { > > > + entry-method = "arm,psci"; > > > + > > > + CPU_PH20: cpu-ph20 { > > > + compatible = "arm,idle-state"; > > > + idle-state-name = "PH20"; > > > + arm,psci-suspend-param = <0x00010000>; > > > + entry-latency-us = <1000>; > > > + exit-latency-us = <1000>; > > > + min-residency-us = <3000>; > > > + }; > > > + }; > > > > There's no PSCI node in this file, and none from am included file, so > > this doesn't look right. > > Looking again, none of the cpu nodes has an enable-method property, and > subsequent patches don't seem to add that to any cpu node. > > Has this DT actually been tested? [S.H] The PSCI node and the enable-method property are added by U-boot. U-boot can determine if using PSCI. If U-boot enables PSCI, it will add these missed parts in the dts. If not, it will not add these missed parts, so kernel will not use PSCI. In other words, the dts does not enable PSCI by default. It's U-boot which adds the missed part if it determines to use PSCI. Thanks, Shaohui From mboxrd@z Thu Jan 1 00:00:00 1970 From: shaohui.xie@nxp.com (S.H. Xie) Date: Fri, 9 Sep 2016 06:55:30 +0000 Subject: [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support In-Reply-To: <20160908131818.GF26570@leverpostej> References: <1473069695-33092-1-git-send-email-shh.xie@gmail.com> <1473069695-33092-4-git-send-email-shh.xie@gmail.com> <20160908131326.GE26570@leverpostej> <20160908131818.GF26570@leverpostej> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > On Thu, Sep 08, 2016 at 02:13:26PM +0100, Mark Rutland wrote: > > On Mon, Sep 05, 2016 at 06:01:31PM +0800, shh.xie at gmail.com wrote: > > > + cpus { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + cpu0: cpu at 0 { > > > + device_type = "cpu"; > > > + compatible = "arm,cortex-a72"; > > > + reg = <0x0>; > > > + clocks = <&clockgen 1 0>; > > > + next-level-cache = <&l2>; > > > + cpu-idle-states = <&CPU_PH20>; > > > + }; > > > > [...] > > > > > + }; > > > + > > > + idle-states { > > > + entry-method = "arm,psci"; > > > + > > > + CPU_PH20: cpu-ph20 { > > > + compatible = "arm,idle-state"; > > > + idle-state-name = "PH20"; > > > + arm,psci-suspend-param = <0x00010000>; > > > + entry-latency-us = <1000>; > > > + exit-latency-us = <1000>; > > > + min-residency-us = <3000>; > > > + }; > > > + }; > > > > There's no PSCI node in this file, and none from am included file, so > > this doesn't look right. > > Looking again, none of the cpu nodes has an enable-method property, and > subsequent patches don't seem to add that to any cpu node. > > Has this DT actually been tested? [S.H] The PSCI node and the enable-method property are added by U-boot. U-boot can determine if using PSCI. If U-boot enables PSCI, it will add these missed parts in the dts. If not, it will not add these missed parts, so kernel will not use PSCI. In other words, the dts does not enable PSCI by default. It's U-boot which adds the missed part if it determines to use PSCI. Thanks, Shaohui