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* [U-Boot] [PATCH 1/2] armv8/fsl-lsch2: refactor the clock system initialization
@ 2016-09-12  4:08 Zhiqiang Hou
  2016-09-12  4:08 ` [U-Boot] [PATCH 2/2] armv8/fsl-lsch3: consolidate " Zhiqiang Hou
                   ` (2 more replies)
  0 siblings, 3 replies; 11+ messages in thread
From: Zhiqiang Hou @ 2016-09-12  4:08 UTC (permalink / raw)
  To: u-boot

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Up to now, there are 3 kinds of SoC under Layerscape Chassis 2,
such as LS1043A, LS1046A and LS1012A. But the clocks tree has a
lot of difference, for instance the IP modules have different
divisors to get clock from Platform PLL. And the core cluster
and platform PLL maybe have different reference clock, such as
LS1012A. Another problem is which clock/PLL should be described
by sys_info->freq_systembus, it is confused in Chissis 2.

This patch is to map the sys_info->freq_systembus to the Platform
PLL, and handle the different divisor of IP modules separately
between different SoCs. And separate cluster and platform PLL
reference clock.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 96 ++++++++++++++++++----
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  1 +
 include/configs/ls1012a_common.h                   |  6 +-
 include/configs/ls1043a_common.h                   |  2 +-
 4 files changed, 86 insertions(+), 19 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 8922197..4fb736d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -52,22 +52,28 @@ void get_sys_info(struct sys_info *sys_info)
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+	unsigned long cluster_clk;
 
 	sys_info->freq_systembus = sysclk;
+#ifdef CONFIG_CLUSTER_CLK_FREQ
+	cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
+#else
+	cluster_clk = sysclk;
+#endif
 #ifdef CONFIG_DDR_CLK_FREQ
 	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
 #else
 	sys_info->freq_ddrbus = sysclk;
 #endif
 
-#ifdef CONFIG_LS1012A
-	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
-			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
-			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
-#else
+	/* The freq_systembus is used to record frequency of platform PLL */
 	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+
+#ifdef CONFIG_LS1012A
+	sys_info->freq_ddrbus = 2 * sys_info->freq_systembus;
+#else
 	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
@@ -76,7 +82,7 @@ void get_sys_info(struct sys_info *sys_info)
 	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
 		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
 		if (ratio[i] > 4)
-			freq_c_pll[i] = sysclk * ratio[i];
+			freq_c_pll[i] = cluster_clk * ratio[i];
 		else
 			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
 	}
@@ -91,11 +97,6 @@ void get_sys_info(struct sys_info *sys_info)
 			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
 
-#ifdef CONFIG_LS1012A
-	sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
-	sys_info->freq_ddrbus *= 2;
-#endif
-
 #define HWA_CGA_M1_CLK_SEL	0xe0000000
 #define HWA_CGA_M1_CLK_SHIFT	29
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -148,7 +149,11 @@ void get_sys_info(struct sys_info *sys_info)
 		break;
 	}
 #else
+#ifdef CONFIG_LS1043A
 	sys_info->freq_sdhc = sys_info->freq_systembus;
+#elif defined(CONFIG_LS1046A) || defined(CONFIG_LS1012A)
+	sys_info->freq_sdhc = sys_info->freq_systembus / 2;
+#endif
 #endif
 #endif
 
@@ -156,7 +161,11 @@ void get_sys_info(struct sys_info *sys_info)
 	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
 	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
 
+#ifdef CONFIG_LS1043A
 	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+#elif defined(CONFIG_LS1046A)
+	sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr;
+#endif
 #endif
 }
 
@@ -179,41 +188,98 @@ int get_clocks(void)
 		return 1;
 }
 
+/********************************************
+ * get_bus_freq
+ * return platform PLL freq in Hz
+ *********************************************/
 ulong get_bus_freq(ulong dummy)
 {
+	if (!gd->bus_clk)
+		get_clocks();
+
 	return gd->bus_clk;
 }
 
 ulong get_ddr_freq(ulong dummy)
 {
+	if (!gd->mem_clk)
+		get_clocks();
+
 	return gd->mem_clk;
 }
 
 #ifdef CONFIG_FSL_ESDHC
 int get_sdhc_freq(ulong dummy)
 {
+	if (!gd->arch.sdhc_clk)
+		get_clocks();
+
 	return gd->arch.sdhc_clk;
 }
 #endif
 
 int get_serial_clock(void)
 {
-	return gd->bus_clk;
+#ifdef CONFIG_LS1043A
+	return get_bus_freq(0);
+#elif defined(CONFIG_LS1046A)
+	return get_bus_freq(0) / 2;
+#elif defined(CONFIG_LS1012A)
+	return get_bus_freq(0) / 4;
+#else
+	return 0;
+#endif
+}
+
+int get_i2c_freq(ulong dummy)
+{
+#ifdef CONFIG_LS1043A
+	return get_bus_freq(0);
+#elif defined(CONFIG_LS1046A)
+	return get_bus_freq(0) / 2;
+#elif defined(CONFIG_LS1012A)
+	return get_bus_freq(0) / 4;
+#else
+	return 0;
+#endif
 }
 
+int get_dspi_freq(ulong dummy)
+{
+#ifdef CONFIG_LS1043A
+	return get_bus_freq(0);
+#elif defined(CONFIG_LS1046A)
+	return get_bus_freq(0) / 2;
+#elif defined(CONFIG_LS1012A)
+	return get_bus_freq(0) / 4;
+#else
+	return 0;
+#endif
+}
+
+int get_uart_freq(ulong dummy)
+{
+#ifdef CONFIG_LS1043A
+	return get_bus_freq(0);
+#elif defined(CONFIG_LS1046A)
+	return get_bus_freq(0) / 2;
+#else
+	return 0;
+#endif
+}
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {
 	case MXC_I2C_CLK:
-		return get_bus_freq(0);
+		return get_i2c_freq(0);
 #if defined(CONFIG_FSL_ESDHC)
 	case MXC_ESDHC_CLK:
 		return get_sdhc_freq(0);
 #endif
 	case MXC_DSPI_CLK:
-		return get_bus_freq(0);
+		return get_dspi_freq(0);
 	case MXC_UART_CLK:
-		return get_bus_freq(0);
+		return get_uart_freq(0);
 	default:
 		printf("Unsupported clock\n");
 	}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 95a4293..ee10765 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -136,6 +136,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
 
 struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];
+	/* frequency of platform PLL */
 	unsigned long freq_systembus;
 	unsigned long freq_ddrbus;
 	unsigned long freq_localbus;
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index fba2fac..928fd76 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -24,8 +24,8 @@
 #define CONFIG_SYS_TEXT_BASE		0x40100000
 
 #define CONFIG_SYS_FSL_CLK
-#define CONFIG_SYS_CLK_FREQ		100000000
-#define CONFIG_DDR_CLK_FREQ		125000000
+#define CONFIG_SYS_CLK_FREQ		125000000
+#define CONFIG_CLUSTER_CLK_FREQ		100000000
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F	1
@@ -86,7 +86,7 @@
 #define CONFIG_CONS_INDEX       1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE     1
-#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
+#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
 
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index e55fcb2..3b55699 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -50,7 +50,7 @@
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))
+#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
 
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-- 
2.1.0.27.g96db324

^ permalink raw reply related	[flat|nested] 11+ messages in thread
end of thread, other threads:[~2016-09-14  9:56 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-09-12  4:08 [U-Boot] [PATCH 1/2] armv8/fsl-lsch2: refactor the clock system initialization Zhiqiang Hou
2016-09-12  4:08 ` [U-Boot] [PATCH 2/2] armv8/fsl-lsch3: consolidate " Zhiqiang Hou
2016-09-13  7:22   ` Prabhakar Kushwaha
2016-09-13  9:09     ` Z.Q. Hou
2016-09-13 10:03       ` Prabhakar Kushwaha
2016-09-14  2:45         ` Z.Q. Hou
2016-09-14  8:18           ` Prabhakar Kushwaha
2016-09-14  9:56             ` Z.Q. Hou
2016-09-12 16:37 ` [U-Boot] [PATCH 1/2] armv8/fsl-lsch2: refactor " york sun
2016-09-13  7:17 ` Prabhakar Kushwaha
2016-09-13  8:52   ` Z.Q. Hou

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