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x-microsoft-antispam-message-info: rNDXW13XYMw/17h+OTPs7qz949PkmudYbWXrxVrwHa09XHgkfmLZ2GviS8X4/WxmgSycAkL+ulGoSUQG+AvSET1oA/BKhLYbk9Gf2mpJDM1mzHwPPn56U6swIaUNNfBjIVN0okLJ/7xs7HCelyaB+bhy5sPdmyHqL+D+fawd+7+03H8TYZx/O+YOYWLTZPfLXV5oYQF7mCtj8NhsLYaI+Ouj3dB8IhvAZh3CdusYEG96XZsF5Hi+KyUOgnEDH4e5Flyo32zT5SQ1ojUuAEvptpGGIxP9ye6nXsvDzd1FJADOhvVVDFzVpsUEp1bSnchEsZCvVNJtljfGcyRnEQB+Edo6iCxHFn37SUB6wJ+w2T3BwABAa9/GNxkiIlTp8z6HwvQx/HN9D3GJ6W7rOdBHoFVrTGzVBz7vjZM2EkevlDo5/nJmRRqfKv+IVM21tTFi x-ms-exchange-antispam-messagedata: pPpdlJhqdIF4DFqVJbFm1CEA6b3guUXjBUwFEEYGyOD6sHPH70igUJOOeMiVz1zxYUx4yX46DYaUSreiFP8QLfDt7GjzweW6ARtDl+zjP6oT3OY+066qS/CCjCsTi/J9WJb3dt6ybbWFzA9eDub2WKrkzU9qyDYFFiW/E30mQzX/vYwOkqhKFvuXF56tU/qMFIMS/WxT08i6aln9RxuHsNtBXMcBoLySIUwCDoBGtYeCaLIHbS+LHU98aGoQdWpjMmfh0iz2HunyuKCbEq+e4IVFCkPdwDkNHlbNiDpK9G6O6H+xkdmm5wvnAehsVaOiG4a3xW4+a3AhKKi3/melrNL8Jelh+jMDZLf4MPXS/gEYvUMGJoYIq5Lgz2P/vfeW+tm+z6KNOY1fHKWOiRULVDu1W/HO/OKEqh2kw4IvUyqtVVT6j5KAlgVBZs3ph5XHiwGJwXP1E5oM0d8dSD73SUsrJbApoSfOnuUEs4W5wghOo9CeO5sufWhEUZx4Z8+tI8fSTCZNWLgsUnOCorFCXgQkjMSSr8QErkbsDLEMrCP2qDk1dnXv6vf+x7gO2kLuMrYWGVjJtbx2SSGe391F/TCAXkRxKx0gDPSsPL/1Vd9WHxRKVtaGu9wHBbNm9ODrRo1vHcjZTye7Gr84TtA2sm3iLPq2BnuIXFkUYcugNrn2eF5mKnjcF9Mb+Iu+BP5b9Z3wBYLNRdSp0DqPIBadBQNU52aTO3V3fmfn6nwh/dwY71uqUnpquUcVuSWMlkYYJwYqiZ+MOwt0wBq+DCYHv8lUkdQd91NLqMGQRpc7dA8= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 758498ee-021a-4f91-7c6a-08d7eb109fef X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Apr 2020 01:08:12.9221 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Prmns/pJxcugQFHNNNBS3P3ft323GBjiAw5dl3Hd2LF55N2gMUXCQ9ajBv452MXloLquxUh7wXnYZ8VPYU/txA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0402MB2759 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite > clk >=20 > On 2020-04-27 12:15 PM, Peng Fan wrote: > >> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M > >> composite clk > >> > >> On 2020-03-12 12:27 PM, Peng Fan wrote: > >>> From: Peng Fan > >>> > >>> The CORE/BUS root slice has following design, simplied graph: > >>> The difference is core not have pre_div block. > >>> A composite core/bus clk has 8 inputs for mux to select, saying clk[0= -7]. > >>> > >>> SEL_A GA > >>> +--+ +-+ > >>> | +->+ +------+ > >>> CLK[0-7]--->+ | +-+ | > >>> | | | +----v---+ +----+ > >>> | +--+ |pre_diva+----> | +---------+ > >>> | +--------+ |mux +--+post_div | > >>> | +--+ |pre_divb+--->+ | +---------+ > >>> | | | +----^---+ +----+ > >>> +--->+ | +-+ | > >>> | +->+ +------+ > >>> +--+ +-+ > >>> SEL_B GB > >>> > >>> There will be system hang, when doing the following steps: > >>> 1. switch mux from clk0 to clk1 > >>> 2. gate off clk0 > >>> 3. swtich from clk1 to clk2, or gate off clk1 > >>> > >>> Step 3 triggers system hang. > >>> > >>> If we skip step2, keep clk0 on, step 3 will not trigger system hang. > >>> However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare > >>> disable the clk0 which will not be used. > >> > >> As far as I understand when switching from clk1 to clk2 this is done > >> by temporarily switching the rightmost SELECT mux to whatever was in > >> the spare SEL, which is essentially arbitrary from linux POV. > > > > No. The fixes in this patches has been confirmed by IC design owner > > > >> > >> This is quite unexpected but in theory it might be desirable to use a > >> third parent as a fallback. > > > > No. this will make things complicated. To CCM SEL_A and SEL_B, it is > > controlled by a hardware counter. Saying you write n times to the > > target interface. > > > > The mux will use n % 2 to choose SEL_A or SEL_B. write twice to make > > sure SEL_A and SEL_B has the same value. >=20 > What if SEL_A and SEL_B have different values on boot? The first time lin= ux > does set_parent it will switch to the other SEL_X which might be off. If SEL_A and SEL_B has different values on boot, SEL_A or SEL_B will be effective according internal counter. There must be one chosen for mux usage whether SEL_A or SEL_B. The CCM ROOT slice only has SEL_A and SEL_B, no SEL_X. SEL_A and SEL_B both have 7 mux inputs. Thanks, Peng. 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Tue, 28 Apr 2020 01:08:13 +0000 Received: from DB6PR0402MB2760.eurprd04.prod.outlook.com ([fe80::d17b:d767:19c3:b871]) by DB6PR0402MB2760.eurprd04.prod.outlook.com ([fe80::d17b:d767:19c3:b871%6]) with mapi id 15.20.2937.020; Tue, 28 Apr 2020 01:08:13 +0000 From: Peng Fan To: Leonard Crestez , Anson Huang Subject: RE: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk Thread-Topic: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk Thread-Index: AQHV+FjOyMJp4JjxAkWF8jtS4KMMQqiOAaZg Date: Tue, 28 Apr 2020 01:08:12 +0000 Message-ID: References: <1584008384-11578-1-git-send-email-peng.fan@nxp.com> <1584008384-11578-8-git-send-email-peng.fan@nxp.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; x-originating-ip: [119.31.174.71] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 758498ee-021a-4f91-7c6a-08d7eb109fef x-ms-traffictypediagnostic: DB6PR0402MB2759:|DB6PR0402MB2759: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org > Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite > clk > > On 2020-04-27 12:15 PM, Peng Fan wrote: > >> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M > >> composite clk > >> > >> On 2020-03-12 12:27 PM, Peng Fan wrote: > >>> From: Peng Fan > >>> > >>> The CORE/BUS root slice has following design, simplied graph: > >>> The difference is core not have pre_div block. > >>> A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7]. > >>> > >>> SEL_A GA > >>> +--+ +-+ > >>> | +->+ +------+ > >>> CLK[0-7]--->+ | +-+ | > >>> | | | +----v---+ +----+ > >>> | +--+ |pre_diva+----> | +---------+ > >>> | +--------+ |mux +--+post_div | > >>> | +--+ |pre_divb+--->+ | +---------+ > >>> | | | +----^---+ +----+ > >>> +--->+ | +-+ | > >>> | +->+ +------+ > >>> +--+ +-+ > >>> SEL_B GB > >>> > >>> There will be system hang, when doing the following steps: > >>> 1. switch mux from clk0 to clk1 > >>> 2. gate off clk0 > >>> 3. swtich from clk1 to clk2, or gate off clk1 > >>> > >>> Step 3 triggers system hang. > >>> > >>> If we skip step2, keep clk0 on, step 3 will not trigger system hang. > >>> However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare > >>> disable the clk0 which will not be used. > >> > >> As far as I understand when switching from clk1 to clk2 this is done > >> by temporarily switching the rightmost SELECT mux to whatever was in > >> the spare SEL, which is essentially arbitrary from linux POV. > > > > No. The fixes in this patches has been confirmed by IC design owner > > > >> > >> This is quite unexpected but in theory it might be desirable to use a > >> third parent as a fallback. > > > > No. this will make things complicated. To CCM SEL_A and SEL_B, it is > > controlled by a hardware counter. Saying you write n times to the > > target interface. > > > > The mux will use n % 2 to choose SEL_A or SEL_B. write twice to make > > sure SEL_A and SEL_B has the same value. > > What if SEL_A and SEL_B have different values on boot? The first time linux > does set_parent it will switch to the other SEL_X which might be off. If SEL_A and SEL_B has different values on boot, SEL_A or SEL_B will be effective according internal counter. There must be one chosen for mux usage whether SEL_A or SEL_B. The CCM ROOT slice only has SEL_A and SEL_B, no SEL_X. SEL_A and SEL_B both have 7 mux inputs. Thanks, Peng. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel