* [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-03-20 2:37 ` Yuantian Tang
0 siblings, 0 replies; 45+ messages in thread
From: Yuantian Tang @ 2017-03-20 2:37 UTC (permalink / raw)
To: mturquette
Cc: sboyd, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood, Tang Yuantian
From: Scott Wood <oss@buserror.net>
ls1012a has separate input root clocks for core PLLs versus the platform
PLL, with the latter described as sysclk in the hw docs.
Update the qoriq-clock binding to allow a second input clock, named
"coreclk". If present, this clock will be used for the core PLLs.
Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v2:
-- change the author to Scott
Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index aa3526f..119cafd 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -56,6 +56,11 @@ Optional properties:
- clocks: If clock-frequency is not specified, sysclk may be provided
as an input clock. Either clock-frequency or clocks must be
provided.
+ A second input clock, called "coreclk", may be provided if
+ core PLLs are based on a different input clock from the
+ platform PLL.
+- clock-names: Required if a coreclk is present. Valid names are
+ "sysclk" and "coreclk".
2. Clock Provider
@@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
2 hwaccel index (n in CLKCGnHWACSR)
3 fman 0 for fm1, 1 for fm2
4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+ 5 coreclk must be 0
3. Example
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-03-20 2:37 ` Yuantian Tang
0 siblings, 0 replies; 45+ messages in thread
From: Yuantian Tang @ 2017-03-20 2:37 UTC (permalink / raw)
To: mturquette
Cc: sboyd, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood, Tang Yuantian
From: Scott Wood <oss@buserror.net>
ls1012a has separate input root clocks for core PLLs versus the platform
PLL, with the latter described as sysclk in the hw docs.
Update the qoriq-clock binding to allow a second input clock, named
"coreclk". If present, this clock will be used for the core PLLs.
Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v2:
-- change the author to Scott
Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index aa3526f..119cafd 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -56,6 +56,11 @@ Optional properties:
- clocks: If clock-frequency is not specified, sysclk may be provided
as an input clock. Either clock-frequency or clocks must be
provided.
+ A second input clock, called "coreclk", may be provided if
+ core PLLs are based on a different input clock from the
+ platform PLL.
+- clock-names: Required if a coreclk is present. Valid names are
+ "sysclk" and "coreclk".
2. Clock Provider
@@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
2 hwaccel index (n in CLKCGnHWACSR)
3 fman 0 for fm1, 1 for fm2
4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+ 5 coreclk must be 0
3. Example
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-03-20 2:37 ` Yuantian Tang
0 siblings, 0 replies; 45+ messages in thread
From: Yuantian Tang @ 2017-03-20 2:37 UTC (permalink / raw)
To: linux-arm-kernel
From: Scott Wood <oss@buserror.net>
ls1012a has separate input root clocks for core PLLs versus the platform
PLL, with the latter described as sysclk in the hw docs.
Update the qoriq-clock binding to allow a second input clock, named
"coreclk". If present, this clock will be used for the core PLLs.
Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v2:
-- change the author to Scott
Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index aa3526f..119cafd 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -56,6 +56,11 @@ Optional properties:
- clocks: If clock-frequency is not specified, sysclk may be provided
as an input clock. Either clock-frequency or clocks must be
provided.
+ A second input clock, called "coreclk", may be provided if
+ core PLLs are based on a different input clock from the
+ platform PLL.
+- clock-names: Required if a coreclk is present. Valid names are
+ "sysclk" and "coreclk".
2. Clock Provider
@@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
2 hwaccel index (n in CLKCGnHWACSR)
3 fman 0 for fm1, 1 for fm2
4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+ 5 coreclk must be 0
3. Example
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
2017-03-20 2:37 ` Yuantian Tang
(?)
@ 2017-03-20 2:37 ` Yuantian Tang
-1 siblings, 0 replies; 45+ messages in thread
From: Yuantian Tang @ 2017-03-20 2:37 UTC (permalink / raw)
To: mturquette
Cc: sboyd, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood, Tang Yuantian
From: Scott Wood <oss@buserror.net>
ls1012a has separate input root clocks for core PLLs versus the
platform PLL, with the latter described as sysclk in the hw docs.
If a second input clock, named "coreclk", is present, this clock will be
used for the core PLLs.
Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v2:
-- change the author to Scott.
drivers/clk/clk-qoriq.c | 91 +++++++++++++++++++++++++++++++++++++++++--------
1 file changed, 77 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index d0bf8b1..f3931e3 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -87,7 +87,7 @@ struct clockgen {
struct device_node *node;
void __iomem *regs;
struct clockgen_chipinfo info; /* mutable copy */
- struct clk *sysclk;
+ struct clk *sysclk, *coreclk;
struct clockgen_pll pll[6];
struct clk *cmux[NUM_CMUX];
struct clk *hwaccel[NUM_HWACCEL];
@@ -904,7 +904,12 @@ static void __init create_muxes(struct clockgen *cg)
static void __init clockgen_init(struct device_node *np);
-/* Legacy nodes may get probed before the parent clockgen node */
+/*
+ * Legacy nodes may get probed before the parent clockgen node.
+ * It is assumed that device trees with legacy nodes will not
+ * contain a "clocks" property -- otherwise the input clocks may
+ * not be initialized at this point.
+ */
static void __init legacy_init_clockgen(struct device_node *np)
{
if (!clockgen.node)
@@ -945,18 +950,13 @@ static struct clk __init
return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
}
-static struct clk *sysclk_from_parent(const char *name)
+static struct clk __init *input_clock(const char *name, struct clk *clk)
{
- struct clk *clk;
- const char *parent_name;
-
- clk = of_clk_get(clockgen.node, 0);
- if (IS_ERR(clk))
- return clk;
+ const char *input_name;
/* Register the input clock under the desired name. */
- parent_name = __clk_get_name(clk);
- clk = clk_register_fixed_factor(NULL, name, parent_name,
+ input_name = __clk_get_name(clk);
+ clk = clk_register_fixed_factor(NULL, name, input_name,
0, 1, 1);
if (IS_ERR(clk))
pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
@@ -965,6 +965,29 @@ static struct clk *sysclk_from_parent(const char *name)
return clk;
}
+static struct clk __init *input_clock_by_name(const char *name,
+ const char *dtname)
+{
+ struct clk *clk;
+
+ clk = of_clk_get_by_name(clockgen.node, dtname);
+ if (IS_ERR(clk))
+ return clk;
+
+ return input_clock(name, clk);
+}
+
+static struct clk __init *input_clock_by_index(const char *name, int idx)
+{
+ struct clk *clk;
+
+ clk = of_clk_get(clockgen.node, 0);
+ if (IS_ERR(clk))
+ return clk;
+
+ return input_clock(name, clk);
+}
+
static struct clk * __init create_sysclk(const char *name)
{
struct device_node *sysclk;
@@ -974,7 +997,11 @@ static struct clk * __init create_sysclk(const char *name)
if (!IS_ERR(clk))
return clk;
- clk = sysclk_from_parent(name);
+ clk = input_clock_by_name(name, "sysclk");
+ if (!IS_ERR(clk))
+ return clk;
+
+ clk = input_clock_by_index(name, 0);
if (!IS_ERR(clk))
return clk;
@@ -985,7 +1012,27 @@ static struct clk * __init create_sysclk(const char *name)
return clk;
}
- pr_err("%s: No input clock\n", __func__);
+ pr_err("%s: No input sysclk\n", __func__);
+ return NULL;
+}
+
+static struct clk * __init create_coreclk(const char *name)
+{
+ struct clk *clk;
+
+ clk = input_clock_by_name(name, "coreclk");
+ if (!IS_ERR(clk))
+ return clk;
+
+ /*
+ * This indicates a mix of legacy nodes with the new coreclk
+ * mechanism, which should never happen. If this error occurs,
+ * don't use the wrong input clock just because coreclk isn't
+ * ready yet.
+ */
+ if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
+ return clk;
+
return NULL;
}
@@ -1008,11 +1055,19 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
u32 __iomem *reg;
u32 mult;
struct clockgen_pll *pll = &cg->pll[idx];
+ const char *input = "cg-sysclk";
int i;
if (!(cg->info.pll_mask & (1 << idx)))
return;
+ if (cg->coreclk && idx != PLATFORM_PLL) {
+ if (IS_ERR(cg->coreclk))
+ return;
+
+ input = "cg-coreclk";
+ }
+
if (cg->info.flags & CG_VER3) {
switch (idx) {
case PLATFORM_PLL:
@@ -1063,7 +1118,7 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
"cg-pll%d-div%d", idx, i + 1);
clk = clk_register_fixed_factor(NULL,
- pll->div[i].name, "cg-sysclk", 0, mult, i + 1);
+ pll->div[i].name, input, 0, mult, i + 1);
if (IS_ERR(clk)) {
pr_err("%s: %s: register failed %ld\n",
__func__, pll->div[i].name, PTR_ERR(clk));
@@ -1200,6 +1255,13 @@ static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
goto bad_args;
clk = pll->div[idx].clk;
break;
+ case 5:
+ if (idx != 0)
+ goto bad_args;
+ clk = cg->coreclk;
+ if (IS_ERR(clk))
+ clk = NULL;
+ break;
default:
goto bad_args;
}
@@ -1311,6 +1373,7 @@ static void __init clockgen_init(struct device_node *np)
clockgen.info.flags |= CG_CMUX_GE_PLAT;
clockgen.sysclk = create_sysclk("cg-sysclk");
+ clockgen.coreclk = create_coreclk("cg-coreclk");
create_plls(&clockgen);
create_muxes(&clockgen);
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
@ 2017-03-20 2:37 ` Yuantian Tang
0 siblings, 0 replies; 45+ messages in thread
From: Yuantian Tang @ 2017-03-20 2:37 UTC (permalink / raw)
To: mturquette
Cc: sboyd, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood, Tang Yuantian
From: Scott Wood <oss@buserror.net>
ls1012a has separate input root clocks for core PLLs versus the
platform PLL, with the latter described as sysclk in the hw docs.
If a second input clock, named "coreclk", is present, this clock will be
used for the core PLLs.
Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v2:
-- change the author to Scott.
drivers/clk/clk-qoriq.c | 91 +++++++++++++++++++++++++++++++++++++++++--------
1 file changed, 77 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index d0bf8b1..f3931e3 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -87,7 +87,7 @@ struct clockgen {
struct device_node *node;
void __iomem *regs;
struct clockgen_chipinfo info; /* mutable copy */
- struct clk *sysclk;
+ struct clk *sysclk, *coreclk;
struct clockgen_pll pll[6];
struct clk *cmux[NUM_CMUX];
struct clk *hwaccel[NUM_HWACCEL];
@@ -904,7 +904,12 @@ static void __init create_muxes(struct clockgen *cg)
static void __init clockgen_init(struct device_node *np);
-/* Legacy nodes may get probed before the parent clockgen node */
+/*
+ * Legacy nodes may get probed before the parent clockgen node.
+ * It is assumed that device trees with legacy nodes will not
+ * contain a "clocks" property -- otherwise the input clocks may
+ * not be initialized at this point.
+ */
static void __init legacy_init_clockgen(struct device_node *np)
{
if (!clockgen.node)
@@ -945,18 +950,13 @@ static struct clk __init
return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
}
-static struct clk *sysclk_from_parent(const char *name)
+static struct clk __init *input_clock(const char *name, struct clk *clk)
{
- struct clk *clk;
- const char *parent_name;
-
- clk = of_clk_get(clockgen.node, 0);
- if (IS_ERR(clk))
- return clk;
+ const char *input_name;
/* Register the input clock under the desired name. */
- parent_name = __clk_get_name(clk);
- clk = clk_register_fixed_factor(NULL, name, parent_name,
+ input_name = __clk_get_name(clk);
+ clk = clk_register_fixed_factor(NULL, name, input_name,
0, 1, 1);
if (IS_ERR(clk))
pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
@@ -965,6 +965,29 @@ static struct clk *sysclk_from_parent(const char *name)
return clk;
}
+static struct clk __init *input_clock_by_name(const char *name,
+ const char *dtname)
+{
+ struct clk *clk;
+
+ clk = of_clk_get_by_name(clockgen.node, dtname);
+ if (IS_ERR(clk))
+ return clk;
+
+ return input_clock(name, clk);
+}
+
+static struct clk __init *input_clock_by_index(const char *name, int idx)
+{
+ struct clk *clk;
+
+ clk = of_clk_get(clockgen.node, 0);
+ if (IS_ERR(clk))
+ return clk;
+
+ return input_clock(name, clk);
+}
+
static struct clk * __init create_sysclk(const char *name)
{
struct device_node *sysclk;
@@ -974,7 +997,11 @@ static struct clk * __init create_sysclk(const char *name)
if (!IS_ERR(clk))
return clk;
- clk = sysclk_from_parent(name);
+ clk = input_clock_by_name(name, "sysclk");
+ if (!IS_ERR(clk))
+ return clk;
+
+ clk = input_clock_by_index(name, 0);
if (!IS_ERR(clk))
return clk;
@@ -985,7 +1012,27 @@ static struct clk * __init create_sysclk(const char *name)
return clk;
}
- pr_err("%s: No input clock\n", __func__);
+ pr_err("%s: No input sysclk\n", __func__);
+ return NULL;
+}
+
+static struct clk * __init create_coreclk(const char *name)
+{
+ struct clk *clk;
+
+ clk = input_clock_by_name(name, "coreclk");
+ if (!IS_ERR(clk))
+ return clk;
+
+ /*
+ * This indicates a mix of legacy nodes with the new coreclk
+ * mechanism, which should never happen. If this error occurs,
+ * don't use the wrong input clock just because coreclk isn't
+ * ready yet.
+ */
+ if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
+ return clk;
+
return NULL;
}
@@ -1008,11 +1055,19 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
u32 __iomem *reg;
u32 mult;
struct clockgen_pll *pll = &cg->pll[idx];
+ const char *input = "cg-sysclk";
int i;
if (!(cg->info.pll_mask & (1 << idx)))
return;
+ if (cg->coreclk && idx != PLATFORM_PLL) {
+ if (IS_ERR(cg->coreclk))
+ return;
+
+ input = "cg-coreclk";
+ }
+
if (cg->info.flags & CG_VER3) {
switch (idx) {
case PLATFORM_PLL:
@@ -1063,7 +1118,7 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
"cg-pll%d-div%d", idx, i + 1);
clk = clk_register_fixed_factor(NULL,
- pll->div[i].name, "cg-sysclk", 0, mult, i + 1);
+ pll->div[i].name, input, 0, mult, i + 1);
if (IS_ERR(clk)) {
pr_err("%s: %s: register failed %ld\n",
__func__, pll->div[i].name, PTR_ERR(clk));
@@ -1200,6 +1255,13 @@ static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
goto bad_args;
clk = pll->div[idx].clk;
break;
+ case 5:
+ if (idx != 0)
+ goto bad_args;
+ clk = cg->coreclk;
+ if (IS_ERR(clk))
+ clk = NULL;
+ break;
default:
goto bad_args;
}
@@ -1311,6 +1373,7 @@ static void __init clockgen_init(struct device_node *np)
clockgen.info.flags |= CG_CMUX_GE_PLAT;
clockgen.sysclk = create_sysclk("cg-sysclk");
+ clockgen.coreclk = create_coreclk("cg-coreclk");
create_plls(&clockgen);
create_muxes(&clockgen);
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
@ 2017-03-20 2:37 ` Yuantian Tang
0 siblings, 0 replies; 45+ messages in thread
From: Yuantian Tang @ 2017-03-20 2:37 UTC (permalink / raw)
To: linux-arm-kernel
From: Scott Wood <oss@buserror.net>
ls1012a has separate input root clocks for core PLLs versus the
platform PLL, with the latter described as sysclk in the hw docs.
If a second input clock, named "coreclk", is present, this clock will be
used for the core PLLs.
Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v2:
-- change the author to Scott.
drivers/clk/clk-qoriq.c | 91 +++++++++++++++++++++++++++++++++++++++++--------
1 file changed, 77 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index d0bf8b1..f3931e3 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -87,7 +87,7 @@ struct clockgen {
struct device_node *node;
void __iomem *regs;
struct clockgen_chipinfo info; /* mutable copy */
- struct clk *sysclk;
+ struct clk *sysclk, *coreclk;
struct clockgen_pll pll[6];
struct clk *cmux[NUM_CMUX];
struct clk *hwaccel[NUM_HWACCEL];
@@ -904,7 +904,12 @@ static void __init create_muxes(struct clockgen *cg)
static void __init clockgen_init(struct device_node *np);
-/* Legacy nodes may get probed before the parent clockgen node */
+/*
+ * Legacy nodes may get probed before the parent clockgen node.
+ * It is assumed that device trees with legacy nodes will not
+ * contain a "clocks" property -- otherwise the input clocks may
+ * not be initialized at this point.
+ */
static void __init legacy_init_clockgen(struct device_node *np)
{
if (!clockgen.node)
@@ -945,18 +950,13 @@ static struct clk __init
return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
}
-static struct clk *sysclk_from_parent(const char *name)
+static struct clk __init *input_clock(const char *name, struct clk *clk)
{
- struct clk *clk;
- const char *parent_name;
-
- clk = of_clk_get(clockgen.node, 0);
- if (IS_ERR(clk))
- return clk;
+ const char *input_name;
/* Register the input clock under the desired name. */
- parent_name = __clk_get_name(clk);
- clk = clk_register_fixed_factor(NULL, name, parent_name,
+ input_name = __clk_get_name(clk);
+ clk = clk_register_fixed_factor(NULL, name, input_name,
0, 1, 1);
if (IS_ERR(clk))
pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
@@ -965,6 +965,29 @@ static struct clk *sysclk_from_parent(const char *name)
return clk;
}
+static struct clk __init *input_clock_by_name(const char *name,
+ const char *dtname)
+{
+ struct clk *clk;
+
+ clk = of_clk_get_by_name(clockgen.node, dtname);
+ if (IS_ERR(clk))
+ return clk;
+
+ return input_clock(name, clk);
+}
+
+static struct clk __init *input_clock_by_index(const char *name, int idx)
+{
+ struct clk *clk;
+
+ clk = of_clk_get(clockgen.node, 0);
+ if (IS_ERR(clk))
+ return clk;
+
+ return input_clock(name, clk);
+}
+
static struct clk * __init create_sysclk(const char *name)
{
struct device_node *sysclk;
@@ -974,7 +997,11 @@ static struct clk * __init create_sysclk(const char *name)
if (!IS_ERR(clk))
return clk;
- clk = sysclk_from_parent(name);
+ clk = input_clock_by_name(name, "sysclk");
+ if (!IS_ERR(clk))
+ return clk;
+
+ clk = input_clock_by_index(name, 0);
if (!IS_ERR(clk))
return clk;
@@ -985,7 +1012,27 @@ static struct clk * __init create_sysclk(const char *name)
return clk;
}
- pr_err("%s: No input clock\n", __func__);
+ pr_err("%s: No input sysclk\n", __func__);
+ return NULL;
+}
+
+static struct clk * __init create_coreclk(const char *name)
+{
+ struct clk *clk;
+
+ clk = input_clock_by_name(name, "coreclk");
+ if (!IS_ERR(clk))
+ return clk;
+
+ /*
+ * This indicates a mix of legacy nodes with the new coreclk
+ * mechanism, which should never happen. If this error occurs,
+ * don't use the wrong input clock just because coreclk isn't
+ * ready yet.
+ */
+ if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
+ return clk;
+
return NULL;
}
@@ -1008,11 +1055,19 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
u32 __iomem *reg;
u32 mult;
struct clockgen_pll *pll = &cg->pll[idx];
+ const char *input = "cg-sysclk";
int i;
if (!(cg->info.pll_mask & (1 << idx)))
return;
+ if (cg->coreclk && idx != PLATFORM_PLL) {
+ if (IS_ERR(cg->coreclk))
+ return;
+
+ input = "cg-coreclk";
+ }
+
if (cg->info.flags & CG_VER3) {
switch (idx) {
case PLATFORM_PLL:
@@ -1063,7 +1118,7 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
"cg-pll%d-div%d", idx, i + 1);
clk = clk_register_fixed_factor(NULL,
- pll->div[i].name, "cg-sysclk", 0, mult, i + 1);
+ pll->div[i].name, input, 0, mult, i + 1);
if (IS_ERR(clk)) {
pr_err("%s: %s: register failed %ld\n",
__func__, pll->div[i].name, PTR_ERR(clk));
@@ -1200,6 +1255,13 @@ static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
goto bad_args;
clk = pll->div[idx].clk;
break;
+ case 5:
+ if (idx != 0)
+ goto bad_args;
+ clk = cg->coreclk;
+ if (IS_ERR(clk))
+ clk = NULL;
+ break;
default:
goto bad_args;
}
@@ -1311,6 +1373,7 @@ static void __init clockgen_init(struct device_node *np)
clockgen.info.flags |= CG_CMUX_GE_PLAT;
clockgen.sysclk = create_sysclk("cg-sysclk");
+ clockgen.coreclk = create_coreclk("cg-coreclk");
create_plls(&clockgen);
create_muxes(&clockgen);
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-03-27 3:39 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-03-27 3:39 UTC (permalink / raw)
To: mturquette
Cc: sboyd, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood
PING!
Regards,
Yuantian
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette@baylibre.com
> Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood;
> Andy Tang
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the platform PLL,
> with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-03-27 3:39 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-03-27 3:39 UTC (permalink / raw)
To: mturquette-rdvid1DuHRBWk0Htik3J/w
Cc: sboyd-sgV2jX0FEOL9JmXXK+q4OQ, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-clk-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Scott Wood
PING!
Regards,
Yuantian
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang-3arQi8VN3Tc@public.gmane.org]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org
> Cc: sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org; robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org; mark.rutland-5wv7dgnIgG8@public.gmane.org;
> linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-
> kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; Scott Wood;
> Andy Tang
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
>
> ls1012a has separate input root clocks for core PLLs versus the platform PLL,
> with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
> Signed-off-by: Tang Yuantian <andy.tang-3arQi8VN3Tc@public.gmane.org>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-03-27 3:39 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-03-27 3:39 UTC (permalink / raw)
To: mturquette
Cc: sboyd, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood
PING!
Regards,
Yuantian
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette@baylibre.com
> Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood;
> Andy Tang
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>=20
> From: Scott Wood <oss@buserror.net>
>=20
> ls1012a has separate input root clocks for core PLLs versus the platform =
PLL,
> with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>=20
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>=20
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>=20
> 2. Clock Provider
>=20
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=3Dpll, 1=3Dpll/2, 2=3Dpll/3, 3=3Dpll/4
> + 5 coreclk must be 0
>=20
> 3. Example
>=20
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-03-27 3:39 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-03-27 3:39 UTC (permalink / raw)
To: linux-arm-kernel
PING!
Regards,
Yuantian
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang at nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette at baylibre.com
> Cc: sboyd at codeaurora.org; robh+dt at kernel.org; mark.rutland at arm.com;
> linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-
> kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Scott Wood;
> Andy Tang
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the platform PLL,
> with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
2017-03-20 2:37 ` Yuantian Tang
(?)
(?)
@ 2017-04-05 6:16 ` Andy Tang
-1 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-04-05 6:16 UTC (permalink / raw)
To: mturquette, sboyd
Cc: robh+dt, mark.rutland, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, Scott Wood
Hello Stephen and Michael,
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette@baylibre.com
> Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood
> <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the platform PLL,
> with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-04-05 6:16 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-04-05 6:16 UTC (permalink / raw)
To: mturquette, sboyd
Cc: robh+dt, mark.rutland, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, Scott Wood
Hello Stephen and Michael,
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette@baylibre.com
> Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood
> <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the platform PLL,
> with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-04-05 6:16 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-04-05 6:16 UTC (permalink / raw)
To: mturquette, sboyd
Cc: robh+dt, mark.rutland, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, Scott Wood
Hello Stephen and Michael,
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette@baylibre.com
> Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood
> <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>=20
> From: Scott Wood <oss@buserror.net>
>=20
> ls1012a has separate input root clocks for core PLLs versus the platform =
PLL,
> with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>=20
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>=20
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>=20
> 2. Clock Provider
>=20
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=3Dpll, 1=3Dpll/2, 2=3Dpll/3, 3=3Dpll/4
> + 5 coreclk must be 0
>=20
> 3. Example
>=20
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-04-05 6:16 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-04-05 6:16 UTC (permalink / raw)
To: linux-arm-kernel
Hello Stephen and Michael,
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang at nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette at baylibre.com
> Cc: sboyd at codeaurora.org; robh+dt at kernel.org; mark.rutland at arm.com;
> linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-
> kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Scott Wood
> <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the platform PLL,
> with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
2017-04-05 6:16 ` Andy Tang
(?)
(?)
@ 2017-04-17 1:37 ` Andy Tang
-1 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-04-17 1:37 UTC (permalink / raw)
To: mturquette, sboyd
Cc: robh+dt, mark.rutland, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, Scott Wood
Hi Stephen and Michael,
This patch set has been pending for more than two months since it was first sent.
I have not received any response from you until now.
Could you give some comments on it?
Regards,
Andy
-----Original Message-----
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturquette@baylibre.com; sboyd@codeaurora.org
Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hello
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette@baylibre.com
> Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott
> Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-04-17 1:37 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-04-17 1:37 UTC (permalink / raw)
To: mturquette, sboyd
Cc: robh+dt, mark.rutland, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, Scott Wood
Hi Stephen and Michael,
This patch set has been pending for more than two months since it was first sent.
I have not received any response from you until now.
Could you give some comments on it?
Regards,
Andy
-----Original Message-----
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturquette@baylibre.com; sboyd@codeaurora.org
Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hello
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette@baylibre.com
> Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott
> Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-04-17 1:37 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-04-17 1:37 UTC (permalink / raw)
To: mturquette, sboyd
Cc: robh+dt, mark.rutland, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, Scott Wood
Hi Stephen and Michael,
This patch set has been pending for more than two months since it was first=
sent.
I have not received any response from you until now.
Could you give some comments on it?
Regards,
Andy
-----Original Message-----
From: Andy Tang=20
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturquette@baylibre.com; sboyd@codeaurora.org
Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; de=
vicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@li=
sts.infradead.org; Scott Wood <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hello=20
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette@baylibre.com
> Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;=20
> linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-=20
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott=20
> Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>=20
> From: Scott Wood <oss@buserror.net>
>=20
> ls1012a has separate input root clocks for core PLLs versus the=20
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named=20
> "coreclk". If present, this clock will be used for the core PLLs.
>=20
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>=20
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>=20
> 2. Clock Provider
>=20
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=3Dpll, 1=3Dpll/2, 2=3Dpll/3, 3=3Dpll/4
> + 5 coreclk must be 0
>=20
> 3. Example
>=20
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-04-17 1:37 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-04-17 1:37 UTC (permalink / raw)
To: linux-arm-kernel
Hi Stephen and Michael,
This patch set has been pending for more than two months since it was first sent.
I have not received any response from you until now.
Could you give some comments on it?
Regards,
Andy
-----Original Message-----
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturquette at baylibre.com; sboyd at codeaurora.org
Cc: robh+dt at kernel.org; mark.rutland at arm.com; linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Scott Wood <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hello
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang at nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette at baylibre.com
> Cc: sboyd at codeaurora.org; robh+dt at kernel.org; mark.rutland at arm.com;
> linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-
> kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Scott
> Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
2017-04-05 6:16 ` Andy Tang
(?)
(?)
@ 2017-04-24 3:14 ` Andy Tang
-1 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-04-24 3:14 UTC (permalink / raw)
To: mturquette, sboyd
Cc: robh+dt, mark.rutland, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, Scott Wood
Does anyone give me a clue why this patch set can't be responded after so long time?
Thanks,
Andy
-----Original Message-----
From: Andy Tang
Sent: Monday, April 17, 2017 9:37 AM
To: 'mturquette@baylibre.com' <mturquette@baylibre.com>; 'sboyd@codeaurora.org' <sboyd@codeaurora.org>
Cc: 'robh+dt@kernel.org' <robh+dt@kernel.org>; 'mark.rutland@arm.com' <mark.rutland@arm.com>; 'linux-clk@vger.kernel.org' <linux-clk@vger.kernel.org>; 'devicetree@vger.kernel.org' <devicetree@vger.kernel.org>; 'linux-kernel@vger.kernel.org' <linux-kernel@vger.kernel.org>; 'linux-arm-kernel@lists.infradead.org' <linux-arm-kernel@lists.infradead.org>; 'Scott Wood' <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hi Stephen and Michael,
This patch set has been pending for more than two months since it was first sent.
I have not received any response from you until now.
Could you give some comments on it?
Regards,
Andy
-----Original Message-----
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturquette@baylibre.com; sboyd@codeaurora.org
Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hello
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette@baylibre.com
> Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott
> Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-04-24 3:14 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-04-24 3:14 UTC (permalink / raw)
To: mturquette, sboyd
Cc: robh+dt, mark.rutland, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, Scott Wood
Does anyone give me a clue why this patch set can't be responded after so long time?
Thanks,
Andy
-----Original Message-----
From: Andy Tang
Sent: Monday, April 17, 2017 9:37 AM
To: 'mturquette@baylibre.com' <mturquette@baylibre.com>; 'sboyd@codeaurora.org' <sboyd@codeaurora.org>
Cc: 'robh+dt@kernel.org' <robh+dt@kernel.org>; 'mark.rutland@arm.com' <mark.rutland@arm.com>; 'linux-clk@vger.kernel.org' <linux-clk@vger.kernel.org>; 'devicetree@vger.kernel.org' <devicetree@vger.kernel.org>; 'linux-kernel@vger.kernel.org' <linux-kernel@vger.kernel.org>; 'linux-arm-kernel@lists.infradead.org' <linux-arm-kernel@lists.infradead.org>; 'Scott Wood' <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hi Stephen and Michael,
This patch set has been pending for more than two months since it was first sent.
I have not received any response from you until now.
Could you give some comments on it?
Regards,
Andy
-----Original Message-----
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturquette@baylibre.com; sboyd@codeaurora.org
Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hello
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette@baylibre.com
> Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott
> Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-04-24 3:14 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-04-24 3:14 UTC (permalink / raw)
To: mturquette, sboyd
Cc: robh+dt, mark.rutland, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, Scott Wood
Does anyone give me a clue why this patch set can't be responded after so l=
ong time?
Thanks,
Andy
-----Original Message-----
From: Andy Tang=20
Sent: Monday, April 17, 2017 9:37 AM
To: 'mturquette@baylibre.com' <mturquette@baylibre.com>; 'sboyd@codeaurora.=
org' <sboyd@codeaurora.org>
Cc: 'robh+dt@kernel.org' <robh+dt@kernel.org>; 'mark.rutland@arm.com' <mark=
.rutland@arm.com>; 'linux-clk@vger.kernel.org' <linux-clk@vger.kernel.org>;=
'devicetree@vger.kernel.org' <devicetree@vger.kernel.org>; 'linux-kernel@v=
ger.kernel.org' <linux-kernel@vger.kernel.org>; 'linux-arm-kernel@lists.inf=
radead.org' <linux-arm-kernel@lists.infradead.org>; 'Scott Wood' <oss@buser=
ror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hi Stephen and Michael,
This patch set has been pending for more than two months since it was first=
sent.
I have not received any response from you until now.
Could you give some comments on it?
Regards,
Andy
-----Original Message-----
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturquette@baylibre.com; sboyd@codeaurora.org
Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; de=
vicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@li=
sts.infradead.org; Scott Wood <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hello=20
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette@baylibre.com
> Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;=20
> linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-=20
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott=20
> Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>=20
> From: Scott Wood <oss@buserror.net>
>=20
> ls1012a has separate input root clocks for core PLLs versus the=20
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named=20
> "coreclk". If present, this clock will be used for the core PLLs.
>=20
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>=20
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>=20
> 2. Clock Provider
>=20
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=3Dpll, 1=3Dpll/2, 2=3Dpll/3, 3=3Dpll/4
> + 5 coreclk must be 0
>=20
> 3. Example
>=20
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-04-24 3:14 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-04-24 3:14 UTC (permalink / raw)
To: linux-arm-kernel
Does anyone give me a clue why this patch set can't be responded after so long time?
Thanks,
Andy
-----Original Message-----
From: Andy Tang
Sent: Monday, April 17, 2017 9:37 AM
To: 'mturquette at baylibre.com' <mturquette@baylibre.com>; 'sboyd at codeaurora.org' <sboyd@codeaurora.org>
Cc: 'robh+dt at kernel.org' <robh+dt@kernel.org>; 'mark.rutland at arm.com' <mark.rutland@arm.com>; 'linux-clk at vger.kernel.org' <linux-clk@vger.kernel.org>; 'devicetree at vger.kernel.org' <devicetree@vger.kernel.org>; 'linux-kernel at vger.kernel.org' <linux-kernel@vger.kernel.org>; 'linux-arm-kernel at lists.infradead.org' <linux-arm-kernel@lists.infradead.org>; 'Scott Wood' <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hi Stephen and Michael,
This patch set has been pending for more than two months since it was first sent.
I have not received any response from you until now.
Could you give some comments on it?
Regards,
Andy
-----Original Message-----
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturquette at baylibre.com; sboyd at codeaurora.org
Cc: robh+dt at kernel.org; mark.rutland at arm.com; linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Scott Wood <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hello
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang at nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette at baylibre.com
> Cc: sboyd at codeaurora.org; robh+dt at kernel.org; mark.rutland at arm.com;
> linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-
> kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Scott
> Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-05-08 5:59 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-05-08 5:59 UTC (permalink / raw)
To: robh+dt
Cc: sboyd, mturquette, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood
Hi Robh,
Could you please take a look at this patch set? They are pending for a really long time.
Don't know why they have not been merged.
Patch links:
https://patchwork.kernel.org/patch/9633007/
https://patchwork.kernel.org/patch/9633009/
Regards,
Andy
> -----Original Message-----
> From: Andy Tang
> Sent: Monday, April 24, 2017 11:15 AM
> To: mturquette@baylibre.com; sboyd@codeaurora.org
> Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; Scott Wood <oss@buserror.net>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> Does anyone give me a clue why this patch set can't be responded after so
> long time?
>
> Thanks,
> Andy
>
> -----Original Message-----
> From: Andy Tang
> Sent: Monday, April 17, 2017 9:37 AM
> To: 'mturquette@baylibre.com' <mturquette@baylibre.com>;
> 'sboyd@codeaurora.org' <sboyd@codeaurora.org>
> Cc: 'robh+dt@kernel.org' <robh+dt@kernel.org>; 'mark.rutland@arm.com'
> <mark.rutland@arm.com>; 'linux-clk@vger.kernel.org' <linux-
> clk@vger.kernel.org>; 'devicetree@vger.kernel.org'
> <devicetree@vger.kernel.org>; 'linux-kernel@vger.kernel.org' <linux-
> kernel@vger.kernel.org>; 'linux-arm-kernel@lists.infradead.org' <linux-arm-
> kernel@lists.infradead.org>; 'Scott Wood' <oss@buserror.net>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> Hi Stephen and Michael,
>
> This patch set has been pending for more than two months since it was first
> sent.
> I have not received any response from you until now.
>
> Could you give some comments on it?
>
> Regards,
> Andy
>
> -----Original Message-----
> From: Andy Tang
> Sent: Wednesday, April 05, 2017 2:16 PM
> To: mturquette@baylibre.com; sboyd@codeaurora.org
> Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; Scott Wood <oss@buserror.net>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> Hello
>
> Do you have any comments on this patch set which was acked by Rob?
>
> Regards,
> Andy
>
> > -----Original Message-----
> > From: Yuantian Tang [mailto:andy.tang@nxp.com]
> > Sent: Monday, March 20, 2017 10:37 AM
> > To: mturquette@baylibre.com
> > Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;
> > linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott
> > Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> > Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> >
> > From: Scott Wood <oss@buserror.net>
> >
> > ls1012a has separate input root clocks for core PLLs versus the
> > platform PLL, with the latter described as sysclk in the hw docs.
> > Update the qoriq-clock binding to allow a second input clock, named
> > "coreclk". If present, this clock will be used for the core PLLs.
> >
> > Signed-off-by: Scott Wood <oss@buserror.net>
> > Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> > Acked-by: Rob Herring <robh@kernel.org>
> > ---
> > v2:
> > -- change the author to Scott
> > Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > index aa3526f..119cafd 100644
> > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > @@ -56,6 +56,11 @@ Optional properties:
> > - clocks: If clock-frequency is not specified, sysclk may be provided
> > as an input clock. Either clock-frequency or clocks must be
> > provided.
> > + A second input clock, called "coreclk", may be provided if
> > + core PLLs are based on a different input clock from the
> > + platform PLL.
> > +- clock-names: Required if a coreclk is present. Valid names are
> > + "sysclk" and "coreclk".
> >
> > 2. Clock Provider
> >
> > @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> > 2 hwaccel index (n in CLKCGnHWACSR)
> > 3 fman 0 for fm1, 1 for fm2
> > 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> > + 5 coreclk must be 0
> >
> > 3. Example
> >
> > --
> > 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-05-08 5:59 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-05-08 5:59 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w,
mark.rutland-5wv7dgnIgG8, linux-clk-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Scott Wood
Hi Robh,
Could you please take a look at this patch set? They are pending for a really long time.
Don't know why they have not been merged.
Patch links:
https://patchwork.kernel.org/patch/9633007/
https://patchwork.kernel.org/patch/9633009/
Regards,
Andy
> -----Original Message-----
> From: Andy Tang
> Sent: Monday, April 24, 2017 11:15 AM
> To: mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org; sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org
> Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org; mark.rutland-5wv7dgnIgG8@public.gmane.org; linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org;
> devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-
> kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> Does anyone give me a clue why this patch set can't be responded after so
> long time?
>
> Thanks,
> Andy
>
> -----Original Message-----
> From: Andy Tang
> Sent: Monday, April 17, 2017 9:37 AM
> To: 'mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org' <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>;
> 'sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org' <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Cc: 'robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org' <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; 'mark.rutland-5wv7dgnIgG8@public.gmane.org'
> <mark.rutland-5wv7dgnIgG8@public.gmane.org>; 'linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org' <linux-
> clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; 'devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org'
> <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; 'linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org' <linux-
> kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; 'linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org' <linux-arm-
> kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>; 'Scott Wood' <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> Hi Stephen and Michael,
>
> This patch set has been pending for more than two months since it was first
> sent.
> I have not received any response from you until now.
>
> Could you give some comments on it?
>
> Regards,
> Andy
>
> -----Original Message-----
> From: Andy Tang
> Sent: Wednesday, April 05, 2017 2:16 PM
> To: mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org; sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org
> Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org; mark.rutland-5wv7dgnIgG8@public.gmane.org; linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org;
> devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-
> kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> Hello
>
> Do you have any comments on this patch set which was acked by Rob?
>
> Regards,
> Andy
>
> > -----Original Message-----
> > From: Yuantian Tang [mailto:andy.tang-3arQi8VN3Tc@public.gmane.org]
> > Sent: Monday, March 20, 2017 10:37 AM
> > To: mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org
> > Cc: sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org; robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org; mark.rutland-5wv7dgnIgG8@public.gmane.org;
> > linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-
> > kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; Scott
> > Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>; Andy Tang <andy.tang-3arQi8VN3Tc@public.gmane.org>
> > Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> >
> > From: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
> >
> > ls1012a has separate input root clocks for core PLLs versus the
> > platform PLL, with the latter described as sysclk in the hw docs.
> > Update the qoriq-clock binding to allow a second input clock, named
> > "coreclk". If present, this clock will be used for the core PLLs.
> >
> > Signed-off-by: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
> > Signed-off-by: Tang Yuantian <andy.tang-3arQi8VN3Tc@public.gmane.org>
> > Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> > ---
> > v2:
> > -- change the author to Scott
> > Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > index aa3526f..119cafd 100644
> > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > @@ -56,6 +56,11 @@ Optional properties:
> > - clocks: If clock-frequency is not specified, sysclk may be provided
> > as an input clock. Either clock-frequency or clocks must be
> > provided.
> > + A second input clock, called "coreclk", may be provided if
> > + core PLLs are based on a different input clock from the
> > + platform PLL.
> > +- clock-names: Required if a coreclk is present. Valid names are
> > + "sysclk" and "coreclk".
> >
> > 2. Clock Provider
> >
> > @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> > 2 hwaccel index (n in CLKCGnHWACSR)
> > 3 fman 0 for fm1, 1 for fm2
> > 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> > + 5 coreclk must be 0
> >
> > 3. Example
> >
> > --
> > 2.1.0.27.g96db324
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-05-08 5:59 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-05-08 5:59 UTC (permalink / raw)
To: robh+dt
Cc: sboyd, mturquette, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood
Hi Robh,
Could you please take a look at this patch set? They are pending for a real=
ly long time.
Don't know why they have not been merged.
Patch links:
https://patchwork.kernel.org/patch/9633007/
https://patchwork.kernel.org/patch/9633009/
Regards,
Andy
> -----Original Message-----
> From: Andy Tang
> Sent: Monday, April 24, 2017 11:15 AM
> To: mturquette@baylibre.com; sboyd@codeaurora.org
> Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; Scott Wood <oss@buserror.net>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>=20
> Does anyone give me a clue why this patch set can't be responded after so
> long time?
>=20
> Thanks,
> Andy
>=20
> -----Original Message-----
> From: Andy Tang
> Sent: Monday, April 17, 2017 9:37 AM
> To: 'mturquette@baylibre.com' <mturquette@baylibre.com>;
> 'sboyd@codeaurora.org' <sboyd@codeaurora.org>
> Cc: 'robh+dt@kernel.org' <robh+dt@kernel.org>; 'mark.rutland@arm.com'
> <mark.rutland@arm.com>; 'linux-clk@vger.kernel.org' <linux-
> clk@vger.kernel.org>; 'devicetree@vger.kernel.org'
> <devicetree@vger.kernel.org>; 'linux-kernel@vger.kernel.org' <linux-
> kernel@vger.kernel.org>; 'linux-arm-kernel@lists.infradead.org' <linux-ar=
m-
> kernel@lists.infradead.org>; 'Scott Wood' <oss@buserror.net>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>=20
> Hi Stephen and Michael,
>=20
> This patch set has been pending for more than two months since it was fir=
st
> sent.
> I have not received any response from you until now.
>=20
> Could you give some comments on it?
>=20
> Regards,
> Andy
>=20
> -----Original Message-----
> From: Andy Tang
> Sent: Wednesday, April 05, 2017 2:16 PM
> To: mturquette@baylibre.com; sboyd@codeaurora.org
> Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; Scott Wood <oss@buserror.net>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>=20
> Hello
>=20
> Do you have any comments on this patch set which was acked by Rob?
>=20
> Regards,
> Andy
>=20
> > -----Original Message-----
> > From: Yuantian Tang [mailto:andy.tang@nxp.com]
> > Sent: Monday, March 20, 2017 10:37 AM
> > To: mturquette@baylibre.com
> > Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;
> > linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott
> > Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> > Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> >
> > From: Scott Wood <oss@buserror.net>
> >
> > ls1012a has separate input root clocks for core PLLs versus the
> > platform PLL, with the latter described as sysclk in the hw docs.
> > Update the qoriq-clock binding to allow a second input clock, named
> > "coreclk". If present, this clock will be used for the core PLLs.
> >
> > Signed-off-by: Scott Wood <oss@buserror.net>
> > Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> > Acked-by: Rob Herring <robh@kernel.org>
> > ---
> > v2:
> > -- change the author to Scott
> > Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > index aa3526f..119cafd 100644
> > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > @@ -56,6 +56,11 @@ Optional properties:
> > - clocks: If clock-frequency is not specified, sysclk may be provided
> > as an input clock. Either clock-frequency or clocks must be
> > provided.
> > + A second input clock, called "coreclk", may be provided if
> > + core PLLs are based on a different input clock from the
> > + platform PLL.
> > +- clock-names: Required if a coreclk is present. Valid names are
> > + "sysclk" and "coreclk".
> >
> > 2. Clock Provider
> >
> > @@ -72,6 +77,7 @@ second cell is the clock index for the specified type=
.
> > 2 hwaccel index (n in CLKCGnHWACSR)
> > 3 fman 0 for fm1, 1 for fm2
> > 4 platform pll 0=3Dpll, 1=3Dpll/2, 2=3Dpll/3, 3=3Dpll/4
> > + 5 coreclk must be 0
> >
> > 3. Example
> >
> > --
> > 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-05-08 5:59 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-05-08 5:59 UTC (permalink / raw)
To: linux-arm-kernel
Hi Robh,
Could you please take a look at this patch set? They are pending for a really long time.
Don't know why they have not been merged.
Patch links:
https://patchwork.kernel.org/patch/9633007/
https://patchwork.kernel.org/patch/9633009/
Regards,
Andy
> -----Original Message-----
> From: Andy Tang
> Sent: Monday, April 24, 2017 11:15 AM
> To: mturquette at baylibre.com; sboyd at codeaurora.org
> Cc: robh+dt at kernel.org; mark.rutland at arm.com; linux-clk at vger.kernel.org;
> devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; Scott Wood <oss@buserror.net>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> Does anyone give me a clue why this patch set can't be responded after so
> long time?
>
> Thanks,
> Andy
>
> -----Original Message-----
> From: Andy Tang
> Sent: Monday, April 17, 2017 9:37 AM
> To: 'mturquette at baylibre.com' <mturquette@baylibre.com>;
> 'sboyd at codeaurora.org' <sboyd@codeaurora.org>
> Cc: 'robh+dt at kernel.org' <robh+dt@kernel.org>; 'mark.rutland at arm.com'
> <mark.rutland@arm.com>; 'linux-clk at vger.kernel.org' <linux-
> clk at vger.kernel.org>; 'devicetree at vger.kernel.org'
> <devicetree@vger.kernel.org>; 'linux-kernel at vger.kernel.org' <linux-
> kernel at vger.kernel.org>; 'linux-arm-kernel at lists.infradead.org' <linux-arm-
> kernel at lists.infradead.org>; 'Scott Wood' <oss@buserror.net>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> Hi Stephen and Michael,
>
> This patch set has been pending for more than two months since it was first
> sent.
> I have not received any response from you until now.
>
> Could you give some comments on it?
>
> Regards,
> Andy
>
> -----Original Message-----
> From: Andy Tang
> Sent: Wednesday, April 05, 2017 2:16 PM
> To: mturquette at baylibre.com; sboyd at codeaurora.org
> Cc: robh+dt at kernel.org; mark.rutland at arm.com; linux-clk at vger.kernel.org;
> devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; Scott Wood <oss@buserror.net>
> Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> Hello
>
> Do you have any comments on this patch set which was acked by Rob?
>
> Regards,
> Andy
>
> > -----Original Message-----
> > From: Yuantian Tang [mailto:andy.tang at nxp.com]
> > Sent: Monday, March 20, 2017 10:37 AM
> > To: mturquette at baylibre.com
> > Cc: sboyd at codeaurora.org; robh+dt at kernel.org; mark.rutland at arm.com;
> > linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-
> > kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Scott
> > Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> > Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
> >
> > From: Scott Wood <oss@buserror.net>
> >
> > ls1012a has separate input root clocks for core PLLs versus the
> > platform PLL, with the latter described as sysclk in the hw docs.
> > Update the qoriq-clock binding to allow a second input clock, named
> > "coreclk". If present, this clock will be used for the core PLLs.
> >
> > Signed-off-by: Scott Wood <oss@buserror.net>
> > Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> > Acked-by: Rob Herring <robh@kernel.org>
> > ---
> > v2:
> > -- change the author to Scott
> > Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > index aa3526f..119cafd 100644
> > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> > @@ -56,6 +56,11 @@ Optional properties:
> > - clocks: If clock-frequency is not specified, sysclk may be provided
> > as an input clock. Either clock-frequency or clocks must be
> > provided.
> > + A second input clock, called "coreclk", may be provided if
> > + core PLLs are based on a different input clock from the
> > + platform PLL.
> > +- clock-names: Required if a coreclk is present. Valid names are
> > + "sysclk" and "coreclk".
> >
> > 2. Clock Provider
> >
> > @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> > 2 hwaccel index (n in CLKCGnHWACSR)
> > 3 fman 0 for fm1, 1 for fm2
> > 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> > + 5 coreclk must be 0
> >
> > 3. Example
> >
> > --
> > 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
2017-04-05 6:16 ` Andy Tang
(?)
(?)
@ 2017-05-31 9:22 ` Andy Tang
-1 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-05-31 9:22 UTC (permalink / raw)
To: mturquette, sboyd
Cc: robh+dt, mark.rutland, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, Scott Wood
Hi Stephen and Michael,
How many times do I need to push those patch get merged?
Regards,
Andy
-----Original Message-----
From: Andy Tang
Sent: Monday, April 17, 2017 9:37 AM
To: 'mturquette@baylibre.com' <mturquette@baylibre.com>; 'sboyd@codeaurora.org' <sboyd@codeaurora.org>
Cc: 'robh+dt@kernel.org' <robh+dt@kernel.org>; 'mark.rutland@arm.com' <mark.rutland@arm.com>; 'linux-clk@vger.kernel.org' <linux-clk@vger.kernel.org>; 'devicetree@vger.kernel.org' <devicetree@vger.kernel.org>; 'linux-kernel@vger.kernel.org' <linux-kernel@vger.kernel.org>; 'linux-arm-kernel@lists.infradead.org' <linux-arm-kernel@lists.infradead.org>; 'Scott Wood' <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hi Stephen and Michael,
This patch set has been pending for more than two months since it was first sent.
I have not received any response from you until now.
Could you give some comments on it?
Regards,
Andy
-----Original Message-----
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturquette@baylibre.com; sboyd@codeaurora.org
Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hello
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette@baylibre.com
> Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott
> Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-05-31 9:22 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-05-31 9:22 UTC (permalink / raw)
To: mturquette, sboyd
Cc: robh+dt, mark.rutland, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, Scott Wood
Hi Stephen and Michael,
How many times do I need to push those patch get merged?
Regards,
Andy
-----Original Message-----
From: Andy Tang
Sent: Monday, April 17, 2017 9:37 AM
To: 'mturquette@baylibre.com' <mturquette@baylibre.com>; 'sboyd@codeaurora.org' <sboyd@codeaurora.org>
Cc: 'robh+dt@kernel.org' <robh+dt@kernel.org>; 'mark.rutland@arm.com' <mark.rutland@arm.com>; 'linux-clk@vger.kernel.org' <linux-clk@vger.kernel.org>; 'devicetree@vger.kernel.org' <devicetree@vger.kernel.org>; 'linux-kernel@vger.kernel.org' <linux-kernel@vger.kernel.org>; 'linux-arm-kernel@lists.infradead.org' <linux-arm-kernel@lists.infradead.org>; 'Scott Wood' <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hi Stephen and Michael,
This patch set has been pending for more than two months since it was first sent.
I have not received any response from you until now.
Could you give some comments on it?
Regards,
Andy
-----Original Message-----
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturquette@baylibre.com; sboyd@codeaurora.org
Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hello
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette@baylibre.com
> Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott
> Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-05-31 9:22 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-05-31 9:22 UTC (permalink / raw)
To: mturquette, sboyd
Cc: robh+dt, mark.rutland, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, Scott Wood
Hi Stephen and Michael,
How many times do I need to push those patch get merged?
Regards,
Andy
-----Original Message-----
From: Andy Tang=20
Sent: Monday, April 17, 2017 9:37 AM
To: 'mturquette@baylibre.com' <mturquette@baylibre.com>; 'sboyd@codeaurora.=
org' <sboyd@codeaurora.org>
Cc: 'robh+dt@kernel.org' <robh+dt@kernel.org>; 'mark.rutland@arm.com' <mark=
.rutland@arm.com>; 'linux-clk@vger.kernel.org' <linux-clk@vger.kernel.org>;=
'devicetree@vger.kernel.org' <devicetree@vger.kernel.org>; 'linux-kernel@v=
ger.kernel.org' <linux-kernel@vger.kernel.org>; 'linux-arm-kernel@lists.inf=
radead.org' <linux-arm-kernel@lists.infradead.org>; 'Scott Wood' <oss@buser=
ror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hi Stephen and Michael,
This patch set has been pending for more than two months since it was first=
sent.
I have not received any response from you until now.
Could you give some comments on it?
Regards,
Andy
-----Original Message-----
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturquette@baylibre.com; sboyd@codeaurora.org
Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; de=
vicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@li=
sts.infradead.org; Scott Wood <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hello=20
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang@nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette@baylibre.com
> Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;=20
> linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-=20
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott=20
> Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>=20
> From: Scott Wood <oss@buserror.net>
>=20
> ls1012a has separate input root clocks for core PLLs versus the=20
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named=20
> "coreclk". If present, this clock will be used for the core PLLs.
>=20
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>=20
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>=20
> 2. Clock Provider
>=20
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=3Dpll, 1=3Dpll/2, 2=3Dpll/3, 3=3Dpll/4
> + 5 coreclk must be 0
>=20
> 3. Example
>=20
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-05-31 9:22 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-05-31 9:22 UTC (permalink / raw)
To: linux-arm-kernel
Hi Stephen and Michael,
How many times do I need to push those patch get merged?
Regards,
Andy
-----Original Message-----
From: Andy Tang
Sent: Monday, April 17, 2017 9:37 AM
To: 'mturquette at baylibre.com' <mturquette@baylibre.com>; 'sboyd at codeaurora.org' <sboyd@codeaurora.org>
Cc: 'robh+dt at kernel.org' <robh+dt@kernel.org>; 'mark.rutland at arm.com' <mark.rutland@arm.com>; 'linux-clk at vger.kernel.org' <linux-clk@vger.kernel.org>; 'devicetree at vger.kernel.org' <devicetree@vger.kernel.org>; 'linux-kernel at vger.kernel.org' <linux-kernel@vger.kernel.org>; 'linux-arm-kernel at lists.infradead.org' <linux-arm-kernel@lists.infradead.org>; 'Scott Wood' <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hi Stephen and Michael,
This patch set has been pending for more than two months since it was first sent.
I have not received any response from you until now.
Could you give some comments on it?
Regards,
Andy
-----Original Message-----
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturquette at baylibre.com; sboyd at codeaurora.org
Cc: robh+dt at kernel.org; mark.rutland at arm.com; linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Scott Wood <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hello
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang at nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette at baylibre.com
> Cc: sboyd at codeaurora.org; robh+dt at kernel.org; mark.rutland at arm.com;
> linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-
> kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Scott
> Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
2017-03-20 2:37 ` Yuantian Tang
@ 2017-06-01 8:27 ` Stephen Boyd
-1 siblings, 0 replies; 45+ messages in thread
From: Stephen Boyd @ 2017-06-01 8:27 UTC (permalink / raw)
To: Yuantian Tang
Cc: mturquette, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood
On 03/20, Yuantian Tang wrote:
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the platform
> PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-06-01 8:27 ` Stephen Boyd
0 siblings, 0 replies; 45+ messages in thread
From: Stephen Boyd @ 2017-06-01 8:27 UTC (permalink / raw)
To: linux-arm-kernel
On 03/20, Yuantian Tang wrote:
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the platform
> PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
2017-04-17 1:37 ` Andy Tang
(?)
@ 2017-06-01 8:27 ` sboyd
-1 siblings, 0 replies; 45+ messages in thread
From: sboyd @ 2017-06-01 8:27 UTC (permalink / raw)
To: Andy Tang
Cc: mturquette, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood
On 04/17, Andy Tang wrote:
> Hi Stephen and Michael,
>
> This patch set has been pending for more than two months since it was first sent.
> I have not received any response from you until now.
>
> Could you give some comments on it?
>
Hmm I think it was sent near the merge window so I put it in the
review queue. Looks ok so let's apply it.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-06-01 8:27 ` sboyd
0 siblings, 0 replies; 45+ messages in thread
From: sboyd @ 2017-06-01 8:27 UTC (permalink / raw)
To: Andy Tang
Cc: mturquette, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood
On 04/17, Andy Tang wrote:
> Hi Stephen and Michael,
>
> This patch set has been pending for more than two months since it was first sent.
> I have not received any response from you until now.
>
> Could you give some comments on it?
>
Hmm I think it was sent near the merge window so I put it in the
review queue. Looks ok so let's apply it.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
@ 2017-06-01 8:27 ` sboyd
0 siblings, 0 replies; 45+ messages in thread
From: sboyd at codeaurora.org @ 2017-06-01 8:27 UTC (permalink / raw)
To: linux-arm-kernel
On 04/17, Andy Tang wrote:
> Hi Stephen and Michael,
>
> This patch set has been pending for more than two months since it was first sent.
> I have not received any response from you until now.
>
> Could you give some comments on it?
>
Hmm I think it was sent near the merge window so I put it in the
review queue. Looks ok so let's apply it.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
2017-03-20 2:37 ` Yuantian Tang
@ 2017-06-01 8:28 ` Stephen Boyd
-1 siblings, 0 replies; 45+ messages in thread
From: Stephen Boyd @ 2017-06-01 8:28 UTC (permalink / raw)
To: Yuantian Tang
Cc: mturquette, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood
On 03/20, Yuantian Tang wrote:
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will be
> used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
@ 2017-06-01 8:28 ` Stephen Boyd
0 siblings, 0 replies; 45+ messages in thread
From: Stephen Boyd @ 2017-06-01 8:28 UTC (permalink / raw)
To: linux-arm-kernel
On 03/20, Yuantian Tang wrote:
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will be
> used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
2017-06-01 8:28 ` Stephen Boyd
(?)
(?)
@ 2017-06-01 8:34 ` Andy Tang
-1 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-06-01 8:34 UTC (permalink / raw)
To: Stephen Boyd
Cc: mturquette, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood
Hi Stephen,
Thanks for your applying.
There are other two patches sent on April 6, 2017:
https://patchwork.kernel.org/patch/9665973/
https://patchwork.kernel.org/patch/9665977/
Hope they are in your review queue. Please give it a review.
Regards,
Andy
-----Original Message-----
From: Stephen Boyd [mailto:sboyd@codeaurora.org]
Sent: Thursday, June 01, 2017 4:28 PM
To: Andy Tang <andy.tang@nxp.com>
Cc: mturquette@baylibre.com; robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood <oss@buserror.net>
Subject: Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
On 03/20, Yuantian Tang wrote:
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will
> be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
@ 2017-06-01 8:34 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-06-01 8:34 UTC (permalink / raw)
To: Stephen Boyd
Cc: mturquette, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood
Hi Stephen,
Thanks for your applying.
There are other two patches sent on April 6, 2017:
https://patchwork.kernel.org/patch/9665973/
https://patchwork.kernel.org/patch/9665977/
Hope they are in your review queue. Please give it a review.
Regards,
Andy
-----Original Message-----
From: Stephen Boyd [mailto:sboyd@codeaurora.org]
Sent: Thursday, June 01, 2017 4:28 PM
To: Andy Tang <andy.tang@nxp.com>
Cc: mturquette@baylibre.com; robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood <oss@buserror.net>
Subject: Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
On 03/20, Yuantian Tang wrote:
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will
> be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 45+ messages in thread
* RE: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
@ 2017-06-01 8:34 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-06-01 8:34 UTC (permalink / raw)
To: Stephen Boyd
Cc: mturquette, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood
Hi Stephen,
Thanks for your applying.
There are other two patches sent on April 6, 2017:
https://patchwork.kernel.org/patch/9665973/
https://patchwork.kernel.org/patch/9665977/
Hope they are in your review queue. Please give it a review.
Regards,
Andy
-----Original Message-----
From: Stephen Boyd [mailto:sboyd@codeaurora.org]=20
Sent: Thursday, June 01, 2017 4:28 PM
To: Andy Tang <andy.tang@nxp.com>
Cc: mturquette@baylibre.com; robh+dt@kernel.org; mark.rutland@arm.com; linu=
x-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel=
.org; linux-arm-kernel@lists.infradead.org; Scott Wood <oss@buserror.net>
Subject: Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core =
PLLs on ls1012a
On 03/20, Yuantian Tang wrote:
> From: Scott Wood <oss@buserror.net>
>=20
> ls1012a has separate input root clocks for core PLLs versus the=20
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will=20
> be used for the core PLLs.
>=20
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux =
Foundation Collaborative Project
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
@ 2017-06-01 8:34 ` Andy Tang
0 siblings, 0 replies; 45+ messages in thread
From: Andy Tang @ 2017-06-01 8:34 UTC (permalink / raw)
To: linux-arm-kernel
Hi Stephen,
Thanks for your applying.
There are other two patches sent on April 6, 2017:
https://patchwork.kernel.org/patch/9665973/
https://patchwork.kernel.org/patch/9665977/
Hope they are in your review queue. Please give it a review.
Regards,
Andy
-----Original Message-----
From: Stephen Boyd [mailto:sboyd at codeaurora.org]
Sent: Thursday, June 01, 2017 4:28 PM
To: Andy Tang <andy.tang@nxp.com>
Cc: mturquette at baylibre.com; robh+dt at kernel.org; mark.rutland at arm.com; linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Scott Wood <oss@buserror.net>
Subject: Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
On 03/20, Yuantian Tang wrote:
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will
> be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
@ 2017-06-01 18:17 ` Stephen Boyd
0 siblings, 0 replies; 45+ messages in thread
From: Stephen Boyd @ 2017-06-01 18:17 UTC (permalink / raw)
To: Andy Tang
Cc: mturquette, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood
On 06/01, Andy Tang wrote:
> Hi Stephen,
>
> Thanks for your applying.
>
> There are other two patches sent on April 6, 2017:
> https://patchwork.kernel.org/patch/9665973/
> https://patchwork.kernel.org/patch/9665977/
>
> Hope they are in your review queue. Please give it a review.
>
Yep they're there. I need to go update patchwork so the queue can
be known outside my local inbox.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
@ 2017-06-01 18:17 ` Stephen Boyd
0 siblings, 0 replies; 45+ messages in thread
From: Stephen Boyd @ 2017-06-01 18:17 UTC (permalink / raw)
To: Andy Tang
Cc: mturquette-rdvid1DuHRBWk0Htik3J/w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Scott Wood
On 06/01, Andy Tang wrote:
> Hi Stephen,
>
> Thanks for your applying.
>
> There are other two patches sent on April 6, 2017:
> https://patchwork.kernel.org/patch/9665973/
> https://patchwork.kernel.org/patch/9665977/
>
> Hope they are in your review queue. Please give it a review.
>
Yep they're there. I need to go update patchwork so the queue can
be known outside my local inbox.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
@ 2017-06-01 18:17 ` Stephen Boyd
0 siblings, 0 replies; 45+ messages in thread
From: Stephen Boyd @ 2017-06-01 18:17 UTC (permalink / raw)
To: Andy Tang
Cc: mturquette, robh+dt, mark.rutland, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, Scott Wood
On 06/01, Andy Tang wrote:
> Hi Stephen,
>
> Thanks for your applying.
>
> There are other two patches sent on April 6, 2017:
> https://patchwork.kernel.org/patch/9665973/
> https://patchwork.kernel.org/patch/9665977/
>
> Hope they are in your review queue. Please give it a review.
>
Yep they're there. I need to go update patchwork so the queue can
be known outside my local inbox.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
@ 2017-06-01 18:17 ` Stephen Boyd
0 siblings, 0 replies; 45+ messages in thread
From: Stephen Boyd @ 2017-06-01 18:17 UTC (permalink / raw)
To: linux-arm-kernel
On 06/01, Andy Tang wrote:
> Hi Stephen,
>
> Thanks for your applying.
>
> There are other two patches sent on April 6, 2017:
> https://patchwork.kernel.org/patch/9665973/
> https://patchwork.kernel.org/patch/9665977/
>
> Hope they are in your review queue. Please give it a review.
>
Yep they're there. I need to go update patchwork so the queue can
be known outside my local inbox.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 45+ messages in thread
end of thread, other threads:[~2017-06-01 18:17 UTC | newest]
Thread overview: 45+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-20 2:37 [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Yuantian Tang
2017-03-20 2:37 ` Yuantian Tang
2017-03-20 2:37 ` Yuantian Tang
2017-03-20 2:37 ` [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a Yuantian Tang
2017-03-20 2:37 ` Yuantian Tang
2017-03-20 2:37 ` Yuantian Tang
2017-06-01 8:28 ` Stephen Boyd
2017-06-01 8:28 ` Stephen Boyd
2017-06-01 8:34 ` Andy Tang
2017-06-01 8:34 ` Andy Tang
2017-06-01 8:34 ` Andy Tang
2017-06-01 8:34 ` Andy Tang
2017-06-01 18:17 ` Stephen Boyd
2017-06-01 18:17 ` Stephen Boyd
2017-06-01 18:17 ` Stephen Boyd
2017-06-01 18:17 ` Stephen Boyd
2017-03-27 3:39 ` [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Andy Tang
2017-03-27 3:39 ` Andy Tang
2017-03-27 3:39 ` Andy Tang
2017-03-27 3:39 ` Andy Tang
2017-04-05 6:16 ` Andy Tang
2017-04-05 6:16 ` Andy Tang
2017-04-05 6:16 ` Andy Tang
2017-04-05 6:16 ` Andy Tang
2017-04-17 1:37 ` Andy Tang
2017-04-17 1:37 ` Andy Tang
2017-04-17 1:37 ` Andy Tang
2017-04-17 1:37 ` Andy Tang
2017-06-01 8:27 ` sboyd
2017-06-01 8:27 ` sboyd at codeaurora.org
2017-06-01 8:27 ` sboyd
2017-04-24 3:14 ` Andy Tang
2017-04-24 3:14 ` Andy Tang
2017-04-24 3:14 ` Andy Tang
2017-04-24 3:14 ` Andy Tang
2017-05-08 5:59 ` Andy Tang
2017-05-08 5:59 ` Andy Tang
2017-05-08 5:59 ` Andy Tang
2017-05-08 5:59 ` Andy Tang
2017-05-31 9:22 ` Andy Tang
2017-05-31 9:22 ` Andy Tang
2017-05-31 9:22 ` Andy Tang
2017-05-31 9:22 ` Andy Tang
2017-06-01 8:27 ` Stephen Boyd
2017-06-01 8:27 ` Stephen Boyd
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