From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1164444AbdDXDPB (ORCPT ); Sun, 23 Apr 2017 23:15:01 -0400 Received: from mail-he1eur01on0054.outbound.protection.outlook.com ([104.47.0.54]:61664 "EHLO EUR01-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1164413AbdDXDOs (ORCPT ); Sun, 23 Apr 2017 23:14:48 -0400 From: Andy Tang To: "mturquette@baylibre.com" , "sboyd@codeaurora.org" CC: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "linux-clk@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Scott Wood Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Thread-Topic: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Thread-Index: AQHSoSTp2gg4DGwNNU+ig6s4pz9lHqG2ZS5QgBKOKjCACxuuIA== Date: Mon, 24 Apr 2017 03:14:44 +0000 Message-ID: References: <1489977443-33582-1-git-send-email-andy.tang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: baylibre.com; dkim=none (message not signed) header.d=none;baylibre.com; dmarc=none action=none header.from=nxp.com; x-originating-ip: [192.158.241.86] x-microsoft-exchange-diagnostics: 1;DB6PR0402MB2838;7:1wPtH3/gAJSdRdbyAtCYOzCTZe8Q+RR2Wok4jjcKfNrCEyz+fkXffmhlM8T6bumMGgL3dkyMumgf3DSMElyKJe4rMZqcXy7Fv3vdytcnuxf9IXrF0bP6G5vlKDQmG+vHjBVK6NrizhzqqdiXTfxSsiFNTGuLfx0cmCx9Ep8gpiaiMxhhjsXB2/marZsPzZ7hHhTGEOBtqFToUlKIdlR13/Ux1wn1iB3ll1YebxBMnOWbxx3h140aRBjc9swVlOboLDe9X9LC8ScawCi0BYYVmmwgnCjWxjjJYqwTVVlG67+9kx90y/yRMzJ5lB70UG3hZslRiUaRTFIMacNLo+HYJg== x-ms-office365-filtering-correlation-id: 40088fe6-e49b-4789-d8f1-08d48ac00e6a x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081);SRVR:DB6PR0402MB2838; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917)(9452136761055)(185117386973197)(258649278758335); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040450)(601004)(2401047)(5005006)(8121501046)(93006095)(93001095)(3002001)(10201501046)(6055026)(6041248)(20161123564025)(201703131423075)(201702281528075)(201703061421075)(20161123560025)(20161123562025)(20161123555025)(6072148);SRVR:DB6PR0402MB2838;BCL:0;PCL:0;RULEID:;SRVR:DB6PR0402MB2838; x-forefront-prvs: 0287BBA78D x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(39450400003)(39840400002)(39860400002)(39400400002)(39410400002)(39850400002)(377454003)(13464003)(229853002)(25786009)(53546009)(33656002)(2501003)(50986999)(5660300001)(76176999)(54356999)(4326008)(122556002)(7736002)(305945005)(74316002)(86362001)(6116002)(53936002)(8936002)(54906002)(38730400002)(99286003)(9686003)(6246003)(55016002)(7696004)(189998001)(6436002)(81166006)(8676002)(77096006)(3846002)(2900100001)(2906002)(3660700001)(3280700002)(102836003)(66066001)(6506006);DIR:OUT;SFP:1101;SCL:1;SRVR:DB6PR0402MB2838;H:DB6PR0402MB2837.eurprd04.prod.outlook.com;FPR:;SPF:None;MLV:sfv;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Apr 2017 03:14:44.5649 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0402MB2838 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v3O3FB4J025428 Does anyone give me a clue why this patch set can't be responded after so long time? Thanks, Andy -----Original Message----- From: Andy Tang Sent: Monday, April 17, 2017 9:37 AM To: 'mturquette@baylibre.com' ; 'sboyd@codeaurora.org' Cc: 'robh+dt@kernel.org' ; 'mark.rutland@arm.com' ; 'linux-clk@vger.kernel.org' ; 'devicetree@vger.kernel.org' ; 'linux-kernel@vger.kernel.org' ; 'linux-arm-kernel@lists.infradead.org' ; 'Scott Wood' Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Hi Stephen and Michael, This patch set has been pending for more than two months since it was first sent. I have not received any response from you until now. Could you give some comments on it? Regards, Andy -----Original Message----- From: Andy Tang Sent: Wednesday, April 05, 2017 2:16 PM To: mturquette@baylibre.com; sboyd@codeaurora.org Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Hello Do you have any comments on this patch set which was acked by Rob? Regards, Andy > -----Original Message----- > From: Yuantian Tang [mailto:andy.tang@nxp.com] > Sent: Monday, March 20, 2017 10:37 AM > To: mturquette@baylibre.com > Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com; > linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott > Wood ; Andy Tang > Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk > > From: Scott Wood > > ls1012a has separate input root clocks for core PLLs versus the > platform PLL, with the latter described as sysclk in the hw docs. > Update the qoriq-clock binding to allow a second input clock, named > "coreclk". If present, this clock will be used for the core PLLs. > > Signed-off-by: Scott Wood > Signed-off-by: Tang Yuantian > Acked-by: Rob Herring > --- > v2: > -- change the author to Scott > Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > index aa3526f..119cafd 100644 > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > @@ -56,6 +56,11 @@ Optional properties: > - clocks: If clock-frequency is not specified, sysclk may be provided > as an input clock. Either clock-frequency or clocks must be > provided. > + A second input clock, called "coreclk", may be provided if > + core PLLs are based on a different input clock from the > + platform PLL. > +- clock-names: Required if a coreclk is present. Valid names are > + "sysclk" and "coreclk". > > 2. Clock Provider > > @@ -72,6 +77,7 @@ second cell is the clock index for the specified type. > 2 hwaccel index (n in CLKCGnHWACSR) > 3 fman 0 for fm1, 1 for fm2 > 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4 > + 5 coreclk must be 0 > > 3. Example > > -- > 2.1.0.27.g96db324 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Tang Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Date: Mon, 24 Apr 2017 03:14:44 +0000 Message-ID: References: <1489977443-33582-1-git-send-email-andy.tang@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Return-path: Content-Language: en-US Sender: linux-clk-owner@vger.kernel.org To: "mturquette@baylibre.com" , "sboyd@codeaurora.org" Cc: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "linux-clk@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Scott Wood List-Id: devicetree@vger.kernel.org Does anyone give me a clue why this patch set can't be responded after so l= ong time? Thanks, Andy -----Original Message----- From: Andy Tang=20 Sent: Monday, April 17, 2017 9:37 AM To: 'mturquette@baylibre.com' ; 'sboyd@codeaurora.= org' Cc: 'robh+dt@kernel.org' ; 'mark.rutland@arm.com' ; 'linux-clk@vger.kernel.org' ;= 'devicetree@vger.kernel.org' ; 'linux-kernel@v= ger.kernel.org' ; 'linux-arm-kernel@lists.inf= radead.org' ; 'Scott Wood' Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Hi Stephen and Michael, This patch set has been pending for more than two months since it was first= sent. I have not received any response from you until now. Could you give some comments on it? Regards, Andy -----Original Message----- From: Andy Tang Sent: Wednesday, April 05, 2017 2:16 PM To: mturquette@baylibre.com; sboyd@codeaurora.org Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; de= vicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@li= sts.infradead.org; Scott Wood Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Hello=20 Do you have any comments on this patch set which was acked by Rob? Regards, Andy > -----Original Message----- > From: Yuantian Tang [mailto:andy.tang@nxp.com] > Sent: Monday, March 20, 2017 10:37 AM > To: mturquette@baylibre.com > Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;=20 > linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-=20 > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott=20 > Wood ; Andy Tang > Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk >=20 > From: Scott Wood >=20 > ls1012a has separate input root clocks for core PLLs versus the=20 > platform PLL, with the latter described as sysclk in the hw docs. > Update the qoriq-clock binding to allow a second input clock, named=20 > "coreclk". If present, this clock will be used for the core PLLs. >=20 > Signed-off-by: Scott Wood > Signed-off-by: Tang Yuantian > Acked-by: Rob Herring > --- > v2: > -- change the author to Scott > Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++ > 1 file changed, 6 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > index aa3526f..119cafd 100644 > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > @@ -56,6 +56,11 @@ Optional properties: > - clocks: If clock-frequency is not specified, sysclk may be provided > as an input clock. Either clock-frequency or clocks must be > provided. > + A second input clock, called "coreclk", may be provided if > + core PLLs are based on a different input clock from the > + platform PLL. > +- clock-names: Required if a coreclk is present. Valid names are > + "sysclk" and "coreclk". >=20 > 2. Clock Provider >=20 > @@ -72,6 +77,7 @@ second cell is the clock index for the specified type. > 2 hwaccel index (n in CLKCGnHWACSR) > 3 fman 0 for fm1, 1 for fm2 > 4 platform pll 0=3Dpll, 1=3Dpll/2, 2=3Dpll/3, 3=3Dpll/4 > + 5 coreclk must be 0 >=20 > 3. Example >=20 > -- > 2.1.0.27.g96db324 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Andy Tang To: "mturquette@baylibre.com" , "sboyd@codeaurora.org" CC: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "linux-clk@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Scott Wood Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Date: Mon, 24 Apr 2017 03:14:44 +0000 Message-ID: References: <1489977443-33582-1-git-send-email-andy.tang@nxp.com> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 List-ID: Does anyone give me a clue why this patch set can't be responded after so l= ong time? Thanks, Andy -----Original Message----- From: Andy Tang=20 Sent: Monday, April 17, 2017 9:37 AM To: 'mturquette@baylibre.com' ; 'sboyd@codeaurora.= org' Cc: 'robh+dt@kernel.org' ; 'mark.rutland@arm.com' ; 'linux-clk@vger.kernel.org' ;= 'devicetree@vger.kernel.org' ; 'linux-kernel@v= ger.kernel.org' ; 'linux-arm-kernel@lists.inf= radead.org' ; 'Scott Wood' Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Hi Stephen and Michael, This patch set has been pending for more than two months since it was first= sent. I have not received any response from you until now. Could you give some comments on it? Regards, Andy -----Original Message----- From: Andy Tang Sent: Wednesday, April 05, 2017 2:16 PM To: mturquette@baylibre.com; sboyd@codeaurora.org Cc: robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; de= vicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@li= sts.infradead.org; Scott Wood Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Hello=20 Do you have any comments on this patch set which was acked by Rob? Regards, Andy > -----Original Message----- > From: Yuantian Tang [mailto:andy.tang@nxp.com] > Sent: Monday, March 20, 2017 10:37 AM > To: mturquette@baylibre.com > Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com;=20 > linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-=20 > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott=20 > Wood ; Andy Tang > Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk >=20 > From: Scott Wood >=20 > ls1012a has separate input root clocks for core PLLs versus the=20 > platform PLL, with the latter described as sysclk in the hw docs. > Update the qoriq-clock binding to allow a second input clock, named=20 > "coreclk". If present, this clock will be used for the core PLLs. >=20 > Signed-off-by: Scott Wood > Signed-off-by: Tang Yuantian > Acked-by: Rob Herring > --- > v2: > -- change the author to Scott > Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++ > 1 file changed, 6 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > index aa3526f..119cafd 100644 > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > @@ -56,6 +56,11 @@ Optional properties: > - clocks: If clock-frequency is not specified, sysclk may be provided > as an input clock. Either clock-frequency or clocks must be > provided. > + A second input clock, called "coreclk", may be provided if > + core PLLs are based on a different input clock from the > + platform PLL. > +- clock-names: Required if a coreclk is present. Valid names are > + "sysclk" and "coreclk". >=20 > 2. Clock Provider >=20 > @@ -72,6 +77,7 @@ second cell is the clock index for the specified type. > 2 hwaccel index (n in CLKCGnHWACSR) > 3 fman 0 for fm1, 1 for fm2 > 4 platform pll 0=3Dpll, 1=3Dpll/2, 2=3Dpll/3, 3=3Dpll/4 > + 5 coreclk must be 0 >=20 > 3. Example >=20 > -- > 2.1.0.27.g96db324 From mboxrd@z Thu Jan 1 00:00:00 1970 From: andy.tang@nxp.com (Andy Tang) Date: Mon, 24 Apr 2017 03:14:44 +0000 Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk References: <1489977443-33582-1-git-send-email-andy.tang@nxp.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Does anyone give me a clue why this patch set can't be responded after so long time? Thanks, Andy -----Original Message----- From: Andy Tang Sent: Monday, April 17, 2017 9:37 AM To: 'mturquette at baylibre.com' ; 'sboyd at codeaurora.org' Cc: 'robh+dt at kernel.org' ; 'mark.rutland at arm.com' ; 'linux-clk at vger.kernel.org' ; 'devicetree at vger.kernel.org' ; 'linux-kernel at vger.kernel.org' ; 'linux-arm-kernel at lists.infradead.org' ; 'Scott Wood' Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Hi Stephen and Michael, This patch set has been pending for more than two months since it was first sent. I have not received any response from you until now. Could you give some comments on it? Regards, Andy -----Original Message----- From: Andy Tang Sent: Wednesday, April 05, 2017 2:16 PM To: mturquette at baylibre.com; sboyd at codeaurora.org Cc: robh+dt at kernel.org; mark.rutland at arm.com; linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Scott Wood Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Hello Do you have any comments on this patch set which was acked by Rob? Regards, Andy > -----Original Message----- > From: Yuantian Tang [mailto:andy.tang at nxp.com] > Sent: Monday, March 20, 2017 10:37 AM > To: mturquette at baylibre.com > Cc: sboyd at codeaurora.org; robh+dt at kernel.org; mark.rutland at arm.com; > linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux- > kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Scott > Wood ; Andy Tang > Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk > > From: Scott Wood > > ls1012a has separate input root clocks for core PLLs versus the > platform PLL, with the latter described as sysclk in the hw docs. > Update the qoriq-clock binding to allow a second input clock, named > "coreclk". If present, this clock will be used for the core PLLs. > > Signed-off-by: Scott Wood > Signed-off-by: Tang Yuantian > Acked-by: Rob Herring > --- > v2: > -- change the author to Scott > Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > index aa3526f..119cafd 100644 > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > @@ -56,6 +56,11 @@ Optional properties: > - clocks: If clock-frequency is not specified, sysclk may be provided > as an input clock. Either clock-frequency or clocks must be > provided. > + A second input clock, called "coreclk", may be provided if > + core PLLs are based on a different input clock from the > + platform PLL. > +- clock-names: Required if a coreclk is present. Valid names are > + "sysclk" and "coreclk". > > 2. Clock Provider > > @@ -72,6 +77,7 @@ second cell is the clock index for the specified type. > 2 hwaccel index (n in CLKCGnHWACSR) > 3 fman 0 for fm1, 1 for fm2 > 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4 > + 5 coreclk must be 0 > > 3. Example > > -- > 2.1.0.27.g96db324