From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ruchika Gupta <ruchika.gupta@nxp.com>
Date: Mon, 3 Apr 2017 07:00:10 +0000
Subject: [U-Boot] [PATCH 3/3][v3] [RESEND] arm: ls1046ardb: Add SD
 secure boot target
In-Reply-To: <VI1PR0401MB268788E3897364508604756D9A370@VI1PR0401MB2687.eurprd04.prod.outlook.com>
References: <1490815584-30551-1-git-send-email-ruchika.gupta@nxp.com>
 <VI1PR0401MB268788E3897364508604756D9A370@VI1PR0401MB2687.eurprd04.prod.outlook.com>
Message-ID: <DB6PR04MB2951FCEDCB5359A23CFED026E5080@DB6PR04MB2951.eurprd04.prod.outlook.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de



> -----Original Message-----
> From: york sun
> Sent: Saturday, April 01, 2017 1:44 AM
> To: Ruchika Gupta <ruchika.gupta@nxp.com>; u-boot at lists.denx.de
> Cc: Vini Pillai <vinitha.pillai@nxp.com>; Sumit Garg <sumit.garg@nxp.com>
> Subject: Re: [PATCH 3/3][v3] [RESEND] arm: ls1046ardb: Add SD secure boot
> target
> 
> On 03/29/2017 07:21 AM, Ruchika Gupta wrote:
> > From: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
> >
> > - Add SD secure boot target for ls1046ardb.
> > - Implement board specific spl_board_init() to setup CAAM stream ID and
> >   corresponding stream ID in SMMU.
> > - Change the u-boot size defined by a macro for copying the main U-Boot
> by SPL
> >   to also include the u-boot Secure Boot header size as header is appended
> to
> >   u-boot image. So header will also be copied from SD to DDR.
> > - CONFIG_MAX_SPL_SIZE is limited to 90K.SPL is copied to OCRAM (128K)
> where 32K
> >   are reserved for use by boot ROM and 6K for the header
> > - Reduce the size of CAAM driver for SPL. Since the size of spl image
> >   was about 94K, Blobification functions and descriptors, that are not
> required
> >   at the time of SPL are disabled. Further error code conversion to strings
> >   is disabled for SPL build. This reduces the spl image size to 92K.
> >
> > Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
> > Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
> > Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
> > ---
> > Changes from v1:
> > - Rebased patches to latest dependent patch set
> > - With the dependent path set , spl imag size increased to 94K. So
> > - additionally  reduce the spl image size by removing the functions
> > from
> > - CAAM driver that are not required in SPL flow
> >
> 
> <snip>
> 
> > +#if defined(CONFIG_SPL_BUILD)
> > +void spl_board_init(void)
> > +{
> > +#ifdef CONFIG_SECURE_BOOT
> > +	/*
> > +	 * In case of Secure Boot, the IBR configures the SMMU
> > +	 * to allow only Secure transactions.
> > +	 * SMMU must be reset in bypass mode.
> > +	 * Set the ClientPD bit and Clear the USFCFG Bit
> > +	*/
> > +	u32 val;
> > +	val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) &
> ~(SCR0_USFCFG_MASK);
> > +	out_le32(SMMU_SCR0, val);
> > +	val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) &
> ~(SCR0_USFCFG_MASK);
> > +	out_le32(SMMU_NSCR0, val);
> > +#endif
> > +}
> 
> Is this the same as LS1043A? Can we move this function to
> arch/arm/cpu/armv8/fsl-layerscape/spl.c?
This is true for LS1043, LS1046, however wouldn't hold good for Chassis gen3 SoC's like LS2088 , LS1088 etc. Is this file arch/arm/cpu/armv8/fsl-layerscape/spl.c common for the Chassis Gen 3 SoC's also ?

Ruchika
> 
> York