From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1168758AbcKAMfj (ORCPT ); Tue, 1 Nov 2016 08:35:39 -0400 Received: from mail-db5eur01on0089.outbound.protection.outlook.com ([104.47.2.89]:30400 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1168499AbcKAMfh (ORCPT ); Tue, 1 Nov 2016 08:35:37 -0400 From: Noam Camus To: Thomas Gleixner CC: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "daniel.lezcano@linaro.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Chris Metcalf Subject: RE: [PATCH v3 3/3] clocksource: Add clockevent support to NPS400 driver Thread-Topic: [PATCH v3 3/3] clocksource: Add clockevent support to NPS400 driver Thread-Index: AQHSM0oAza9YlT/TO0mU+ZUXCx5b4KDC3jyAgADk3qA= Date: Tue, 1 Nov 2016 09:03:32 +0000 Message-ID: References: <1477899468-5494-1-git-send-email-noamca@mellanox.com> <1477899468-5494-4-git-send-email-noamca@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=noamca@mellanox.com; x-originating-ip: [212.179.42.66] x-ms-office365-filtering-correlation-id: c401be75-cc33-4961-fc01-08d40235f472 x-microsoft-exchange-diagnostics: 1;DB6PR0501MB2759;7:pOepOhJ1s9mgbyeNATtAjjcbF2bcjAEGJGEwdXQKWXodIHGPZyY5YSXcFbbI4PJUgMa2PxzYGy7jZ2F/FSOnKOn0KFt5F/VNTXHEuvKFARaA5qwKeA6S9f2DsARlfU7qE9ncv38Sy/haun+fstUcTKjh91itAOnQScInJEh8UfNUsCo66ntWA9mdMo093O5EgX0J1lDLdoPAn4VctyR5B1EIc2dnDyR7RZxdXqYAQMGYfnV8+CgiYSYfCUVHxMmYtkEVYNpEhQSKbCSHl3xwX0IMkK4gWwt+G/2y3XP9BooSd8R7/1ze4gnye97elcDQGde9ZPvpFxRB5Fapa69PK1S2tlIVJwG+rXFuXsZW/LE= x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DB6PR0501MB2759; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(788757137089); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040176)(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001)(6055026);SRVR:DB6PR0501MB2759;BCL:0;PCL:0;RULEID:;SRVR:DB6PR0501MB2759; x-forefront-prvs: 01136D2D90 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(7916002)(189002)(69224002)(377454003)(199003)(66654002)(81166006)(7846002)(50986999)(5660300001)(76576001)(54356999)(9686002)(101416001)(107886002)(33656002)(8936002)(76176999)(77096005)(106356001)(10400500002)(2950100002)(305945005)(106116001)(86362001)(122556002)(5002640100001)(74316002)(66066001)(19580395003)(110136003)(4001430100002)(3846002)(6916009)(11100500001)(2900100001)(3660700001)(586003)(81156014)(68736007)(8676002)(97736004)(3280700002)(19580405001)(105586002)(87936001)(2906002)(102836003)(4326007)(6116002)(7696004)(92566002)(7736002)(189998001);DIR:OUT;SFP:1101;SCL:1;SRVR:DB6PR0501MB2759;H:DB6PR0501MB2518.eurprd05.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;MX:1;A:1;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Nov 2016 09:03:32.1679 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0501MB2759 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id uA1CZjPb002613 > From: Thomas Gleixner [mailto:tglx@linutronix.de] > Sent: Monday, October 31, 2016 8:13 PM >> >> -static unsigned long nps_timer_rate; >> +static unsigned long nps_timer1_freq; >This should be either in the previous patch or seperate. Will fix in V4 .... >> @@ -101,3 +101,215 @@ static int __init nps_setup_clocksource(struct >> device_node *node) >> >> CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer", >> nps_setup_clocksource); >> +CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1", >> + nps_setup_clocksource); >What's the point of this change? I do this as preparation for next patch where we use timer0 for clockevent while timer1 is kept for clocksource. I realize that it is not aligned with binding document, so I will move this to next patch. >> +/* >> + * Arm the timer to interrupt after @cycles */ static void >> +nps_clkevent_timer_event_setup(unsigned int cycles) { >> + write_aux_reg(NPS_REG_TIMER0_LIMIT, cycles); >> + write_aux_reg(NPS_REG_TIMER0_CNT, 0); /* start from 0 */ >Please do not use tail comments. They break the reading flow. Will fix in V4 >> + >> + write_aux_reg(NPS_REG_TIMER0_CTRL, TIMER0_CTRL_IE | TIMER0_CTRL_NH); >> +} >> + >> +static void nps_clkevent_rm_thread(bool remove_thread) >I have a hard time to understand why a remove_thread function needs a remove_thread boolean argument. Commenting things like this would be more helpful than commenting the obvious. Sorry for that, will be commented in V4 >> +{ >> + unsigned int cflags; >> + unsigned int enabled_threads; >>+ unsigned long flags; >> + int thread; >> + >> + local_irq_save(flags); >That's pointless. Both call sites have interrupts disabled. Will be fixed in V4 ... >> + >> +static void nps_clkevent_add_thread(bool set_event) { >> + int thread; >> + unsigned int cflags, enabled_threads; >> + unsigned long flags; >> + >> + local_irq_save(flags); >Ditto. Will be removed as well at V4 ... >> +static int nps_clkevent_set_next_event(unsigned long delta, >> + struct clock_event_device *dev) { >> + struct irq_desc *desc = irq_to_desc(nps_timer0_irq); >> + struct irq_chip *chip = irq_data_get_irq_chip(&desc->irq_data); >> + >> + nps_clkevent_add_thread(true); >> + chip->irq_unmask(&desc->irq_data); >Oh no. You are not supposed to fiddle in the guts of the interrupts from a random driver. Can you please explain what you are trying to do and why >the existing interfaces are not sufficient? This function is assigned and used by several hooks at clock_event_device type. Main purpose is to support oneshot timer mode and in general support NOHZ_FULL and finally TASK_ISOLATION. The idea for this is borrowed from arch/tile timer driver that just like us aiming to support the TASK_ISOLATION. Will it be better to replace these with irq_percpu_enable()/irq_percpu_disable() which seem to achieve quiet the same affect? ... >> +static int nps_clkevent_set_periodic(struct clock_event_device *dev) >> +{ >> + nps_clkevent_add_thread(false); >> + if (read_aux_reg(CTOP_AUX_THREAD_ID) == 0) >> + nps_clkevent_timer_event_setup(nps_timer0_freq / HZ); >So how is that enabling interrupts again? I guess that in our system we never switch back to periodic. Time infrastructure starts as periodic (I set CLOCK_EVT_FEAT_PERIODIC) and when timer is ready state is switched to oneshot mode and never goes back to periodic. I might be missing here, but couldn't find any place where CLOCK_EVT_STATE_PERIODIC is set but in tick_setup_periodic(). Should I call here to enable interrupts anyway? >> + >> +static irqreturn_t timer_irq_handler(int irq, void *dev_id) { >> + /* >> + * Note that generic IRQ core could have passed @evt for @dev_id if >> + * irq_set_chip_and_handler() asked for handle_percpu_devid_irq() > >And why are you not doing that? Will do that in V4 >> +static int __init nps_setup_clockevent(struct device_node *node) { >> + struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device); >> + struct clk *clk; >> + int ret; >> + >> + nps_timer0_irq = irq_of_parse_and_map(node, 0); >> + if (nps_timer0_irq <= 0) { >> + pr_err("clockevent: missing irq"); >> + return -EINVAL; >> + } >> + >> + nps_get_timer_clk(node, &nps_timer0_freq, clk); >> + >> + /* Needs apriori irq_set_percpu_devid() done in intc map function */ >> + ret = request_percpu_irq(nps_timer0_irq, timer_irq_handler, >> + "Timer0 (per-cpu-tick)", evt); > >This is wrong. the dev_id argument wants to be a __per_cpu pointer. So it should be &nps_clockevent_device and not a pointer to the cpu local one. Will fix that in V4 >> + if (ret) { >> + pr_err("Couldn't request irq\n"); >> + clk_disable_unprepare(clk); >> + return ret; >> + } >> + >> + ret = cpuhp_setup_state(CPUHP_AP_NPS_TIMER_STARTING, >> + "AP_NPS_TIMER_STARTING", > >Please make this "clockevents/nps:starting" Sorry but I can't see any similar thing all around. Could you explain why you prefer this format for the string? >> + nps_timer_starting_cpu, >> + nps_timer_dying_cpu); >> + if (ret) { >> + pr_err("Failed to setup hotplug state"); >> + clk_disable_unprepare(clk); > >You leave the irq requested.... Will fix that in V4. Many thanks for all comments. Waiting for your answers on my few questions above. -Noam