From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Phil Yang (Arm Technology China)" Subject: Re: [PATCH v4 2/5] meson: add infra to support machine specific flags Date: Tue, 12 Feb 2019 08:06:16 +0000 Message-ID: References: <20190106131933.7898-1-jerinj@marvell.com> <20190109103915.29210-1-pbhagavatula@marvell.com> <20190109103915.29210-2-pbhagavatula@marvell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Cc: "dev@dpdk.org" , nd , nd To: Pavan Nikhilesh Bhagavatula , "jerinj@marvell.com" , "Gavin Hu (Arm Technology China)" , "bruce.richardson@intel.com" , "thomas@monjalon.net" Return-path: Received: from EUR03-VE1-obe.outbound.protection.outlook.com (mail-eopbgr50057.outbound.protection.outlook.com [40.107.5.57]) by dpdk.org (Postfix) with ESMTP id 43FB21B44B for ; Tue, 12 Feb 2019 09:06:19 +0100 (CET) In-Reply-To: <20190109103915.29210-2-pbhagavatula@marvell.com> Content-Language: en-US List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Pavan, > -----Original Message----- > From: dev On Behalf Of Pavan Nikhilesh Bhagavatula > Sent: Wednesday, January 9, 2019 6:40 PM > To: jerinj@marvell.com; Gavin Hu (Arm Technology China) > ; bruce.richardson@intel.com; thomas@monjalon.net > Cc: dev@dpdk.org; Pavan Nikhilesh Bhagavatula > Subject: [dpdk-dev] [PATCH v4 2/5] meson: add infra to support machine sp= ecific > flags >=20 > From: Pavan Nikhilesh >=20 > Currently, RTE_* flags are set based on the implementer ID but there migh= t be > some micro arch specific differences from the same vendor eg. CACHE_LINES= IZE. > Add support to set micro arch specific flags. >=20 > Signed-off-by: Jerin Jacob > Signed-off-by: Pavan Nikhilesh > --- > config/arm/meson.build | 53 +++++++++++++++++++++++++----------------- > 1 file changed, 32 insertions(+), 21 deletions(-) >=20 > diff --git a/config/arm/meson.build b/config/arm/meson.build index > dae55d6b2..576363fc0 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -7,23 +7,6 @@ march_opt =3D '-march=3D@0@'.format(machine) >=20 > arm_force_native_march =3D false >=20 > -machine_args_generic =3D [ > - ['default', ['-march=3Darmv8-a+crc+crypto']], > - ['native', ['-march=3Dnative']], > - ['0xd03', ['-mcpu=3Dcortex-a53']], > - ['0xd04', ['-mcpu=3Dcortex-a35']], > - ['0xd07', ['-mcpu=3Dcortex-a57']], > - ['0xd08', ['-mcpu=3Dcortex-a72']], > - ['0xd09', ['-mcpu=3Dcortex-a73']], > - ['0xd0a', ['-mcpu=3Dcortex-a75']], > -] > -machine_args_cavium =3D [ > - ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], > - ['native', ['-march=3Dnative']], > - ['0xa1', ['-mcpu=3Dthunderxt88']], > - ['0xa2', ['-mcpu=3Dthunderxt81']], > - ['0xa3', ['-mcpu=3Dthunderxt83']]] > - > flags_common_default =3D [ > # Accelarate rte_memcpy. Be sure to run unit test > (memcpy_perf_autotest) > # to determine the best threshold in code. Refer to notes in source fil= e > @@ -50,12 +33,10 @@ flags_generic =3D [ > ['RTE_USE_C11_MEM_MODEL', true], > ['RTE_CACHE_LINE_SIZE', 128]] > flags_cavium =3D [ > - ['RTE_MACHINE', '"thunderx"'], > ['RTE_CACHE_LINE_SIZE', 128], > ['RTE_MAX_NUMA_NODES', 2], > ['RTE_MAX_LCORE', 96], > - ['RTE_MAX_VFIO_GROUPS', 128], > - ['RTE_USE_C11_MEM_MODEL', false]] > + ['RTE_MAX_VFIO_GROUPS', 128]] > flags_dpaa =3D [ > ['RTE_MACHINE', '"dpaa"'], > ['RTE_USE_C11_MEM_MODEL', true], > @@ -69,6 +50,27 @@ flags_dpaa2 =3D [ > ['RTE_MAX_NUMA_NODES', 1], > ['RTE_MAX_LCORE', 16], > ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] > +flags_default_extra =3D [] > +flags_thunderx_extra =3D [ > + ['RTE_MACHINE', '"thunderx"'], > + ['RTE_USE_C11_MEM_MODEL', false]] > + > +machine_args_generic =3D [ > + ['default', ['-march=3Darmv8-a+crc+crypto']], > + ['native', ['-march=3Dnative']], > + ['0xd03', ['-mcpu=3Dcortex-a53']], > + ['0xd04', ['-mcpu=3Dcortex-a35']], > + ['0xd07', ['-mcpu=3Dcortex-a57']], > + ['0xd08', ['-mcpu=3Dcortex-a72']], > + ['0xd09', ['-mcpu=3Dcortex-a73']], > + ['0xd0a', ['-mcpu=3Dcortex-a75']]] > + > +machine_args_cavium =3D [ > + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], > + ['native', ['-march=3Dnative']], > + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], > + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], > + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >=20 > ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) > impl_generic =3D ['Generic armv8', flags_generic, machine_args_generic] @= @ - > 157,10 +159,19 @@ else > foreach marg: machine[2] > if marg[0] =3D=3D impl_pn > foreach f: marg[1] > - machine_args +=3D f > + if cc.has_argument(f) > + machine_args +=3D f > + endif > endforeach > endif > endforeach > + > + # Apply any extra machine specific flags. > + foreach flag: marg.get(2, flags_default_extra) > + if flag.length() > 0 > + dpdk_conf.set(flag[0], flag[1]) > + endif > + endforeach I think this loop should put inside the 'if marg[0] =3D=3D impl_pn' conditi= on. The right logic should be: If marg[0] =3D=3D impl_pn # update machine_args # Apply any extra machine specific flags endif I tested this patch on thunderx2, but it set the octeontx2 extra flags into= the rte_build_config.h. Because octeontx2 is the last item of 'machine_arg= s_cavium' table. > endif > message(machine_args) >=20 > -- > 2.20.1 Thanks, Phil Yang.