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Sat, 21 Mar 2020 15:04:14 +0000 From: Peter Smith To: "stefan@agner.ch" CC: Ard Biesheuvel , Arnd Bergmann , clang-built-linux , Jian Cai , Linux ARM , LKML , "linux@armlinux.org.uk" , Manoj Gupta , Nick Desaulniers , Robin Murphy , Masahiro Yamada , nd Subject: Re: [PATCH 0/3] ARM: make use of UAL VFP mnemonics when possible Thread-Topic: [PATCH 0/3] ARM: make use of UAL VFP mnemonics when possible Thread-Index: AQHV/5F6uBdROLXuBUO25GaNt3oLRA== Date: Sat, 21 Mar 2020 15:04:14 +0000 Message-ID: Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: X-MS-TNEF-Correlator: Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Peter.Smith@arm.com; x-originating-ip: [82.30.113.194] x-ms-publictraffictype: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 0ac389c9-63d0-4de7-e033-08d7cda92477 x-ms-traffictypediagnostic: DBBPR08MB4428:|DBBPR08MB4428:|DB7PR08MB3322: x-ms-exchange-transport-forked: True X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true nodisclaimer: true x-ms-oob-tlc-oobclassifiers: OLM:9508;OLM:9508; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB4428 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Peter.Smith@arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM5EUR03FT046.eop-EUR03.prod.protection.outlook.com X-Forefront-Antispam-Report: CIP:63.35.35.123;IPV:CAL;SCL:-1;CTRY:IE;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(136003)(346002)(39860400002)(376002)(396003)(199004)(46966005)(36906005)(86362001)(356004)(6862004)(81156014)(8676002)(8936002)(33656002)(2906002)(7696005)(316002)(81166006)(54906003)(966005)(186003)(26826003)(47076004)(55016002)(70586007)(70206006)(6506007)(4326008)(26005)(478600001)(9686003)(5660300002)(52536014)(336012);DIR:OUT;SFP:1101;SCL:1;SRVR:DB7PR08MB3322;H:64aa7808-outbound-1.mta.getcheckrecipient.com;FPR:;SPF:Pass;LANG:en;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;A:1; X-MS-Office365-Filtering-Correlation-Id-Prvs: aa500a0c-699f-4b55-7bf3-08d7cda91ef0 X-Forefront-PRVS: 034902F5BC X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: M8lnVR78gNSu+2lBwVMq5kdNETffZ/pL2G+iao3pvRDcrGM+7bE/QHpERzlO8ayHz6JXYbqkSbXC/keueGqbsHcWe1KohFkxmy9o7JzOGa+bMIYdHIyqILKD9LOzKtc6moD8hxa5KgWaBREpR7pZSpJ4e5APV9q5hXO3qCtf2QDup9BckH51Ou1Ytx8X2+dYr9OPs+kS0tVCAUCIwGTiUkpc2WPXLbgLGl64f5V6j27280AS7zns0qXLnOfAhA29l6AMp9P3tpeCXzvKatnUgERaCiv6wAw7i95anrBE3GOVOk4phikS9JLpdcLZAZlZ9rkJtcpnscLnp05rHX3tm75ewKsAVNOGAU34xvQI7P3m7MjU5pdgLRCHF8dKQhRm4Rl+N9Gonz6UN8HZNo0FDbYVvnz19+/F/cCQO9CicUmdoW4/Vvjv47DXnkjsoAzx6V5DViW/mousm99pHXIQ7Ppd+r4KABqNvJWtKHpqmWvogmAajFuzrSikYm6kV34TJ0RJrsiRgiHj3CMLaPUGZpDR0X/VZZ7MVwiXvRGiMjCUmiUcbiM5p3dCJg8cJUwzQZuTgoz6a0aVBofJla0TwA== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2020 15:04:24.0176 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ac389c9-63d0-4de7-e033-08d7cda92477 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR08MB3322 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > To build the kernel with Clang's integrated assembler the VFP code needs= =0A= > to make use of the unified assembler language (UAL) VFP mnemonics.=0A= > =0A= > At first I tried to get rid of the co-processor instructions to access=0A= > the floating point unit along with the macros completely. However, due=0A= > to missing FPINST/FPINST2 argument support in older binutils versions we= =0A= > have to keep them around. Once we drop support for binutils 2.24 and=0A= > older, the move to UAL VFP mnemonics will be straight forward with this= =0A= > changes applied.=0A= >=0A= > Tested using Clang with integrated assembler as well as external=0A= > (binutils assembler), various gcc/binutils version down to 4.7/2.23.=0A= > Disassembled and compared the object files in arch/arm/vfp/ to make=0A= > sure this changes leads to the same code. Besides different inlining=0A= > behavior I was not able to spot a difference.=0A= >=0A= =0A= >From the perspective of an Arm toolchain developer perspective the=0A= substitutions in this patch series look correct to me.=0A= =0A= Some references I found helpful:=0A= =0A= The v8-A Arm Architecture Reference Manual chapter Legacy Instruction Synta= x for=0A= AArch32 Instruction Sets. Table K6-2 Pre-UAL instruction syntax for A32=0A= floating-point instructions=0A= =0A= FMSR/FMRS is the pre-UAL name for VMOV (between general-purpose register an= d=0A= single-precision)=0A= FMDRR/FMRRD is the pre-UAL name for VMOV (between two general-purpose=0A= registers and a doubleword floating-point register)=0A= FLDMIAD is the pre-UAL name for VLDMIA=0A= FSTMIAD is the pre-UAL name for VSTMIA=0A= =0A= FLDMIAX and FSTMIAX has no UAL equivalent and is deprecated in ARMv6 and ab= ove,=0A= it is equivalent to pre-UAL FLDMIAD/FSTMIAD except that the imm8 field is s= et=0A= to twice the number of doubleword registers + 1, instead of twice the numbe= r of=0A= doubleword registers. This description is taken from A8.8.50 F*, former=0A= Floating-point instruction mnemonics in the v7-A Arm Architecture reference= =0A= manual.=0A= =0A= The mrrc/mcrr and mcr/mcr correspond to a VMOV instruction. The mrrc/mcrr a= nd=0A= mcr/mcr set opc2 to #4 when accessing registers 16 to 31 as the instruction= s=0A= can only refer to 16 coprocessor registers. The same bit (7) in the VMOV=0A= corresponds to N, with the register n =3D UInt(N:Vn) so VMOV can refer to 3= 2=0A= registers.=0A= =0A= Ref: Arm V8-A https://static.docs.arm.com/ddi0487/fa/DDI0487F_a_armv8_arm.p= df=0A= Ref: Arm V7-A https://static.docs.arm.com/ddi0406/c/DDI0406C_C_arm_architec= ture_reference_manual.pdf=0A= =0A= Hope this helps move this forward=0A= =0A= Peter=0A= =0A= > This replaces (and extends) my earlier patch "ARM: use assembly mnemonics= =0A= > for VFP register access"=0A= > http://lore.kernel.org/r/8bb16ac4b15a7e28a8e819ef9aae20bfc3f75fbc.1582266= 841.git.stefan@agner.ch=0A= >=0A= > --=0A= > Stefan=0A= >=0A= > Stefan Agner (3):=0A= > ARM: use .fpu assembler directives instead of assembler arguments=0A= > ARM: use VFP assembler mnemonics in register load/store macros=0A= > ARM: use VFP assembler mnemonics if available=0A= >=0A= > arch/arm/include/asm/vfp.h | 2 ++=0A= > arch/arm/include/asm/vfpmacros.h | 31 ++++++++++++++++++++++---------=0A= > arch/arm/vfp/Makefile | 5 ++++-=0A= > arch/arm/vfp/vfphw.S | 31 ++++++++++++++++++++-----------=0A= > arch/arm/vfp/vfpinstr.h | 23 +++++++++++++++++++----=0A= > 5 files changed, 67 insertions(+), 25 deletions(-)=0A= > =0A= > -- =0A= > 2.25.1=0A=