From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751464AbeCTTPO (ORCPT ); Tue, 20 Mar 2018 15:15:14 -0400 Received: from mail-bn3nam01on0074.outbound.protection.outlook.com ([104.47.33.74]:15072 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751186AbeCTTPL (ORCPT ); Tue, 20 Mar 2018 15:15:11 -0400 From: Jolly Shah To: Stephen Boyd , Rob Herring CC: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "mturquette@baylibre.com" , "sboyd@codeaurora.org" , "michal.simek@xilinx.com" , Shubhrajyoti Datta , Rajan Vaja , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: RE: [PATCH 2/3] dt-bindings: clock: Add bindings for ZynqMP clock driver Thread-Topic: [PATCH 2/3] dt-bindings: clock: Add bindings for ZynqMP clock driver Thread-Index: AQHTsONzi5kT5xZmx0aJGWwSpBvQuKPCd+2AgALw7dCAACyGAIAI+snwgAls8ICAAZo/sA== Date: Tue, 20 Mar 2018 19:15:05 +0000 Message-ID: References: <1519856861-31384-1-git-send-email-jollys@xilinx.com> <1519856861-31384-3-git-send-email-jollys@xilinx.com> <20180306014549.6t3ae5adzc3cpi5v@rob-hp-laptop> <152148383577.242365.14896728603053993045@swboyd.mtv.corp.google.com> In-Reply-To: <152148383577.242365.14896728603053993045@swboyd.mtv.corp.google.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=JOLLYS@xilinx.com; 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x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 3979a874-4a4e-411d-2de8-08d58e96e34e x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(4652020)(48565401081)(5600026)(4604075)(3008032)(4534165)(4627221)(201703031133081)(201702281549075)(2017052603328)(7153060)(7193020);SRVR:DM2PR0201MB0592; x-ms-traffictypediagnostic: DM2PR0201MB0592: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917)(9452136761055)(258649278758335)(192813158149592); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(3231221)(944501244)(52105095)(93006095)(93001095)(10201501046)(3002001)(6055026)(6041310)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123560045)(6072148)(201708071742011);SRVR:DM2PR0201MB0592;BCL:0;PCL:0;RULEID:;SRVR:DM2PR0201MB0592; x-forefront-prvs: 061725F016 x-microsoft-antispam-message-info: vXYhs8voLHKL3r8E9+HK/iRRigJ/XGtZjADOU1GiJa+0O82wMo9r+rw/D110G/SP07iMmqgmFmfCop7fyp9OzfzWNuXEDzA6jaHXMvlWzghqrZum/OPGafVs4honw6eyS4U45bBTEJCWJpLXvFsjjDF76mISjPSvZI+ZbKnU3Ev7KvwRekFqccAUxdcM4nmjdXxu3usymijwP4tMF0YaTYakA7J4IO2qAT9t7Ko4TQ30tO5qkkHuB/K7MRaj2iLA7CSN7hh7XYRzy9jjdwSsvSRiUEVlLc+afimI/DHwFnFpljH8uOKg5oWB9EBgR6zwyK+7KPGbiVoR1dhNFtEz1Q== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3979a874-4a4e-411d-2de8-08d58e96e34e X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Mar 2018 19:15:05.0552 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0201MB0592 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id w2KJFQPr021767 Hi Rob and Stephan, > -----Original Message----- > From: Stephen Boyd [mailto:sboyd@kernel.org] > Sent: Monday, March 19, 2018 11:24 AM > To: Jolly Shah ; Rob Herring > Cc: mark.rutland@arm.com; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org; mturquette@baylibre.com; sboyd@codeaurora.org; > michal.simek@xilinx.com; Shubhrajyoti Datta ; Rajan > Vaja ; linux-clk@vger.kernel.org; linux-arm- > kernel@lists.infradead.org > Subject: RE: [PATCH 2/3] dt-bindings: clock: Add bindings for ZynqMP clock > driver > > Quoting Jolly Shah (2018-03-13 11:39:13) > > Hi Rob, > > > > > > What is the interface to the "platform management controller"? > > > Because you have no registers, I'm guessing a firmware interface? If > > > so, then just define the firmware node as a clock provider. > > > > Yes it is firmware interface. Along with clocks, firmware interface also controls > power and pinctrl operations as major. > > I am not sure if I understand you correctly. Do you suggest to register clocks > through Firmware driver or just use firmware DT node as clock provider and > clock driver DT node can reference clocks from FW node to register same? > > I would suggest making the firmware driver register the clks and act as the clk > provider. Not sure what Rob wants. Firmware driver just provides API interface and doesn’t actually control the clocks. Along with clocks, it provides interface for power and pinmux control also. Shall we register clocks/pins/power domains in FW driver or follow something like scpi as below and keep registration separate? zynqmp_firmware { compatible = "xlnx,zynqmp-firmware"; method = "smc"; zynqmp_clk: zynqmp_clk { compatible = "xlnx,zynqmp-clk"; #clock-cells = <1>; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk> clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk" }; zynqmp-genpd: zynqmp-genpd { compatible = "xlnx,zynqmp-genpd"; ... }; zynqmp-pinctrl: zynqmp-pinctrl { compatible = "xlnx,zynqmp-pinctrl"; ... }; }; Thanks, Jolly Shah From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Jolly Shah To: Stephen Boyd , Rob Herring CC: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "mturquette@baylibre.com" , "sboyd@codeaurora.org" , "michal.simek@xilinx.com" , Shubhrajyoti Datta , Rajan Vaja , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: RE: [PATCH 2/3] dt-bindings: clock: Add bindings for ZynqMP clock driver Date: Tue, 20 Mar 2018 19:15:05 +0000 Message-ID: References: <1519856861-31384-1-git-send-email-jollys@xilinx.com> <1519856861-31384-3-git-send-email-jollys@xilinx.com> <20180306014549.6t3ae5adzc3cpi5v@rob-hp-laptop> <152148383577.242365.14896728603053993045@swboyd.mtv.corp.google.com> In-Reply-To: <152148383577.242365.14896728603053993045@swboyd.mtv.corp.google.com> Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 List-ID: SGkgUm9iIGFuZCBTdGVwaGFuLA0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZy b206IFN0ZXBoZW4gQm95ZCBbbWFpbHRvOnNib3lkQGtlcm5lbC5vcmddDQo+IFNlbnQ6IE1vbmRh eSwgTWFyY2ggMTksIDIwMTggMTE6MjQgQU0NCj4gVG86IEpvbGx5IFNoYWggPEpPTExZU0B4aWxp bnguY29tPjsgUm9iIEhlcnJpbmcgPHJvYmhAa2VybmVsLm9yZz4NCj4gQ2M6IG1hcmsucnV0bGFu ZEBhcm0uY29tOyBkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZzsgbGludXgtDQo+IGtlcm5lbEB2 Z2VyLmtlcm5lbC5vcmc7IG10dXJxdWV0dGVAYmF5bGlicmUuY29tOyBzYm95ZEBjb2RlYXVyb3Jh Lm9yZzsNCj4gbWljaGFsLnNpbWVrQHhpbGlueC5jb207IFNodWJocmFqeW90aSBEYXR0YSA8c2h1 YmhyYWpAeGlsaW54LmNvbT47IFJhamFuDQo+IFZhamEgPFJBSkFOVkB4aWxpbnguY29tPjsgbGlu dXgtY2xrQHZnZXIua2VybmVsLm9yZzsgbGludXgtYXJtLQ0KPiBrZXJuZWxAbGlzdHMuaW5mcmFk ZWFkLm9yZw0KPiBTdWJqZWN0OiBSRTogW1BBVENIIDIvM10gZHQtYmluZGluZ3M6IGNsb2NrOiBB ZGQgYmluZGluZ3MgZm9yIFp5bnFNUCBjbG9jaw0KPiBkcml2ZXINCj4gDQo+IFF1b3RpbmcgSm9s bHkgU2hhaCAoMjAxOC0wMy0xMyAxMTozOToxMykNCj4gPiBIaSBSb2IsDQo+ID4gPg0KPiA+ID4g V2hhdCBpcyB0aGUgaW50ZXJmYWNlIHRvIHRoZSAicGxhdGZvcm0gbWFuYWdlbWVudCBjb250cm9s bGVyIj8NCj4gPiA+IEJlY2F1c2UgeW91IGhhdmUgbm8gcmVnaXN0ZXJzLCBJJ20gZ3Vlc3Npbmcg YSBmaXJtd2FyZSBpbnRlcmZhY2U/IElmDQo+ID4gPiBzbywgdGhlbiBqdXN0IGRlZmluZSB0aGUg ZmlybXdhcmUgbm9kZSBhcyBhIGNsb2NrIHByb3ZpZGVyLg0KPiA+DQo+ID4gWWVzIGl0IGlzIGZp cm13YXJlIGludGVyZmFjZS4gQWxvbmcgd2l0aCBjbG9ja3MsIGZpcm13YXJlIGludGVyZmFjZSBh bHNvIGNvbnRyb2xzDQo+IHBvd2VyIGFuZCBwaW5jdHJsIG9wZXJhdGlvbnMgYXMgbWFqb3IuDQo+ ID4gSSBhbSBub3Qgc3VyZSBpZiBJIHVuZGVyc3RhbmQgeW91IGNvcnJlY3RseS4gRG8geW91IHN1 Z2dlc3QgdG8gcmVnaXN0ZXIgY2xvY2tzDQo+IHRocm91Z2ggRmlybXdhcmUgZHJpdmVyIG9yIGp1 c3QgdXNlIGZpcm13YXJlIERUIG5vZGUgYXMgY2xvY2sgcHJvdmlkZXIgYW5kDQo+IGNsb2NrIGRy aXZlciBEVCBub2RlIGNhbiByZWZlcmVuY2UgY2xvY2tzIGZyb20gRlcgbm9kZSB0byByZWdpc3Rl ciBzYW1lPw0KPiANCj4gSSB3b3VsZCBzdWdnZXN0IG1ha2luZyB0aGUgZmlybXdhcmUgZHJpdmVy IHJlZ2lzdGVyIHRoZSBjbGtzIGFuZCBhY3QgYXMgdGhlIGNsaw0KPiBwcm92aWRlci4gTm90IHN1 cmUgd2hhdCBSb2Igd2FudHMuDQoNCkZpcm13YXJlIGRyaXZlciBqdXN0IHByb3ZpZGVzIEFQSSBp bnRlcmZhY2UgYW5kIGRvZXNu4oCZdCBhY3R1YWxseSBjb250cm9sIHRoZSBjbG9ja3MuIEFsb25n IHdpdGggY2xvY2tzLCBpdCBwcm92aWRlcyBpbnRlcmZhY2UgZm9yIHBvd2VyIGFuZCBwaW5tdXgg Y29udHJvbCBhbHNvLiBTaGFsbCB3ZSByZWdpc3RlciBjbG9ja3MvcGlucy9wb3dlciBkb21haW5z IGluIEZXIGRyaXZlciBvciBmb2xsb3cgc29tZXRoaW5nIGxpa2Ugc2NwaSBhcyBiZWxvdyBhbmQg a2VlcCByZWdpc3RyYXRpb24gc2VwYXJhdGU/IA0KDQp6eW5xbXBfZmlybXdhcmUgIHsNCgkJY29t cGF0aWJsZSA9ICJ4bG54LHp5bnFtcC1maXJtd2FyZSI7DQoJCW1ldGhvZCA9ICJzbWMiOw0KCQkN CgkJenlucW1wX2NsazogenlucW1wX2NsayB7DQoJCQkJY29tcGF0aWJsZSA9ICJ4bG54LHp5bnFt cC1jbGsiOw0KCQkJCSNjbG9jay1jZWxscyA9IDwxPjsNCgkJCQljbG9ja3MgPSA8JnBzc19yZWZf Y2xrPiwgPCZ2aWRlb19jbGs+LCA8JnBzc19hbHRfcmVmX2Nsaz4NCgkJCQljbG9jay1uYW1lcyA9 ICJwc3NfcmVmX2NsayIsICJ2aWRlb19jbGsiLCAicHNzX2FsdF9yZWZfY2xrIg0KCQl9Ow0KCQkN CgkJenlucW1wLWdlbnBkOiB6eW5xbXAtZ2VucGQgew0KCQkJCWNvbXBhdGlibGUgPSAieGxueCx6 eW5xbXAtZ2VucGQiOw0KCQkJCS4uLg0KCQl9Ow0KCQl6eW5xbXAtcGluY3RybDogenlucW1wLXBp bmN0cmwgew0KICAgICAgICAgICAgICAgIAkJCWNvbXBhdGlibGUgPSAieGxueCx6eW5xbXAtcGlu Y3RybCI7DQoJCQkgICAgICAgICAgICAgICAgLi4uDQogICAgICAgIAkJfTsNCgl9Ow0KDQpUaGFu a3MsDQpKb2xseSBTaGFoDQoNCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: JOLLYS@xilinx.com (Jolly Shah) Date: Tue, 20 Mar 2018 19:15:05 +0000 Subject: [PATCH 2/3] dt-bindings: clock: Add bindings for ZynqMP clock driver In-Reply-To: <152148383577.242365.14896728603053993045@swboyd.mtv.corp.google.com> References: <1519856861-31384-1-git-send-email-jollys@xilinx.com> <1519856861-31384-3-git-send-email-jollys@xilinx.com> <20180306014549.6t3ae5adzc3cpi5v@rob-hp-laptop> <152148383577.242365.14896728603053993045@swboyd.mtv.corp.google.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Rob and Stephan, > -----Original Message----- > From: Stephen Boyd [mailto:sboyd at kernel.org] > Sent: Monday, March 19, 2018 11:24 AM > To: Jolly Shah ; Rob Herring > Cc: mark.rutland at arm.com; devicetree at vger.kernel.org; linux- > kernel at vger.kernel.org; mturquette at baylibre.com; sboyd at codeaurora.org; > michal.simek at xilinx.com; Shubhrajyoti Datta ; Rajan > Vaja ; linux-clk at vger.kernel.org; linux-arm- > kernel at lists.infradead.org > Subject: RE: [PATCH 2/3] dt-bindings: clock: Add bindings for ZynqMP clock > driver > > Quoting Jolly Shah (2018-03-13 11:39:13) > > Hi Rob, > > > > > > What is the interface to the "platform management controller"? > > > Because you have no registers, I'm guessing a firmware interface? If > > > so, then just define the firmware node as a clock provider. > > > > Yes it is firmware interface. Along with clocks, firmware interface also controls > power and pinctrl operations as major. > > I am not sure if I understand you correctly. Do you suggest to register clocks > through Firmware driver or just use firmware DT node as clock provider and > clock driver DT node can reference clocks from FW node to register same? > > I would suggest making the firmware driver register the clks and act as the clk > provider. Not sure what Rob wants. Firmware driver just provides API interface and doesn?t actually control the clocks. Along with clocks, it provides interface for power and pinmux control also. Shall we register clocks/pins/power domains in FW driver or follow something like scpi as below and keep registration separate? zynqmp_firmware { compatible = "xlnx,zynqmp-firmware"; method = "smc"; zynqmp_clk: zynqmp_clk { compatible = "xlnx,zynqmp-clk"; #clock-cells = <1>; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk> clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk" }; zynqmp-genpd: zynqmp-genpd { compatible = "xlnx,zynqmp-genpd"; ... }; zynqmp-pinctrl: zynqmp-pinctrl { compatible = "xlnx,zynqmp-pinctrl"; ... }; }; Thanks, Jolly Shah