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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR11MB5971.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 85798a6a-bd03-4345-6882-08db414f4329 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Apr 2023 03:28:08.7455 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: SPL0XGfD0DmJJa29aBj6WZFnaApcDnch9jqRzNkg6d9gnc9YE38CNWMA3OBdubhZPjEQh9hXhRmZJS4m7Q5Sz4pXciVUAAmhl0WpW74WC3g= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB5069 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use separate "DC off" power well for ADL-P and DG2 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "intel-gfx@lists.freedesktop.org" , "De Marchi, Lucas" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" > -----Original Message----- > From: Deak, Imre > Sent: Friday, March 17, 2023 10:43 AM > To: Sripada, Radhakrishna > Cc: intel-gfx@lists.freedesktop.org; De Marchi, Lucas > > Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use separate "DC off" powe= r well > for ADL-P and DG2 >=20 > On Thu, Mar 16, 2023 at 01:25:45PM -0700, Radhakrishna Sripada wrote: > > From: Matt Roper > > > > Although ADL-P and DG2 both use the same general power well setup, the > > DC5/DC6 requirements are slightly different which means each platform > > should have its own "DC off" power well. > > > > DG2 (i.e., Xe_HPD IP) requires that DC5 be disabled whenever PG2 is > > active. However ADL-P (i.e., Xe_LPD IP) only requires DC5/DC6 to be > > disabled when the PGC or PGD subwells are active; we should be able to > > remain in these DC states when PGB and general PG2 functionality is in > > use. > > > > Bspec: 49193 > > Signed-off-by: Matt Roper > > Signed-off-by: Radhakrishna Sripada > > --- > > .../i915/display/intel_display_power_map.c | 41 +++++++++++++++++-- > > 1 file changed, 38 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c > b/drivers/gpu/drm/i915/display/intel_display_power_map.c > > index 6645eb1911d8..d9e02cc9cf3c 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c > > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c > > @@ -1301,7 +1301,8 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2, > > */ > > > > I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off, > > - XELPD_PW_2_POWER_DOMAINS, > > + XELPD_PW_C_POWER_DOMAINS, > > + XELPD_PW_D_POWER_DOMAINS, > > POWER_DOMAIN_PORT_DSI, > > POWER_DOMAIN_AUDIO_MMIO, > > POWER_DOMAIN_AUX_A, > > @@ -1310,14 +1311,38 @@ > I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off, > > POWER_DOMAIN_DC_OFF, > > POWER_DOMAIN_INIT); > > > > -static const struct i915_power_well_desc xelpd_power_wells_main[] =3D = { > > +static const struct i915_power_well_desc xelpd_power_wells_dcoff[] =3D= { >=20 > Nit: Here and in the xehpd defintion, s/dcoff/dc_off/ to match other plat= forms. >=20 > > { > > .instances =3D &I915_PW_INSTANCES( > > I915_PW("DC_off", &xelpd_pwdoms_dc_off, > > .id =3D SKL_DISP_DC_OFF), > > ), > > .ops =3D &gen9_dc_off_power_well_ops, > > - }, { > > + } > > +}; > > + > > +I915_DECL_PW_DOMAINS(xehpd_pwdoms_dc_off, > > + XELPD_PW_2_POWER_DOMAINS, > > + POWER_DOMAIN_PORT_DSI, > > + POWER_DOMAIN_AUDIO_MMIO, > > + POWER_DOMAIN_AUX_A, > > + POWER_DOMAIN_AUX_B, > > + POWER_DOMAIN_MODESET, > > + POWER_DOMAIN_DC_OFF, > > + POWER_DOMAIN_INIT); > > + > > +static const struct i915_power_well_desc xehpd_power_wells_dcoff[] =3D= { > > + { > > + .instances =3D &I915_PW_INSTANCES( > > + I915_PW("DC_off", &xehpd_pwdoms_dc_off, > > + .id =3D SKL_DISP_DC_OFF), > > + ), > > + .ops =3D &gen9_dc_off_power_well_ops, > > + } > > +}; >=20 > Could you move the xehpd definitions to precede xehpd_power_wells[]? >=20 > Patches 1, 2 look ok to me: > Reviewed-by: Imre Deak Thank you for the R-b merged Patches 1, 2 - Radhakrishna(RK) Sripada >=20 > > + > > +static const struct i915_power_well_desc xelpd_power_wells_main[] =3D = { > > + { > > .instances =3D &I915_PW_INSTANCES( > > I915_PW("PW_2", &xelpd_pwdoms_pw_2, > > .hsw.idx =3D ICL_PW_CTL_IDX_PW_2, > > @@ -1400,6 +1425,14 @@ static const struct i915_power_well_desc > xelpd_power_wells_main[] =3D { > > static const struct i915_power_well_desc_list xelpd_power_wells[] =3D = { > > I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), > > I915_PW_DESCRIPTORS(icl_power_wells_pw_1), > > + I915_PW_DESCRIPTORS(xelpd_power_wells_dcoff), > > + I915_PW_DESCRIPTORS(xelpd_power_wells_main), > > +}; > > + > > +static const struct i915_power_well_desc_list xehpd_power_wells[] =3D = { > > + I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), > > + I915_PW_DESCRIPTORS(icl_power_wells_pw_1), > > + I915_PW_DESCRIPTORS(xehpd_power_wells_dcoff), > > I915_PW_DESCRIPTORS(xelpd_power_wells_main), > > }; > > > > @@ -1624,6 +1657,8 @@ int intel_display_power_map_init(struct > i915_power_domains *power_domains) > > > > if (DISPLAY_VER(i915) >=3D 14) > > return set_power_wells(power_domains, xelpdp_power_wells); > > + else if (IS_DG2(i915)) > > + return set_power_wells(power_domains, xehpd_power_wells); > > else if (DISPLAY_VER(i915) >=3D 13) > > return set_power_wells(power_domains, xelpd_power_wells); > > else if (IS_DG1(i915)) > > -- > > 2.34.1 > >