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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB5263.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 86db4169-c376-420c-a587-08d95cd84221 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Aug 2021 14:56:54.0743 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: TLXrE8YItNF33g0aHrUP2A+zWm+5aluXehqyubwm5oxQGsOPvHz1n6MeiZJmKREe0HTJxU557lj6ZY+6uSEA3w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5199 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" [AMD Official Use Only] > -----Original Message----- > From: Kasiviswanathan, Harish > Sent: Tuesday, August 10, 2021 9:15 PM > To: Joshi, Mukul ; amd-gfx@lists.freedesktop.org > Cc: Kuehling, Felix ; Cornwall, Jay > ; Joshi, Mukul > Subject: RE: [PATCH] drm/amdkfd: CWSR with software scheduler >=20 > [AMD Official Use Only] >=20 > Just few comments inline. With that acknowledged Reviewed-by: Harish > Kasiviswanathan >=20 > -----Original Message----- > From: amd-gfx On Behalf Of Mukul > Joshi > Sent: Monday, August 9, 2021 4:41 PM > To: amd-gfx@lists.freedesktop.org > Cc: Kuehling, Felix ; Cornwall, Jay > ; Joshi, Mukul > Subject: [PATCH] drm/amdkfd: CWSR with software scheduler >=20 > This patch adds support to program trap handler settings when loading dri= ver > with software scheduler (sched_policy=3D2). >=20 > Signed-off-by: Mukul Joshi > Suggested-by: Jay Cornwall > --- > .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c | 31 +++++++++++++++++ > .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c | 31 +++++++++++++++++ > .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 33 > ++++++++++++++++++- .../drm/amd/amdkfd/kfd_device_queue_manager.c | > 20 +++++++++-- > .../gpu/drm/amd/include/kgd_kfd_interface.h | 3 ++ > 5 files changed, 115 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c > index 491acdf92f73..960acf68150a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c > @@ -560,6 +560,9 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, void > *mqd, > case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: > type =3D RESET_WAVES; > break; > + case KFD_PREEMPT_TYPE_WAVEFRONT_SAVE: > + type =3D SAVE_WAVES; > + break; > default: > type =3D DRAIN_PIPE; > break; > @@ -754,6 +757,33 @@ static void set_vm_context_page_table_base(struct > kgd_dev *kgd, uint32_t vmid, > adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); > } >=20 > +static void program_trap_handler_settings(struct kgd_dev *kgd, > + uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr) { > + struct amdgpu_device *adev =3D get_amdgpu_device(kgd); > + > + lock_srbm(kgd, 0, 0, 0, vmid); > + > + /* > + * Program TBA registers > + */ > + WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO), > + lower_32_bits(tba_addr >> 8)); > + WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI), > + upper_32_bits(tba_addr >> 8) | > + (1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT)); > + > + /* > + * Program TMA registers > + */ > + WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO), > + lower_32_bits(tma_addr >> 8)); > + WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI), > + upper_32_bits(tma_addr >> 8)); > + > + unlock_srbm(kgd); > +} > + > const struct kfd2kgd_calls gfx_v10_kfd2kgd =3D { > .program_sh_mem_settings =3D kgd_program_sh_mem_settings, > .set_pasid_vmid_mapping =3D kgd_set_pasid_vmid_mapping, @@ -774,4 > +804,5 @@ const struct kfd2kgd_calls gfx_v10_kfd2kgd =3D { > .get_atc_vmid_pasid_mapping_info =3D > get_atc_vmid_pasid_mapping_info, > .set_vm_context_page_table_base =3D > set_vm_context_page_table_base, > + .program_trap_handler_settings =3D program_trap_handler_settings, >=20 > [HK]: Naming not consistent. program_trap_handler_settings, > program_trap_handler_settings_v10_3 and > kgd_gfx_v9_program_trap_handler_settings >=20 I am following the naming convention for the other functions defined in the= se files. That's the reason the functions names are different. I don't mind naming th= em all the same. > }; > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c > index 1f5620cc3570..dac0d751d5af 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c > @@ -537,6 +537,9 @@ static int hqd_destroy_v10_3(struct kgd_dev *kgd, voi= d > *mqd, > case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: > type =3D RESET_WAVES; > break; > + case KFD_PREEMPT_TYPE_WAVEFRONT_SAVE: > + type =3D SAVE_WAVES; > + break; > default: > type =3D DRAIN_PIPE; > break; > @@ -658,6 +661,33 @@ static void > set_vm_context_page_table_base_v10_3(struct kgd_dev *kgd, uint32_t v > adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); > } >=20 > +static void program_trap_handler_settings_v10_3(struct kgd_dev *kgd, > + uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr) { > + struct amdgpu_device *adev =3D get_amdgpu_device(kgd); > + > + lock_srbm(kgd, 0, 0, 0, vmid); > + > + /* > + * Program TBA registers > + */ > + WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO), > + lower_32_bits(tba_addr >> 8)); > + WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI), > + upper_32_bits(tba_addr >> 8) | > + (1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT)); > + > + /* > + * Program TMA registers > + */ > + WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO), > + lower_32_bits(tma_addr >> 8)); > + WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI), > + upper_32_bits(tma_addr >> 8)); > + > + unlock_srbm(kgd); > +} > + > #if 0 > uint32_t enable_debug_trap_v10_3(struct kgd_dev *kgd, > uint32_t trap_debug_wave_launch_mode, @@ > -820,6 +850,7 @@ const struct kfd2kgd_calls gfx_v10_3_kfd2kgd =3D { > .address_watch_get_offset =3D address_watch_get_offset_v10_3, > .get_atc_vmid_pasid_mapping_info =3D NULL, > .set_vm_context_page_table_base =3D > set_vm_context_page_table_base_v10_3, > + .program_trap_handler_settings =3D > program_trap_handler_settings_v10_3, > #if 0 > .enable_debug_trap =3D enable_debug_trap_v10_3, > .disable_debug_trap =3D disable_debug_trap_v10_3, diff --git > a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c > index ed3014fbb563..154244916727 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c > @@ -42,7 +42,8 @@ > enum hqd_dequeue_request_type { > NO_ACTION =3D 0, > DRAIN_PIPE, > - RESET_WAVES > + RESET_WAVES, > + SAVE_WAVES > }; >=20 > static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kg= d) > @@ -566,6 +567,9 @@ int kgd_gfx_v9_hqd_destroy(struct kgd_dev *kgd, void > *mqd, > case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: > type =3D RESET_WAVES; > break; > + case KFD_PREEMPT_TYPE_WAVEFRONT_SAVE: > + type =3D SAVE_WAVES; > + break; > default: > type =3D DRAIN_PIPE; > break; > @@ -878,6 +882,32 @@ void kgd_gfx_v9_get_cu_occupancy(struct kgd_dev > *kgd, int pasid, > adev->gfx.cu_info.max_waves_per_simd; > } >=20 > +static void kgd_gfx_v9_program_trap_handler_settings(struct kgd_dev *kgd= , > + uint32_t vmid, uint64_t tba_addr, uint64_t > +tma_addr) { > + struct amdgpu_device *adev =3D get_amdgpu_device(kgd); > + > + lock_srbm(kgd, 0, 0, 0, vmid); > + > + /* > + * Program TBA registers > + */ > + WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO), > + lower_32_bits(tba_addr >> 8)); > + WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI), > + upper_32_bits(tba_addr >> 8)); > + > + /* > + * Program TMA registers > + */ > + WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO), > + lower_32_bits(tma_addr >> 8)); > + WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI), > + upper_32_bits(tma_addr >> 8)); > + > + unlock_srbm(kgd); > +} > + > const struct kfd2kgd_calls gfx_v9_kfd2kgd =3D { > .program_sh_mem_settings =3D kgd_gfx_v9_program_sh_mem_settings, > .set_pasid_vmid_mapping =3D kgd_gfx_v9_set_pasid_vmid_mapping, > @@ -899,4 +929,5 @@ const struct kfd2kgd_calls gfx_v9_kfd2kgd =3D { > kgd_gfx_v9_get_atc_vmid_pasid_mapping_info, > .set_vm_context_page_table_base =3D > kgd_gfx_v9_set_vm_context_page_table_base, > .get_cu_occupancy =3D kgd_gfx_v9_get_cu_occupancy, > + .program_trap_handler_settings =3D > +kgd_gfx_v9_program_trap_handler_settings, > }; > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c > b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c > index a972ef5eae68..6fd6b2248992 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c > @@ -211,6 +211,14 @@ static void deallocate_doorbell(struct > qcm_process_device *qpd, > WARN_ON(!old); > } >=20 > +static void program_trap_handler_settings(struct device_queue_manager > *dqm, > + struct qcm_process_device *qpd) > +{ > + return dqm->dev->kfd2kgd->program_trap_handler_settings( > + dqm->dev->kgd, qpd->vmid, > + qpd->tba_addr, qpd- > >tma_addr); >=20 > [HK]: Since, this is not defined for all GFX generations, safer to check = if function > pointer is not NULL. I see it is called only VEGA10+ >=20 Sure I can add that. However, I am making sure that the function is defined= for all ASICs after VEGA10+. Regards, Mukul > +} > + > static int allocate_vmid(struct device_queue_manager *dqm, > struct qcm_process_device *qpd, > struct queue *q) > @@ -241,6 +249,10 @@ static int allocate_vmid(struct device_queue_manager > *dqm, >=20 > program_sh_mem_settings(dqm, qpd); >=20 > + if (dqm->dev->device_info->asic_family >=3D CHIP_VEGA10 && > + dqm->dev->cwsr_enabled) > + program_trap_handler_settings(dqm, qpd); > + > /* qpd->page_table_base is set earlier when register_process() > * is called, i.e. when the first queue is created. > */ > @@ -582,7 +594,9 @@ static int update_queue(struct device_queue_manager > *dqm, struct queue *q) > } >=20 > retval =3D mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, > - KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN, > + (dqm->dev->cwsr_enabled? > + KFD_PREEMPT_TYPE_WAVEFRONT_SAVE: > + KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), > KFD_UNMAP_LATENCY_MS, q->pipe, q- > >queue); > if (retval) { > pr_err("destroy mqd failed\n"); > @@ -675,7 +689,9 @@ static int evict_process_queues_nocpsch(struct > device_queue_manager *dqm, > continue; >=20 > retval =3D mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, > - KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN, > + (dqm->dev->cwsr_enabled? > + KFD_PREEMPT_TYPE_WAVEFRONT_SAVE: > + KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN), > KFD_UNMAP_LATENCY_MS, q->pipe, q- > >queue); > if (retval && !ret) > /* Return the first error, but keep going to diff --git > a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h > b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h > index 95c656d205ed..c84bd7b2cf59 100644 > --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h > +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h > @@ -44,6 +44,7 @@ struct kgd_mem; > enum kfd_preempt_type { > KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN =3D 0, > KFD_PREEMPT_TYPE_WAVEFRONT_RESET, > + KFD_PREEMPT_TYPE_WAVEFRONT_SAVE > }; >=20 > struct kfd_vm_fault_info { > @@ -298,6 +299,8 @@ struct kfd2kgd_calls { >=20 > void (*get_cu_occupancy)(struct kgd_dev *kgd, int pasid, int > *wave_cnt, > int *max_waves_per_cu); > + void (*program_trap_handler_settings)(struct kgd_dev *kgd, > + uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr); > }; >=20 > #endif /* KGD_KFD_INTERFACE_H_INCLUDED */ > -- > 2.17.1