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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB5278.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c6308e3a-3c87-43be-a370-08dab68c1af5 X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Oct 2022 13:23:28.9704 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ObHp0TZqo3KF4vZ2FEP+rQddLxSFQ6QGj5UH4EztuBHWZp8Mdi2yx2tpFEY/WjNWvcOD8AdH9IrdzqKWw+5oXQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6243 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org [AMD Official Use Only - General] Hi Ray.=20 > -----Original Message----- > From: Huang, Ray > Sent: Tuesday, October 25, 2022 8:32 AM > To: Yuan, Perry > Cc: Limonciello, Mario ; > rafael.j.wysocki@intel.com; viresh.kumar@linaro.org; Sharma, Deepak > ; Fontenot, Nathan > ; Deucher, Alexander > ; Huang, Shimmer > ; Du, Xiaojian ; Meng, > Li (Jassmine) ; linux-pm@vger.kernel.org; linux- > kernel@vger.kernel.org; Borislav Petkov > Subject: Re: [RESEND PATCH V2 4/9] x86/msr: Add the MSR definition for > AMD CPPC boost state >=20 > On Mon, Oct 24, 2022 at 10:56:50AM +0800, Yuan, Perry wrote: > > [AMD Official Use Only - General] > > > > Hi Ray. > > > > > -----Original Message----- > > > From: Huang, Ray > > > Sent: Friday, October 21, 2022 1:22 PM > > > To: Limonciello, Mario > > > Cc: Yuan, Perry ; rafael.j.wysocki@intel.com; > > > viresh.kumar@linaro.org; Sharma, Deepak ; > > > Fontenot, Nathan ; Deucher, Alexander > > > ; Huang, Shimmer > ; > > > Du, Xiaojian ; Meng, Li (Jassmine) > > > ; linux-pm@vger.kernel.org; linux- > > > kernel@vger.kernel.org; Borislav Petkov > > > Subject: Re: [RESEND PATCH V2 4/9] x86/msr: Add the MSR definition > > > for AMD CPPC boost state > > > > > > + Boris, > > > > > > On Fri, Oct 21, 2022 at 12:05:21AM +0800, Limonciello, Mario wrote: > > > > [Public] > > > > > > > > > > > > > > > > > -----Original Message----- > > > > > From: Yuan, Perry > > > > > Sent: Thursday, October 20, 2022 11:01 > > > > > To: Huang, Ray > > > > > Cc: rafael.j.wysocki@intel.com; viresh.kumar@linaro.org; Sharma, > > > > > Deepak ; Limonciello, Mario > > > > > ; Fontenot, Nathan > > > > > ; Deucher, Alexander > > > > > ; Huang, Shimmer > > > ; > > > > > Du, Xiaojian ; Meng, Li (Jassmine) > > > > > ; linux-pm@vger.kernel.org; linux- > > > > > kernel@vger.kernel.org > > > > > Subject: RE: [RESEND PATCH V2 4/9] x86/msr: Add the MSR > > > > > definition for AMD CPPC boost state > > > > > > > > > > [AMD Official Use Only - General] > > > > > > > > > > Hi Ray. > > > > > > > > > > > -----Original Message----- > > > > > > From: Huang, Ray > > > > > > Sent: Monday, October 17, 2022 5:57 PM > > > > > > To: Yuan, Perry > > > > > > Cc: rafael.j.wysocki@intel.com; viresh.kumar@linaro.org; > > > > > > Sharma, Deepak ; Limonciello, Mario > > > > > > ; Fontenot, Nathan > > > > > > ; Deucher, Alexander > > > > > > ; Huang, Shimmer > > > > > > ; Du, Xiaojian > ; > > > > > Meng, > > > > > > Li (Jassmine) ; linux-pm@vger.kernel.org; > > > > > > linux- kernel@vger.kernel.org > > > > > > Subject: Re: [RESEND PATCH V2 4/9] x86/msr: Add the MSR > > > > > > definition for AMD CPPC boost state > > > > > > > > > > > > On Tue, Oct 11, 2022 at 12:22:43AM +0800, Yuan, Perry wrote: > > > > > > > This MSR can be used to check whether the CPU frequency > > > > > > > boost state is enabled in the hardware control. User can > > > > > > > change the boost state in the BIOS setting,amd_pstate driver > > > > > > > will update the boost state according to this msr value. > > > > > > > > > > > > > > AMD Processor Programming Reference (PPR) > > > > > > > Link: https://www.amd.com/system/files/TechDocs/40332.pdf > > > > > > > [p1095] > > > > > > > Link: https://www.amd.com/system/files/TechDocs/56569-A1- > > > PUB.zip > > > > > > > [p162] > > > > > > > > > > > > > > Signed-off-by: Perry Yuan > > > > > > > --- > > > > > > > arch/x86/include/asm/msr-index.h | 3 +++ > > > > > > > 1 file changed, 3 insertions(+) > > > > > > > > > > > > > > diff --git a/arch/x86/include/asm/msr-index.h > > > > > > > b/arch/x86/include/asm/msr-index.h > > > > > > > index 6674bdb096f3..e5ea1c9f747b 100644 > > > > > > > --- a/arch/x86/include/asm/msr-index.h > > > > > > > +++ b/arch/x86/include/asm/msr-index.h > > > > > > > @@ -569,6 +569,7 @@ > > > > > > > #define MSR_AMD_CPPC_CAP2 0xc00102b2 > > > > > > > #define MSR_AMD_CPPC_REQ 0xc00102b3 > > > > > > > #define MSR_AMD_CPPC_STATUS 0xc00102b4 > > > > > > > +#define MSR_AMD_CPPC_HW_CTL 0xc0010015 > > > > > > > > > > > > > > #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & > 0xff) > > > > > > > #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) > > > > > > > @@ -579,6 +580,8 @@ > > > > > > > #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) > > > > > > > #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) > > > > > > > #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) > << 24) > > > > > > > +#define AMD_CPPC_PRECISION_BOOST_BIT 25 > > > > > > > +#define AMD_CPPC_PRECISION_BOOST_ENABLED > > > > > > BIT_ULL(AMD_CPPC_PRECISION_BOOST_BIT) > > > > > > > > > > > > I had commented the MSR_AMD_CPPC_HW_CTL is duplicated with > > > > > > MSR_K7_HWCR > > > > > > > > > > > > https://lore.kernel.org/lkml/YtX+uF/nAIG0ykHN@amd.com/ > > > > > > https://lore.kernel.org/lkml/YtX586RDd9Xw44IO@amd.com/ > > > > > > > > > > > > Could you please make sure address the commments? > > > > > > > > > > > > Thanks, > > > > > > Ray > > > > > > > > > > If I rename that the MSR definition string, that will cause lots > > > > > of driver file change. > > > > > So I suggest to add one new MSR macro for the CPPC, the > > > > > MSR_K7_HWCR is mismatching in the CPPC Pstate driver. > > > > > If you refuse to use this new one, I will reuse that old one. > > > > > > > > To avoid changing too much stuff at once how about if you give an a= lias? > > > > IE something like: > > > > > > > > #define MSR_AMD_CPPC_HW_CTL MSR_K7_HWCR > > > > > > > > > > The mainly concern is that HWCR is for legacy ACPI P-State control > > > not for CPPC. I talked with hardware guys before, it's not suggested > > > to mix them up together. This register has been defined for a long > > > time even before Zen processor. > > > > > > Thanks, > > > Ray > > > > I have removed the code not to write boost state to that MSR, just chec= k > the boost state from the MSR bit value. > > It will not cause any problems, I have tested and confirmed that the BI= T > value will be changed after BOOST ON/OFF switched in BIOS setting. > > So we can just check the boost state here for pstate driver notificatio= n. > > >=20 > If we found MSR_K7_HWCR would impact the max frequency in CPPC, we > should report a defect or issue to firmware team. (Then we can add a quir= k > function to workaround this in amd-pstate) >=20 > Thanks, > Ray Sure , I will revise the patch and still using the MSR_K7_HWCR to check fre= q boost state in pstate driver.=20 Thanks for the feedback. Perry.