From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752640AbeC0QAD (ORCPT ); Tue, 27 Mar 2018 12:00:03 -0400 Received: from mail-by2nam01on0055.outbound.protection.outlook.com ([104.47.34.55]:20736 "EHLO NAM01-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751179AbeC0QAB (ORCPT ); Tue, 27 Mar 2018 12:00:01 -0400 From: "Ghannam, Yazen" To: "Ghannam, Yazen" , Borislav Petkov CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "tony.luck@intel.com" , "x86@kernel.org" Subject: RE: [PATCH 1/2] Revert "x86/mce/AMD: Collect error info even if valid bits are not set" Thread-Topic: [PATCH 1/2] Revert "x86/mce/AMD: Collect error info even if valid bits are not set" Thread-Index: AQHTxTbYl0Ocyw67K0ebLpEvWOkqDaPi53kAgAAAvNCAAAmPAIABK29QgAAfYjA= Date: Tue, 27 Mar 2018 15:59:37 +0000 Message-ID: References: <20180326191526.64314-1-Yazen.Ghannam@amd.com> <20180326193052.GJ25548@pd.tnic> <20180326200742.GF28372@pd.tnic> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [2601:345:301:c593:3414:3059:320b:d027] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;DM5PR12MB2567;7:G1qlRT9UxtvdlIzkMm/oJ/HNdpTO6AH1DjqXRpECUWIjCyi2WqeP1XI6pwF0qWFeyEfvj9uGJUZ0vRGHbuaH6EXpAmmNtYPyDYLTAwUmJ1wdzIssiXcG3bPZErEJIZ0zP9yBvGRrIVRywM1I1U+aBL2jO6OORdJNcgQKlDDEBf+Bwo7LKtu4GXRF19+QgLCZDWeaTXTYb3SiQuJHzjspKLB4sNjXkPZMgZR/glDcCcn0lIiMsXja+uG6wJZGhg3G;20:mPbwn73t1C62SkbxyITgtXQ11E/4lVNvFcChiGTKVN5kLF12GlCczYQj47tb9cRe0jPlyJ95mUIBkxkM3SWZZfpBl1EfE72eKxlpHVBMTkWWfLjuVK5xgXL+/Anpz86dJd225c/LqFyco+yKSUhiaJsiF/cA4TCrlUoN/mNRxSS+ZBJucxjmbLeuqUxDjhFnR4zukReNhBcVsK/sENslkTwHu3OlRAiVmRbEN3R3FoJV9vDMmGogFAMSeeczaAXz x-ms-exchange-antispam-srfa-diagnostics: SOS;SOR; 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charset="utf-8" MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7fc51e04-dc4a-4eee-70bf-08d593fbbe3b X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Mar 2018 15:59:37.8715 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2567 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id w2RG08HL022212 > -----Original Message----- > From: linux-edac-owner@vger.kernel.org owner@vger.kernel.org> On Behalf Of Ghannam, Yazen > Sent: Tuesday, March 27, 2018 10:02 AM > To: Borislav Petkov > Cc: linux-edac@vger.kernel.org; linux-kernel@vger.kernel.org; > tony.luck@intel.com; x86@kernel.org > Subject: RE: [PATCH 1/2] Revert "x86/mce/AMD: Collect error info even if > valid bits are not set" > > > -----Original Message----- > > From: Borislav Petkov > > Sent: Monday, March 26, 2018 4:08 PM > > To: Ghannam, Yazen > > Cc: linux-edac@vger.kernel.org; linux-kernel@vger.kernel.org; > > tony.luck@intel.com; x86@kernel.org > > Subject: Re: [PATCH 1/2] Revert "x86/mce/AMD: Collect error info even if > > valid bits are not set" > > > > On Mon, Mar 26, 2018 at 07:58:51PM +0000, Ghannam, Yazen wrote: > > > So at a minimum, we should always save and report as much as we can. > > > > Only on Zen or all AMD families? > > > > I'll confirm with the HW folks. I understand it as a change in philosophy > rather than a change in hardware. > So this recommendation could apply to all families, but it's okay if we just apply this behavior to SMCA systems. That way we don't need to worry about changing things on legacy systems. I'll write a new patch that abstracts the register reads and applies the different behaviors. In any case, this patch should be reverted since faking the valid bits will cause the downstream code in the notifier blocks to process errors they shouldn't. Thanks, Yazen From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [1/2] Revert "x86/mce/AMD: Collect error info even if valid bits are not set" From: Yazen Ghannam Message-Id: Date: Tue, 27 Mar 2018 15:59:37 +0000 To: "Ghannam, Yazen" , Borislav Petkov Cc: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "tony.luck@intel.com" , "x86@kernel.org" List-ID: PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBsaW51eC1lZGFjLW93bmVyQHZn ZXIua2VybmVsLm9yZyA8bGludXgtZWRhYy0NCj4gb3duZXJAdmdlci5rZXJuZWwub3JnPiBPbiBC ZWhhbGYgT2YgR2hhbm5hbSwgWWF6ZW4NCj4gU2VudDogVHVlc2RheSwgTWFyY2ggMjcsIDIwMTgg MTA6MDIgQU0NCj4gVG86IEJvcmlzbGF2IFBldGtvdiA8YnBAYWxpZW44LmRlPg0KPiBDYzogbGlu dXgtZWRhY0B2Z2VyLmtlcm5lbC5vcmc7IGxpbnV4LWtlcm5lbEB2Z2VyLmtlcm5lbC5vcmc7DQo+ IHRvbnkubHVja0BpbnRlbC5jb207IHg4NkBrZXJuZWwub3JnDQo+IFN1YmplY3Q6IFJFOiBbUEFU Q0ggMS8yXSBSZXZlcnQgIng4Ni9tY2UvQU1EOiBDb2xsZWN0IGVycm9yIGluZm8gZXZlbiBpZg0K PiB2YWxpZCBiaXRzIGFyZSBub3Qgc2V0Ig0KPiANCj4gPiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2Ut LS0tLQ0KPiA+IEZyb206IEJvcmlzbGF2IFBldGtvdiA8YnBAYWxpZW44LmRlPg0KPiA+IFNlbnQ6 IE1vbmRheSwgTWFyY2ggMjYsIDIwMTggNDowOCBQTQ0KPiA+IFRvOiBHaGFubmFtLCBZYXplbiA8 WWF6ZW4uR2hhbm5hbUBhbWQuY29tPg0KPiA+IENjOiBsaW51eC1lZGFjQHZnZXIua2VybmVsLm9y ZzsgbGludXgta2VybmVsQHZnZXIua2VybmVsLm9yZzsNCj4gPiB0b255Lmx1Y2tAaW50ZWwuY29t OyB4ODZAa2VybmVsLm9yZw0KPiA+IFN1YmplY3Q6IFJlOiBbUEFUQ0ggMS8yXSBSZXZlcnQgIng4 Ni9tY2UvQU1EOiBDb2xsZWN0IGVycm9yIGluZm8gZXZlbiBpZg0KPiA+IHZhbGlkIGJpdHMgYXJl IG5vdCBzZXQiDQo+ID4NCj4gPiBPbiBNb24sIE1hciAyNiwgMjAxOCBhdCAwNzo1ODo1MVBNICsw MDAwLCBHaGFubmFtLCBZYXplbiB3cm90ZToNCj4gPiA+IFNvIGF0IGEgbWluaW11bSwgd2Ugc2hv dWxkIGFsd2F5cyBzYXZlIGFuZCByZXBvcnQgYXMgbXVjaCBhcyB3ZSBjYW4uDQo+ID4NCj4gPiBP bmx5IG9uIFplbiBvciBhbGwgQU1EIGZhbWlsaWVzPw0KPiA+DQo+IA0KPiBJJ2xsIGNvbmZpcm0g d2l0aCB0aGUgSFcgZm9sa3MuIEkgdW5kZXJzdGFuZCBpdCBhcyBhIGNoYW5nZSBpbiBwaGlsb3Nv cGh5DQo+IHJhdGhlciB0aGFuIGEgY2hhbmdlIGluIGhhcmR3YXJlLg0KPiANCg0KU28gdGhpcyBy ZWNvbW1lbmRhdGlvbiBjb3VsZCBhcHBseSB0byBhbGwgZmFtaWxpZXMsIGJ1dCBpdCdzIG9rYXkg aWYgd2UganVzdA0KYXBwbHkgdGhpcyBiZWhhdmlvciB0byBTTUNBIHN5c3RlbXMuIFRoYXQgd2F5 IHdlIGRvbid0IG5lZWQgdG8gd29ycnkNCmFib3V0IGNoYW5naW5nIHRoaW5ncyBvbiBsZWdhY3kg c3lzdGVtcy4NCg0KSSdsbCB3cml0ZSBhIG5ldyBwYXRjaCB0aGF0IGFic3RyYWN0cyB0aGUgcmVn aXN0ZXIgcmVhZHMgYW5kIGFwcGxpZXMgdGhlDQpkaWZmZXJlbnQgYmVoYXZpb3JzLg0KDQpJbiBh bnkgY2FzZSwgdGhpcyBwYXRjaCBzaG91bGQgYmUgcmV2ZXJ0ZWQgc2luY2UgZmFraW5nIHRoZSB2 YWxpZCBiaXRzIHdpbGwNCmNhdXNlIHRoZSBkb3duc3RyZWFtIGNvZGUgaW4gdGhlIG5vdGlmaWVy IGJsb2NrcyB0byBwcm9jZXNzIGVycm9ycyB0aGV5DQpzaG91bGRuJ3QuDQoNClRoYW5rcywNCllh emVuCg==