From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751732AbeCZUFl (ORCPT ); Mon, 26 Mar 2018 16:05:41 -0400 Received: from mail-by2nam03on0058.outbound.protection.outlook.com ([104.47.42.58]:20704 "EHLO NAM03-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751107AbeCZUFj (ORCPT ); Mon, 26 Mar 2018 16:05:39 -0400 From: "Ghannam, Yazen" To: Borislav Petkov CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "tony.luck@intel.com" , "x86@kernel.org" Subject: RE: [PATCH 2/2] x86/MCE: Always save MCA_{ADDR,MISC,SYND} register contents Thread-Topic: [PATCH 2/2] x86/MCE: Always save MCA_{ADDR,MISC,SYND} register contents Thread-Index: AQHTxTbgS6+ZvZR8h0mCmC3vV5RUb6Pi6MAAgAAGmcA= Date: Mon, 26 Mar 2018 20:05:37 +0000 Message-ID: References: <20180326191526.64314-1-Yazen.Ghannam@amd.com> <20180326191526.64314-2-Yazen.Ghannam@amd.com> <20180326193526.GK25548@pd.tnic> In-Reply-To: <20180326193526.GK25548@pd.tnic> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Yazen.Ghannam@amd.com; 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x-microsoft-antispam-message-info: o5RkgjxUXFFWIaAIyx9g6ej27F4j7TMO5bK1fh5jtJrSlPUKY6vQ0/Vm26/hCtP+6TTbQQ0eo1vbdfr0s6JAQKFVH1zlIFpupanQ3TwzAtds1YiciSl/KToPT2P75vCQ5/t1iPmin/JWJ4Nm+1S+5WzMkzjgFLAiBjuZX/naxxgLhMtXrt8fvYHTGxqNz3N2oThlQxqb6GJss9LV6e873N2kwzi5HWDKDEAMU1GSArtqsB39k0J/E5o7khjk1CTNDn/w6LWW3B40Dpx/lRpFGPESRE9zR2GJt2Ad1AB4TIOJVkqvuD8UVgdkCIl4hKtMPsFOanP3UBrRw0qzh5Fc/g== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1979416d-ca47-4b25-cb87-08d59354f0fc X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Mar 2018 20:05:37.1959 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1785 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id w2QK5jSa010430 > -----Original Message----- > From: linux-edac-owner@vger.kernel.org owner@vger.kernel.org> On Behalf Of Borislav Petkov > Sent: Monday, March 26, 2018 3:35 PM > To: Ghannam, Yazen > Cc: linux-edac@vger.kernel.org; linux-kernel@vger.kernel.org; > tony.luck@intel.com; x86@kernel.org > Subject: Re: [PATCH 2/2] x86/MCE: Always save MCA_{ADDR,MISC,SYND} > register contents > > On Mon, Mar 26, 2018 at 02:15:26PM -0500, Yazen Ghannam wrote: > > From: Yazen Ghannam > > > > The Intel SDM and AMD APM both state that the contents of the > MCA_ADDR > > register should be saved if MCA_STATUS[ADDRV] is set. The same applies > > to MCA_MISC and MCA_SYND (on SMCA systems) and their respective valid > > bits. > > > > However, the Fam17h Processor Programming Reference states > > "Error handlers should save the values in MCA_ADDR, MCA_MISC0, and > > MCA_SYND even if MCA_STATUS[AddrV], MCA_STATUS[MiscV], and > > MCA_STATUS[SyndV] are zero." > > Well, then you can't remove valid bit checks for older families. This > sounds like F17h only. > > If so, it better be abstracted away cleanly and not changing the generic > code. > Sure, I can do that. But I didn't think it was necessary because it doesn't hurt to read the registers whether or not the valid bits are set. > > > > This is to ensure that all MCA state information is collected even if > > software cannot act upon it (because the valid bits are cleared). > > > > So always save the auxiliary MCA register contents even if the valid > > bits are cleared. This should not affect error processing because > > software should still check the valid bits before using the register > > contents for error processing. > > > > Also, print MCA_{ADDR,MISC,SYND} even if their valid bits are not set. > > Printing from EDAC/mce_amd is included here since we want to do this on > > AMD systems. > > > > Signed-off-by: Yazen Ghannam > > --- > > arch/x86/kernel/cpu/mcheck/mce.c | 23 +++++++---------------- > > arch/x86/kernel/cpu/mcheck/mce_amd.c | 10 +++------- > > drivers/edac/mce_amd.c | 10 +++------- > > 3 files changed, 13 insertions(+), 30 deletions(-) > > > > diff --git a/arch/x86/kernel/cpu/mcheck/mce.c > b/arch/x86/kernel/cpu/mcheck/mce.c > > index 42cf2880d0ed..a556e1cadfbc 100644 > > --- a/arch/x86/kernel/cpu/mcheck/mce.c > > +++ b/arch/x86/kernel/cpu/mcheck/mce.c > > @@ -248,19 +248,14 @@ static void __print_mce(struct mce *m) > > } > > > > pr_emerg(HW_ERR "TSC %llx ", m->tsc); > > - if (m->addr) > > - pr_cont("ADDR %llx ", m->addr); > > - if (m->misc) > > - pr_cont("MISC %llx ", m->misc); > > + pr_cont("ADDR %016llx ", m->addr); > > + pr_cont("MISC %016llx\n", m->misc); > > You simply can't do this - this is generic code, not AMD only. > I can change this if you'd like. I just thought it would be simpler to make the change here since we're just printing the values. Thanks, Yazen From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [2/2] x86/MCE: Always save MCA_{ADDR,MISC,SYND} register contents From: Yazen Ghannam Message-Id: Date: Mon, 26 Mar 2018 20:05:37 +0000 To: Borislav Petkov Cc: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "tony.luck@intel.com" , "x86@kernel.org" List-ID: PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBsaW51eC1lZGFjLW93bmVyQHZn ZXIua2VybmVsLm9yZyA8bGludXgtZWRhYy0NCj4gb3duZXJAdmdlci5rZXJuZWwub3JnPiBPbiBC ZWhhbGYgT2YgQm9yaXNsYXYgUGV0a292DQo+IFNlbnQ6IE1vbmRheSwgTWFyY2ggMjYsIDIwMTgg MzozNSBQTQ0KPiBUbzogR2hhbm5hbSwgWWF6ZW4gPFlhemVuLkdoYW5uYW1AYW1kLmNvbT4NCj4g Q2M6IGxpbnV4LWVkYWNAdmdlci5rZXJuZWwub3JnOyBsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwu b3JnOw0KPiB0b255Lmx1Y2tAaW50ZWwuY29tOyB4ODZAa2VybmVsLm9yZw0KPiBTdWJqZWN0OiBS ZTogW1BBVENIIDIvMl0geDg2L01DRTogQWx3YXlzIHNhdmUgTUNBX3tBRERSLE1JU0MsU1lORH0N Cj4gcmVnaXN0ZXIgY29udGVudHMNCj4gDQo+IE9uIE1vbiwgTWFyIDI2LCAyMDE4IGF0IDAyOjE1 OjI2UE0gLTA1MDAsIFlhemVuIEdoYW5uYW0gd3JvdGU6DQo+ID4gRnJvbTogWWF6ZW4gR2hhbm5h bSA8eWF6ZW4uZ2hhbm5hbUBhbWQuY29tPg0KPiA+DQo+ID4gVGhlIEludGVsIFNETSBhbmQgQU1E IEFQTSBib3RoIHN0YXRlIHRoYXQgdGhlIGNvbnRlbnRzIG9mIHRoZQ0KPiBNQ0FfQUREUg0KPiA+ IHJlZ2lzdGVyIHNob3VsZCBiZSBzYXZlZCBpZiBNQ0FfU1RBVFVTW0FERFJWXSBpcyBzZXQuIFRo ZSBzYW1lIGFwcGxpZXMNCj4gPiB0byBNQ0FfTUlTQyBhbmQgTUNBX1NZTkQgKG9uIFNNQ0Egc3lz dGVtcykgYW5kIHRoZWlyIHJlc3BlY3RpdmUgdmFsaWQNCj4gPiBiaXRzLg0KPiA+DQo+ID4gSG93 ZXZlciwgdGhlIEZhbTE3aCBQcm9jZXNzb3IgUHJvZ3JhbW1pbmcgUmVmZXJlbmNlIHN0YXRlcw0K PiA+ICJFcnJvciBoYW5kbGVycyBzaG91bGQgc2F2ZSB0aGUgdmFsdWVzIGluIE1DQV9BRERSLCBN Q0FfTUlTQzAsIGFuZA0KPiA+IE1DQV9TWU5EIGV2ZW4gaWYgTUNBX1NUQVRVU1tBZGRyVl0sIE1D QV9TVEFUVVNbTWlzY1ZdLCBhbmQNCj4gPiBNQ0FfU1RBVFVTW1N5bmRWXSBhcmUgemVyby4iDQo+ IA0KPiBXZWxsLCB0aGVuIHlvdSBjYW4ndCByZW1vdmUgdmFsaWQgYml0IGNoZWNrcyBmb3Igb2xk ZXIgZmFtaWxpZXMuIFRoaXMNCj4gc291bmRzIGxpa2UgRjE3aCBvbmx5Lg0KPiANCj4gSWYgc28s IGl0IGJldHRlciBiZSBhYnN0cmFjdGVkIGF3YXkgY2xlYW5seSBhbmQgbm90IGNoYW5naW5nIHRo ZSBnZW5lcmljDQo+IGNvZGUuDQo+IA0KDQpTdXJlLCBJIGNhbiBkbyB0aGF0LiBCdXQgSSBkaWRu J3QgdGhpbmsgaXQgd2FzIG5lY2Vzc2FyeSBiZWNhdXNlIGl0IGRvZXNuJ3QgaHVydA0KdG8gcmVh ZCB0aGUgcmVnaXN0ZXJzIHdoZXRoZXIgb3Igbm90IHRoZSB2YWxpZCBiaXRzIGFyZSBzZXQuDQoN Cj4gPg0KPiA+IFRoaXMgaXMgdG8gZW5zdXJlIHRoYXQgYWxsIE1DQSBzdGF0ZSBpbmZvcm1hdGlv biBpcyBjb2xsZWN0ZWQgZXZlbiBpZg0KPiA+IHNvZnR3YXJlIGNhbm5vdCBhY3QgdXBvbiBpdCAo YmVjYXVzZSB0aGUgdmFsaWQgYml0cyBhcmUgY2xlYXJlZCkuDQo+ID4NCj4gPiBTbyBhbHdheXMg c2F2ZSB0aGUgYXV4aWxpYXJ5IE1DQSByZWdpc3RlciBjb250ZW50cyBldmVuIGlmIHRoZSB2YWxp ZA0KPiA+IGJpdHMgYXJlIGNsZWFyZWQuIFRoaXMgc2hvdWxkIG5vdCBhZmZlY3QgZXJyb3IgcHJv Y2Vzc2luZyBiZWNhdXNlDQo+ID4gc29mdHdhcmUgc2hvdWxkIHN0aWxsIGNoZWNrIHRoZSB2YWxp ZCBiaXRzIGJlZm9yZSB1c2luZyB0aGUgcmVnaXN0ZXINCj4gPiBjb250ZW50cyBmb3IgZXJyb3Ig cHJvY2Vzc2luZy4NCj4gPg0KPiA+IEFsc28sIHByaW50IE1DQV97QUREUixNSVNDLFNZTkR9IGV2 ZW4gaWYgdGhlaXIgdmFsaWQgYml0cyBhcmUgbm90IHNldC4NCj4gPiBQcmludGluZyBmcm9tIEVE QUMvbWNlX2FtZCBpcyBpbmNsdWRlZCBoZXJlIHNpbmNlIHdlIHdhbnQgdG8gZG8gdGhpcyBvbg0K PiA+IEFNRCBzeXN0ZW1zLg0KPiA+DQo+ID4gU2lnbmVkLW9mZi1ieTogWWF6ZW4gR2hhbm5hbSA8 eWF6ZW4uZ2hhbm5hbUBhbWQuY29tPg0KPiA+IC0tLQ0KPiA+ICBhcmNoL3g4Ni9rZXJuZWwvY3B1 L21jaGVjay9tY2UuYyAgICAgfCAyMyArKysrKysrLS0tLS0tLS0tLS0tLS0tLQ0KPiA+ICBhcmNo L3g4Ni9rZXJuZWwvY3B1L21jaGVjay9tY2VfYW1kLmMgfCAxMCArKystLS0tLS0tDQo+ID4gIGRy aXZlcnMvZWRhYy9tY2VfYW1kLmMgICAgICAgICAgICAgICB8IDEwICsrKy0tLS0tLS0NCj4gPiAg MyBmaWxlcyBjaGFuZ2VkLCAxMyBpbnNlcnRpb25zKCspLCAzMCBkZWxldGlvbnMoLSkNCj4gPg0K PiA+IGRpZmYgLS1naXQgYS9hcmNoL3g4Ni9rZXJuZWwvY3B1L21jaGVjay9tY2UuYw0KPiBiL2Fy Y2gveDg2L2tlcm5lbC9jcHUvbWNoZWNrL21jZS5jDQo+ID4gaW5kZXggNDJjZjI4ODBkMGVkLi5h NTU2ZTFjYWRmYmMgMTAwNjQ0DQo+ID4gLS0tIGEvYXJjaC94ODYva2VybmVsL2NwdS9tY2hlY2sv bWNlLmMNCj4gPiArKysgYi9hcmNoL3g4Ni9rZXJuZWwvY3B1L21jaGVjay9tY2UuYw0KPiA+IEBA IC0yNDgsMTkgKzI0OCwxNCBAQCBzdGF0aWMgdm9pZCBfX3ByaW50X21jZShzdHJ1Y3QgbWNlICpt KQ0KPiA+ICAJfQ0KPiA+DQo+ID4gIAlwcl9lbWVyZyhIV19FUlIgIlRTQyAlbGx4ICIsIG0tPnRz Yyk7DQo+ID4gLQlpZiAobS0+YWRkcikNCj4gPiAtCQlwcl9jb250KCJBRERSICVsbHggIiwgbS0+ YWRkcik7DQo+ID4gLQlpZiAobS0+bWlzYykNCj4gPiAtCQlwcl9jb250KCJNSVNDICVsbHggIiwg bS0+bWlzYyk7DQo+ID4gKwlwcl9jb250KCJBRERSICUwMTZsbHggIiwgbS0+YWRkcik7DQo+ID4g Kwlwcl9jb250KCJNSVNDICUwMTZsbHhcbiIsIG0tPm1pc2MpOw0KPiANCj4gWW91IHNpbXBseSBj YW4ndCBkbyB0aGlzIC0gdGhpcyBpcyBnZW5lcmljIGNvZGUsIG5vdCBBTUQgb25seS4NCj4gDQoN CkkgY2FuIGNoYW5nZSB0aGlzIGlmIHlvdSdkIGxpa2UuIEkganVzdCB0aG91Z2h0IGl0IHdvdWxk IGJlIHNpbXBsZXIgdG8NCm1ha2UgdGhlIGNoYW5nZSBoZXJlIHNpbmNlIHdlJ3JlIGp1c3QgcHJp bnRpbmcgdGhlIHZhbHVlcy4NCg0KVGhhbmtzLA0KWWF6ZW4K