From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Yin, Tianci (Rico)" Subject: Re: [PATCH 8/8] drm/amdgpu/psp: add psp memory training implementation Date: Wed, 16 Oct 2019 02:19:57 +0000 Message-ID: References: <20191014032118.14020-1-tianci.yin@amd.com> <20191014032118.14020-8-tianci.yin@amd.com>, Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="_004_DM5PR12MB2535098825FB8316985B8A6995920DM5PR12MB2535namp_" Return-path: In-Reply-To: Content-Language: en-US List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: "Tuikov, Luben" , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" Cc: "Deucher, Alexander" , "Koenig, Christian" --_004_DM5PR12MB2535098825FB8316985B8A6995920DM5PR12MB2535namp_ Content-Type: multipart/alternative; boundary="_000_DM5PR12MB2535098825FB8316985B8A6995920DM5PR12MB2535namp_" --_000_DM5PR12MB2535098825FB8316985B8A6995920DM5PR12MB2535namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks very much! Please review again. Rico ________________________________ From: Tuikov, Luben Sent: Wednesday, October 16, 2019 1:59 To: Yin, Tianci (Rico) ; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org = Cc: Koenig, Christian ; Deucher, Alexander Subject: Re: [PATCH 8/8] drm/amdgpu/psp: add psp memory training implementa= tion On 2019-10-13 11:21 p.m., Tianci Yin wrote: > From: "Tianci.Yin" > > add memory training implementation code to save resume time. > > Change-Id: I625794a780b11d824ab57ef39cc33b872c6dc6c9 > Reviewed-by: Alex Deucher > Signed-off-by: Tianci.Yin > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 ++ > drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 159 ++++++++++++++++++++++++ > 3 files changed, 169 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/am= dgpu/amdgpu.h > index 8704f93cabf2..c2b776fd82b5 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -151,6 +151,7 @@ extern uint amdgpu_sdma_phase_quantum; > extern char *amdgpu_disable_cu; > extern char *amdgpu_virtual_display; > extern uint amdgpu_pp_feature_mask; > +extern uint amdgpu_force_long_training; > extern int amdgpu_job_hang_limit; > extern int amdgpu_lbpw; > extern int amdgpu_compute_multipipe; > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/am= d/amdgpu/amdgpu_drv.c > index da7cbee25c61..c7d086569acb 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > @@ -127,6 +127,7 @@ char *amdgpu_disable_cu =3D NULL; > char *amdgpu_virtual_display =3D NULL; > /* OverDrive(bit 14) disabled by default*/ > uint amdgpu_pp_feature_mask =3D 0xffffbfff; > +uint amdgpu_force_long_training =3D 0; > int amdgpu_job_hang_limit =3D 0; > int amdgpu_lbpw =3D -1; > int amdgpu_compute_multipipe =3D -1; > @@ -390,6 +391,14 @@ module_param_named(sched_hw_submission, amdgpu_sched= _hw_submission, int, 0444); > MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))")= ; > module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); > > +/** > + * DOC: forcelongtraining (uint) > + * Force long memory training in resume. > + * The default is zero, indicates short training in resume. > + */ > +MODULE_PARM_DESC(forcelongtraining, "force memory long training"); > +module_param_named(forcelongtraining, amdgpu_force_long_training, uint, = 0444); > + > /** > * DOC: pcie_gen_cap (uint) > * Override PCIE gen speed capabilities. See the CAIL flags in drivers/g= pu/drm/amd/include/amd_pcie.h. > diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd= /amdgpu/psp_v11_0.c > index 2ba0f68ced10..b7efaa3e913c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c > @@ -902,6 +902,162 @@ static int psp_v11_0_rlc_autoload_start(struct psp_= context *psp) > return psp_rlc_autoload_start(psp); > } > > +static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, i= nt msg) > +{ > + int ret =3D 0; > + int i =3D 0; > + uint32_t data_32 =3D 0; NAK! Leave all of those integer variables uninitialized. > + struct amdgpu_device *adev =3D psp->adev; > + > + data_32 =3D (psp->mem_train_ctx.c2p_train_data_offset >> 20); > + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32); > + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg); > + > + /*max 5s*/ > + while (i < 50) { > + ret =3D psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SM= N_C2PMSG_35), > + 0x80000000, 0x80000000, false); > + if (ret =3D=3D 0) > + break; > + i++; > + } NAK! For-loop please: for (i =3D 0; i < 50; i++) { ret =3D ...; } Regards, Luben > + DRM_DEBUG("%s training %s, cost %d * %dms.\n", > + (msg =3D=3D PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", > + (ret =3D=3D 0) ? "succeed" : "failed", > + i, adev->usec_timeout/1000); > + return ret; > +} > + > +static int psp_v11_0_memory_training_fini(struct psp_context *psp) > +{ > + int ret =3D 0; > + struct psp_memory_training_context *ctx =3D &psp->mem_train_ctx; > + > + ctx->init =3D PSP_MEM_TRAIN_NOT_SUPPORT; > + if(ctx->sys_cache) { > + kfree(ctx->sys_cache); > + ctx->sys_cache =3D NULL; > + } > + > + return ret; > +} > + > +static int psp_v11_0_memory_training_init(struct psp_context *psp) > +{ > + int ret =3D 0; > + struct psp_memory_training_context *ctx =3D &psp->mem_train_ctx; > + > + if(ctx->init !=3D PSP_MEM_TRAIN_RESERVE_SUCCESS) { > + DRM_DEBUG("memory training does not support!\n"); > + return 0; > + } > + > + ctx->sys_cache =3D kzalloc(ctx->train_data_size, GFP_KERNEL); > + if(ctx->sys_cache =3D=3D NULL) { > + DRM_ERROR("alloc mem_train_ctx.sys_cache failed(%d)!\n", re= t); > + ret =3D -ENOMEM; > + goto Err_out; > + } > + > + DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_trai= n_data_offset:%llx.\n", > + ctx->train_data_size, > + ctx->p2c_train_data_offset, > + ctx->c2p_train_data_offset); > + ctx->init =3D PSP_MEM_TRAIN_INIT_SUCCESS; > + return 0; > + > +Err_out: > + psp_v11_0_memory_training_fini(psp); > + return ret; > +} > + > +/* > + * save and restore proces > + */ > +static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t o= ps) > +{ > + int ret =3D 0; > + uint32_t p2c_header[4]; > + struct psp_memory_training_context *ctx =3D &psp->mem_train_ctx; > + uint32_t *pcache =3D (uint32_t*)ctx->sys_cache; > + > + if (ctx->init =3D=3D PSP_MEM_TRAIN_NOT_SUPPORT) { > + DRM_DEBUG("Memory training does not support.\n"); > + return 0; > + } else if (ctx->init !=3D PSP_MEM_TRAIN_INIT_SUCCESS) { > + DRM_ERROR("Please check initialization failure.\n"); > + return -EINVAL; > + } > + > + if (psp_v11_0_is_sos_alive(psp)) { > + DRM_DEBUG("sos is alive, skip memory training.\n"); > + return 0; > + } > + > + amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, p2= c_header, sizeof(p2c_header), false); > + DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x= ,%08x]\n", > + pcache[0], pcache[1], pcache[2], pcache[3], > + p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3= ]); > + > + if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { > + DRM_DEBUG("short training depend on restore.\n"); > + ops |=3D PSP_MEM_TRAIN_RESTORE; > + } > + > + if ((ops & PSP_MEM_TRAIN_RESTORE) && > + pcache[0] !=3D MEM_TRAIN_SYSTEM_SIGNATURE) { > + DRM_DEBUG("sys_cache[0] is invalid, restore depend on save.= \n"); > + ops |=3D PSP_MEM_TRAIN_SAVE; > + } > + > + if (p2c_header[0] =3D=3D MEM_TRAIN_SYSTEM_SIGNATURE && > + !(pcache[0] =3D=3D MEM_TRAIN_SYSTEM_SIGNATURE && > + pcache[3] =3D=3D p2c_header[3])) { > + DRM_DEBUG("sys_cache is invalid or out-of-date, need save t= raining data to sys_cache.\n"); > + ops |=3D PSP_MEM_TRAIN_SAVE; > + } > + > + if ((ops & PSP_MEM_TRAIN_SAVE) && > + p2c_header[0] !=3D MEM_TRAIN_SYSTEM_SIGNATURE) { > + DRM_DEBUG("p2c_header[0] is invalid, save depend on long tr= aining.\n"); > + ops |=3D PSP_MEM_TRAIN_SEND_LONG_MSG; > + } > + > + if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { > + ops &=3D ~PSP_MEM_TRAIN_SEND_SHORT_MSG; > + ops |=3D PSP_MEM_TRAIN_SAVE; > + } > + > + DRM_DEBUG("mem training ops:%x.\n", ops); > + > + if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { > + ret =3D psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRA= M_LONG_TRAIN); > + if (ret) { > + DRM_ERROR("send long training msg failed.\n"); > + return ret; > + } > + } > + > + if (ops & PSP_MEM_TRAIN_SAVE) { > + amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_of= fset, ctx->sys_cache, ctx->train_data_size, false); > + } > + > + if (ops & PSP_MEM_TRAIN_RESTORE) { > + amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_of= fset, ctx->sys_cache, ctx->train_data_size, true); > + } > + > + if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { > + ret =3D psp_v11_0_memory_training_send_msg(psp, (amdgpu_for= ce_long_training > 0) ? > + PSP_BL__DRAM_LONG_= TRAIN : PSP_BL__DRAM_SHORT_TRAIN); > + if (ret) { > + DRM_ERROR("send training msg failed.\n"); > + return ret; > + } > + } > + ctx->training_cnt++; > + return ret; > +} > + > static const struct psp_funcs psp_v11_0_funcs =3D { > .init_microcode =3D psp_v11_0_init_microcode, > .bootloader_load_kdb =3D psp_v11_0_bootloader_load_kdb, > @@ -922,6 +1078,9 @@ static const struct psp_funcs psp_v11_0_funcs =3D { > .ras_trigger_error =3D psp_v11_0_ras_trigger_error, > .ras_cure_posion =3D psp_v11_0_ras_cure_posion, > .rlc_autoload_start =3D psp_v11_0_rlc_autoload_start, > + .mem_training_init =3D psp_v11_0_memory_training_init, > + .mem_training_fini =3D psp_v11_0_memory_training_fini, > + .mem_training =3D psp_v11_0_memory_training, > }; > > void psp_v11_0_set_psp_funcs(struct psp_context *psp) > --_000_DM5PR12MB2535098825FB8316985B8A6995920DM5PR12MB2535namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Thanks very much! Please review again.

Rico
From: Tuikov, Luben <Lub= en.Tuikov-5C7GfCeVMHo@public.gmane.org>
Sent: Wednesday, October 16, 2019 1:59
To: Yin, Tianci (Rico) <Tianci.Yin-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32mzQB+pC5nmwQ@public.gmane.org= edesktop.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Koenig, Christian <Christian.Koenig-5C7GfCeVMHo@public.gmane.org>; Deucher, Ale= xander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
Subject: Re: [PATCH 8/8] drm/amdgpu/psp: add psp memory training imp= lementation
 
On 2019-10-13 11:21 p.m., Tianci Yin wrote:
> From: "Tianci.Yin" <tianci.yin-5C7GfCeVMHo@public.gmane.org>
>
> add memory training implementation code to save resume time.
>
> Change-Id: I625794a780b11d824ab57ef39cc33b872c6dc6c9
> Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
> Signed-off-by: Tianci.Yin <tianci.yin-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h     |&nb= sp;  1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |   9 += 3;
>  drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 159 ++= 3;++++++++++++++= 3;++++++
>  3 files changed, 169 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd= /amdgpu/amdgpu.h
> index 8704f93cabf2..c2b776fd82b5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -151,6 +151,7 @@ extern uint amdgpu_sdma_phase_quantum;
>  extern char *amdgpu_disable_cu;
>  extern char *amdgpu_virtual_display;
>  extern uint amdgpu_pp_feature_mask;
> +extern uint amdgpu_force_long_training;
>  extern int amdgpu_job_hang_limit;
>  extern int amdgpu_lbpw;
>  extern int amdgpu_compute_multipipe;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm= /amd/amdgpu/amdgpu_drv.c
> index da7cbee25c61..c7d086569acb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -127,6 +127,7 @@ char *amdgpu_disable_cu =3D NULL;
>  char *amdgpu_virtual_display =3D NULL;
>  /* OverDrive(bit 14) disabled by default*/
>  uint amdgpu_pp_feature_mask =3D 0xffffbfff;
> +uint amdgpu_force_long_training =3D 0;
>  int amdgpu_job_hang_limit =3D 0;
>  int amdgpu_lbpw =3D -1;
>  int amdgpu_compute_multipipe =3D -1;
> @@ -390,6 +391,14 @@ module_param_named(sched_hw_submission, amdgp= u_sched_hw_submission, int, 0444);
>  MODULE_PARM_DESC(ppfeaturemask, "all power features enabled= (default))");
>  module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, = 0444);
> 
> +/**
> + * DOC: forcelongtraining (uint)
> + * Force long memory training in resume.
> + * The default is zero, indicates short training in resume.
> + */
> +MODULE_PARM_DESC(forcelongtraining, "force memory long train= ing");
> +module_param_named(forcelongtraining, amdgpu_force_long_training,= uint, 0444);
> +
>  /**
>   * DOC: pcie_gen_cap (uint)
>   * Override PCIE gen speed capabilities. See the CAIL flags= in drivers/gpu/drm/amd/include/amd_pcie.h.
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/= amd/amdgpu/psp_v11_0.c
> index 2ba0f68ced10..b7efaa3e913c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> @@ -902,6 +902,162 @@ static int psp_v11_0_rlc_autoload_start(stru= ct psp_context *psp)
>        return psp_rlc_autoload_star= t(psp);
>  }
> 
> +static int psp_v11_0_memory_training_send_msg(struct psp_context = *psp, int msg)
> +{
> +     int ret =3D 0;
> +     int i =3D 0;
> +     uint32_t data_32 =3D 0;

NAK!

Leave all of those integer variables uninitialized.

> +     struct amdgpu_device *adev =3D psp->a= dev;
> +
> +     data_32 =3D (psp->mem_train_ctx.c2p_t= rain_data_offset >> 20);
> +     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36= , data_32);
> +     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35= , msg);
> +
> +     /*max 5s*/
> +     while (i < 50) {
> +           = ;  ret =3D psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG= _35),
> +           = ;            &n= bsp;        0x80000000, 0x80000000, fals= e);
> +           = ;  if (ret =3D=3D 0)
> +           = ;          break;
> +           = ;  i++;
> +     }

NAK!

For-loop please:

for (i =3D 0; i < 50; i++) {
        ret =3D ...;
}

Regards,
Luben

> +     DRM_DEBUG("%s training %s, cost %d = * %dms.\n",
> +           = ;    (msg =3D=3D PSP_BL__DRAM_SHORT_TRAIN) ? "short&quo= t; : "long",
> +           = ;    (ret =3D=3D 0) ? "succeed" : "failed&quo= t;,
> +           = ;    i, adev->usec_timeout/1000);
> +     return ret;
> +}
> +
> +static int psp_v11_0_memory_training_fini(struct psp_context *psp= )
> +{
> +     int ret =3D 0;
> +     struct psp_memory_training_context *ctx = =3D &psp->mem_train_ctx;
> +
> +     ctx->init =3D PSP_MEM_TRAIN_NOT_SUPPO= RT;
> +     if(ctx->sys_cache) {
> +           = ;  kfree(ctx->sys_cache);
> +           = ;  ctx->sys_cache =3D NULL;
> +     }
> +
> +     return ret;
> +}
> +
> +static int psp_v11_0_memory_training_init(struct psp_context *psp= )
> +{
> +     int ret =3D 0;
> +     struct psp_memory_training_context *ctx = =3D &psp->mem_train_ctx;
> +
> +     if(ctx->init !=3D PSP_MEM_TRAIN_RESER= VE_SUCCESS) {
> +           = ;  DRM_DEBUG("memory training does not support!\n");
> +           = ;  return 0;
> +     }
> +
> +     ctx->sys_cache =3D kzalloc(ctx->tr= ain_data_size, GFP_KERNEL);
> +     if(ctx->sys_cache =3D=3D NULL) {
> +           = ;  DRM_ERROR("alloc mem_train_ctx.sys_cache failed(%d)!\n", = ret);
> +           = ;  ret =3D -ENOMEM;
> +           = ;  goto Err_out;
> +     }
> +
> +     DRM_DEBUG("train_data_size:%llx,p2c= _train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
> +           = ;    ctx->train_data_size,
> +           = ;    ctx->p2c_train_data_offset,
> +           = ;    ctx->c2p_train_data_offset);
> +     ctx->init =3D PSP_MEM_TRAIN_INIT_SUCC= ESS;
> +     return 0;
> +
> +Err_out:
> +     psp_v11_0_memory_training_fini(psp);
> +     return ret;
> +}
> +
> +/*
> + * save and restore proces
> + */
> +static int psp_v11_0_memory_training(struct psp_context *psp, uin= t32_t ops)
> +{
> +     int ret =3D 0;
> +     uint32_t p2c_header[4];
> +     struct psp_memory_training_context *ctx = =3D &psp->mem_train_ctx;
> +     uint32_t *pcache =3D (uint32_t*)ctx->= sys_cache;
> +
> +     if (ctx->init =3D=3D PSP_MEM_TRAIN_NO= T_SUPPORT) {
> +           = ;  DRM_DEBUG("Memory training does not support.\n");
> +           = ;  return 0;
> +     } else if (ctx->init !=3D PSP_MEM_TRA= IN_INIT_SUCCESS) {
> +           = ;  DRM_ERROR("Please check initialization failure.\n");
> +           = ;  return -EINVAL;
> +     }
> +
> +     if (psp_v11_0_is_sos_alive(psp)) {
> +           = ;  DRM_DEBUG("sos is alive, skip memory training.\n");
> +           = ;  return 0;
> +     }
> +
> +     amdgpu_device_vram_access(psp->adev, = ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
> +     DRM_DEBUG("sys_cache[%08x,%08x,%08x= ,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
> +           = ;    pcache[0], pcache[1], pcache[2], pcache[3],
> +           = ;    p2c_header[0], p2c_header[1], p2c_header[2], p2c_header= [3]);
> +
> +     if (ops & PSP_MEM_TRAIN_SEND_SHORT_M= SG) {
> +           = ;  DRM_DEBUG("short training depend on restore.\n");
> +           = ;  ops |=3D PSP_MEM_TRAIN_RESTORE;
> +     }
> +
> +     if ((ops & PSP_MEM_TRAIN_RESTORE) &a= mp;&
> +         pcache[0] !=3D M= EM_TRAIN_SYSTEM_SIGNATURE) {
> +           = ;  DRM_DEBUG("sys_cache[0] is invalid, restore depend on save.\n&= quot;);
> +           = ;  ops |=3D PSP_MEM_TRAIN_SAVE;
> +     }
> +
> +     if (p2c_header[0] =3D=3D MEM_TRAIN_SYSTE= M_SIGNATURE &&
> +         !(pcache[0] =3D= =3D MEM_TRAIN_SYSTEM_SIGNATURE &&
> +           pcac= he[3] =3D=3D p2c_header[3])) {
> +           = ;  DRM_DEBUG("sys_cache is invalid or out-of-date, need save trai= ning data to sys_cache.\n");
> +           = ;  ops |=3D PSP_MEM_TRAIN_SAVE;
> +     }
> +
> +     if ((ops & PSP_MEM_TRAIN_SAVE) &= &
> +         p2c_header[0] != =3D MEM_TRAIN_SYSTEM_SIGNATURE) {
> +           = ;  DRM_DEBUG("p2c_header[0] is invalid, save depend on long train= ing.\n");
> +           = ;  ops |=3D PSP_MEM_TRAIN_SEND_LONG_MSG;
> +     }
> +
> +     if (ops & PSP_MEM_TRAIN_SEND_LONG_MS= G) {
> +           = ;  ops &=3D ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
> +           = ;  ops |=3D PSP_MEM_TRAIN_SAVE;
> +     }
> +
> +     DRM_DEBUG("mem training ops:%x.\n&q= uot;, ops);
> +
> +     if (ops & PSP_MEM_TRAIN_SEND_LONG_MS= G) {
> +           = ;  ret =3D psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_T= RAIN);
> +           = ;  if (ret) {
> +           = ;          DRM_ERROR("sen= d long training msg failed.\n");
> +           = ;          return ret;
> +           = ;  }
> +     }
> +
> +     if (ops & PSP_MEM_TRAIN_SAVE) {
> +           = ;  amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offs= et, ctx->sys_cache, ctx->train_data_size, false);
> +     }
> +
> +     if (ops & PSP_MEM_TRAIN_RESTORE) { > +           = ;  amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offs= et, ctx->sys_cache, ctx->train_data_size, true);
> +     }
> +
> +     if (ops & PSP_MEM_TRAIN_SEND_SHORT_M= SG) {
> +           = ;  ret =3D psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_= training > 0) ?
> +           = ;            &n= bsp;            = ;            &n= bsp;     PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_T= RAIN);
> +           = ;  if (ret) {
> +           = ;          DRM_ERROR("sen= d training msg failed.\n");
> +           = ;          return ret;
> +           = ;  }
> +     }
> +     ctx->training_cnt++;
> +     return ret;
> +}
> +
>  static const struct psp_funcs psp_v11_0_funcs =3D {
>        .init_microcode =3D psp_v11_= 0_init_microcode,
>        .bootloader_load_kdb =3D psp= _v11_0_bootloader_load_kdb,
> @@ -922,6 +1078,9 @@ static const struct psp_funcs psp_v11_0_funcs= =3D {
>        .ras_trigger_error =3D psp_v= 11_0_ras_trigger_error,
>        .ras_cure_posion =3D psp_v11= _0_ras_cure_posion,
>        .rlc_autoload_start =3D psp_= v11_0_rlc_autoload_start,
> +     .mem_training_init =3D psp_v11_0_memory_= training_init,
> +     .mem_training_fini =3D psp_v11_0_memory_= training_fini,
> +     .mem_training =3D psp_v11_0_memory_train= ing,
>  };
> 
>  void psp_v11_0_set_psp_funcs(struct psp_context *psp)
>

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