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Mon, 4 May 2020 11:55:24 +0000 From: Nava kishore Manne To: Moritz Fischer CC: Michal Simek , "linux-fpga@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "chinnikishore369@gmail.com" Subject: RE: [PATCH 2/2] fpga: zynq: Add AFI config driver Thread-Topic: [PATCH 2/2] fpga: zynq: Add AFI config driver Thread-Index: AQHWExAhzZUocH0/3EuatlmWIllh3KiGGIAAgBHUQYA= Date: Mon, 4 May 2020 11:55:23 +0000 Message-ID: References: <1586946290-7280-1-git-send-email-nava.manne@xilinx.com> <1586946290-7280-2-git-send-email-nava.manne@xilinx.com> <20200423032854.GB2430@epycbox.lan> In-Reply-To: <20200423032854.GB2430@epycbox.lan> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=xilinx.com; x-originating-ip: [149.199.50.129] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: b0f4afc2-5634-4446-3064-08d7f022076d x-ms-traffictypediagnostic: DM6PR02MB6124:|DM6PR02MB6124: x-ld-processed: 657af505-d5df-48d0-8300-c31994686c5c,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:335; 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Please find my response inline. > -----Original Message----- > From: Moritz Fischer [mailto:mdf@kernel.org] > Sent: Thursday, April 23, 2020 8:59 AM > To: Nava kishore Manne > Cc: mdf@kernel.org; Michal Simek ; linux- > fpga@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; chinnikishore369@gmail.com > Subject: Re: [PATCH 2/2] fpga: zynq: Add AFI config driver >=20 > Hi Nava, >=20 > On Wed, Apr 15, 2020 at 03:54:50PM +0530, Nava kishore Manne wrote: > > This patch Adds AFI config driver. This is useful for the PS to PL > > configuration for the fpga manager On zynq platform. > > > > Signed-off-by: Nava kishore Manne > > --- > > drivers/fpga/Kconfig | 8 +++++ > > drivers/fpga/Makefile | 1 + > > drivers/fpga/zynq-afi.c | 81 > > +++++++++++++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 90 insertions(+) > > create mode 100644 drivers/fpga/zynq-afi.c > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index > > 474f304e..60982a0 100644 > > --- a/drivers/fpga/Kconfig > > +++ b/drivers/fpga/Kconfig > > @@ -214,4 +214,12 @@ config FPGA_MGR_ZYNQMP_FPGA > > to configure the programmable logic(PL) through PS > > on ZynqMP SoC. > > > > +config FPGA_MGR_ZYNQ_AFI_FPGA > > + bool "Xilinx AFI FPGA" > > + depends on FPGA_MGR_ZYNQ_FPGA > Curious. How does this dependency play in here? > > + help > > + Zynq AFI driver support for writing to the AFI registers > > + for configuring the PS_PL interface. For some of the bitstream > > + or designs to work the PS to PL interfaces need to be configured > > + like the data bus-width etc. > > endif # FPGA > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index > > 312b937..d115e29 100644 > > --- a/drivers/fpga/Makefile > > +++ b/drivers/fpga/Makefile > > @@ -26,6 +26,7 @@ obj-$(CONFIG_FPGA_BRIDGE) +=3D fpga- > bridge.o > > obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) +=3D altera-hps2fpga.o altera- > fpga2sdram.o > > obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) +=3D altera-freeze-bridge.o > > obj-$(CONFIG_XILINX_PR_DECOUPLER) +=3D xilinx-pr-decoupler.o > > +obj-$(CONFIG_FPGA_MGR_ZYNQ_AFI_FPGA) +=3D zynq-afi.o > > > > # High Level Interfaces > > obj-$(CONFIG_FPGA_REGION) +=3D fpga-region.o > > diff --git a/drivers/fpga/zynq-afi.c b/drivers/fpga/zynq-afi.c new > > file mode 100644 index 0000000..7ce0d08 > > --- /dev/null > > +++ b/drivers/fpga/zynq-afi.c > > @@ -0,0 +1,81 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Xilinx FPGA AFI driver. > > + * Copyright (c) 2018 Xilinx Inc. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* Registers and special values for doing register-based operations */ > > +#define AFI_RDCHAN_CTRL_OFFSET 0x00 > > +#define AFI_WRCHAN_CTRL_OFFSET 0x14 > > + > > +#define AFI_BUSWIDTH_MASK 0x01 > > + > > +/** > > + * struct afi_fpga - AFI register description > > + * @membase: pointer to register struct > > + * @afi_width: AFI bus width to be written > > + */ > > +struct zynq_afi_fpga { > > + void __iomem *membase; > > + u32 afi_width; > > +}; > > + > > +static int zynq_afi_fpga_probe(struct platform_device *pdev) { > > + struct zynq_afi_fpga *afi_fpga; > > + struct resource *res; > > + u32 reg_val; > > + u32 val; > > + > > + afi_fpga =3D devm_kzalloc(&pdev->dev, sizeof(*afi_fpga), GFP_KERNEL); > > + if (!afi_fpga) > > + return -ENOMEM; > > + > > + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); > > + afi_fpga->membase =3D devm_ioremap_resource(&pdev->dev, res); > > + if (IS_ERR(afi_fpga->membase)) > > + return PTR_ERR(afi_fpga->membase); > > + > > + val =3D device_property_read_u32(&pdev->dev, "xlnx,afi-width", > > + &afi_fpga->afi_width); > > + if (val) { > > + dev_err(&pdev->dev, "Fail to get the afi bus width\n"); > > + return -EINVAL; > > + } > > + > > + reg_val =3D readl(afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET); > > + reg_val &=3D ~AFI_BUSWIDTH_MASK; > > + writel(reg_val | afi_fpga->afi_width, > > + afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET); > > + reg_val =3D readl(afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET); > > + reg_val &=3D ~AFI_BUSWIDTH_MASK; > > + writel(reg_val | afi_fpga->afi_width, > > + afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET); > > + > > + return 0; > > +} > > + > > +static const struct of_device_id zynq_afi_fpga_ids[] =3D { > > + { .compatible =3D "xlnx,zynq-afi-fpga" }, > > + { }, > > +}; > > +MODULE_DEVICE_TABLE(of, zynq_afi_fpga_ids); > > + > > +static struct platform_driver zynq_afi_fpga_driver =3D { > > + .driver =3D { > > + .name =3D "zynq-afi-fpga", > > + .of_match_table =3D zynq_afi_fpga_ids, > > + }, > > + .probe =3D zynq_afi_fpga_probe, > > +}; > > +module_platform_driver(zynq_afi_fpga_driver); > > + > > +MODULE_DESCRIPTION("ZYNQ FPGA AFI module"); > MODULE_AUTHOR("Nava > > +kishore Manne "); MODULE_LICENSE("GPL v2"); > > -- > > 2.7.4 > > >=20 > It looks like all the driver does is writing two registers? How does > that fit into FPGA Manager as a framework. Should this maybe be eithe > for Zynq architecture or a Misc driver instead? >=20 To establish the proper communication channel between PS and PL, The AXI In= terface Bus Width should be configured properly. For a design to design this AXI Interface Bus Width settings are vary. So f= or Zynq just loading the Bitstream into the PL is not sufficient to establish a proper communication channel between PS and PL we have to do= AXI Interface Bus Width settings as per the design after loading the Bit file into the PL. I feel this is more relevant to the= FPGA settings so I have placed this driver here. Please suggest the best place to put this driver. > Is the idea here to create the device via an overlay? Yes, this driver loading/removal is triggered by the overlay after loading = the bit file into the PL. Regards, Navakishore. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: Received: from mail-bn8nam11on2085.outbound.protection.outlook.com ([40.107.236.85]:22592 "EHLO NAM11-BN8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728612AbgEDLz1 (ORCPT ); Mon, 4 May 2020 07:55:27 -0400 From: Nava kishore Manne Subject: RE: [PATCH 2/2] fpga: zynq: Add AFI config driver Date: Mon, 4 May 2020 11:55:23 +0000 Message-ID: References: <1586946290-7280-1-git-send-email-nava.manne@xilinx.com> <1586946290-7280-2-git-send-email-nava.manne@xilinx.com> <20200423032854.GB2430@epycbox.lan> In-Reply-To: <20200423032854.GB2430@epycbox.lan> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: linux-fpga-owner@vger.kernel.org List-Id: linux-fpga@vger.kernel.org To: Moritz Fischer Cc: Michal Simek , "linux-fpga@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "chinnikishore369@gmail.com" Hi Mortiz, Thanks for proving the comments. Please find my response inline. > -----Original Message----- > From: Moritz Fischer [mailto:mdf@kernel.org] > Sent: Thursday, April 23, 2020 8:59 AM > To: Nava kishore Manne > Cc: mdf@kernel.org; Michal Simek ; linux- > fpga@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; chinnikishore369@gmail.com > Subject: Re: [PATCH 2/2] fpga: zynq: Add AFI config driver >=20 > Hi Nava, >=20 > On Wed, Apr 15, 2020 at 03:54:50PM +0530, Nava kishore Manne wrote: > > This patch Adds AFI config driver. This is useful for the PS to PL > > configuration for the fpga manager On zynq platform. > > > > Signed-off-by: Nava kishore Manne > > --- > > drivers/fpga/Kconfig | 8 +++++ > > drivers/fpga/Makefile | 1 + > > drivers/fpga/zynq-afi.c | 81 > > +++++++++++++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 90 insertions(+) > > create mode 100644 drivers/fpga/zynq-afi.c > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index > > 474f304e..60982a0 100644 > > --- a/drivers/fpga/Kconfig > > +++ b/drivers/fpga/Kconfig > > @@ -214,4 +214,12 @@ config FPGA_MGR_ZYNQMP_FPGA > > to configure the programmable logic(PL) through PS > > on ZynqMP SoC. > > > > +config FPGA_MGR_ZYNQ_AFI_FPGA > > + bool "Xilinx AFI FPGA" > > + depends on FPGA_MGR_ZYNQ_FPGA > Curious. How does this dependency play in here? > > + help > > + Zynq AFI driver support for writing to the AFI registers > > + for configuring the PS_PL interface. For some of the bitstream > > + or designs to work the PS to PL interfaces need to be configured > > + like the data bus-width etc. > > endif # FPGA > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index > > 312b937..d115e29 100644 > > --- a/drivers/fpga/Makefile > > +++ b/drivers/fpga/Makefile > > @@ -26,6 +26,7 @@ obj-$(CONFIG_FPGA_BRIDGE) +=3D fpga- > bridge.o > > obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) +=3D altera-hps2fpga.o altera- > fpga2sdram.o > > obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) +=3D altera-freeze-bridge.o > > obj-$(CONFIG_XILINX_PR_DECOUPLER) +=3D xilinx-pr-decoupler.o > > +obj-$(CONFIG_FPGA_MGR_ZYNQ_AFI_FPGA) +=3D zynq-afi.o > > > > # High Level Interfaces > > obj-$(CONFIG_FPGA_REGION) +=3D fpga-region.o > > diff --git a/drivers/fpga/zynq-afi.c b/drivers/fpga/zynq-afi.c new > > file mode 100644 index 0000000..7ce0d08 > > --- /dev/null > > +++ b/drivers/fpga/zynq-afi.c > > @@ -0,0 +1,81 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Xilinx FPGA AFI driver. > > + * Copyright (c) 2018 Xilinx Inc. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* Registers and special values for doing register-based operations */ > > +#define AFI_RDCHAN_CTRL_OFFSET 0x00 > > +#define AFI_WRCHAN_CTRL_OFFSET 0x14 > > + > > +#define AFI_BUSWIDTH_MASK 0x01 > > + > > +/** > > + * struct afi_fpga - AFI register description > > + * @membase: pointer to register struct > > + * @afi_width: AFI bus width to be written > > + */ > > +struct zynq_afi_fpga { > > + void __iomem *membase; > > + u32 afi_width; > > +}; > > + > > +static int zynq_afi_fpga_probe(struct platform_device *pdev) { > > + struct zynq_afi_fpga *afi_fpga; > > + struct resource *res; > > + u32 reg_val; > > + u32 val; > > + > > + afi_fpga =3D devm_kzalloc(&pdev->dev, sizeof(*afi_fpga), GFP_KERNEL); > > + if (!afi_fpga) > > + return -ENOMEM; > > + > > + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); > > + afi_fpga->membase =3D devm_ioremap_resource(&pdev->dev, res); > > + if (IS_ERR(afi_fpga->membase)) > > + return PTR_ERR(afi_fpga->membase); > > + > > + val =3D device_property_read_u32(&pdev->dev, "xlnx,afi-width", > > + &afi_fpga->afi_width); > > + if (val) { > > + dev_err(&pdev->dev, "Fail to get the afi bus width\n"); > > + return -EINVAL; > > + } > > + > > + reg_val =3D readl(afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET); > > + reg_val &=3D ~AFI_BUSWIDTH_MASK; > > + writel(reg_val | afi_fpga->afi_width, > > + afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET); > > + reg_val =3D readl(afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET); > > + reg_val &=3D ~AFI_BUSWIDTH_MASK; > > + writel(reg_val | afi_fpga->afi_width, > > + afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET); > > + > > + return 0; > > +} > > + > > +static const struct of_device_id zynq_afi_fpga_ids[] =3D { > > + { .compatible =3D "xlnx,zynq-afi-fpga" }, > > + { }, > > +}; > > +MODULE_DEVICE_TABLE(of, zynq_afi_fpga_ids); > > + > > +static struct platform_driver zynq_afi_fpga_driver =3D { > > + .driver =3D { > > + .name =3D "zynq-afi-fpga", > > + .of_match_table =3D zynq_afi_fpga_ids, > > + }, > > + .probe =3D zynq_afi_fpga_probe, > > +}; > > +module_platform_driver(zynq_afi_fpga_driver); > > + > > +MODULE_DESCRIPTION("ZYNQ FPGA AFI module"); > MODULE_AUTHOR("Nava > > +kishore Manne "); MODULE_LICENSE("GPL v2"); > > -- > > 2.7.4 > > >=20 > It looks like all the driver does is writing two registers? How does > that fit into FPGA Manager as a framework. Should this maybe be eithe > for Zynq architecture or a Misc driver instead? >=20 To establish the proper communication channel between PS and PL, The AXI In= terface Bus Width should be configured properly. For a design to design this AXI Interface Bus Width settings are vary. So f= or Zynq just loading the Bitstream into the PL is not sufficient to establish a proper communication channel between PS and PL we have to do= AXI Interface Bus Width settings as per the design after loading the Bit file into the PL. I feel this is more relevant to the= FPGA settings so I have placed this driver here. Please suggest the best place to put this driver. > Is the idea here to create the device via an overlay? Yes, this driver loading/removal is triggered by the overlay after loading = the bit file into the PL. Regards, Navakishore. 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mortiz, Thanks for proving the comments. Please find my response inline. > -----Original Message----- > From: Moritz Fischer [mailto:mdf@kernel.org] > Sent: Thursday, April 23, 2020 8:59 AM > To: Nava kishore Manne > Cc: mdf@kernel.org; Michal Simek ; linux- > fpga@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; chinnikishore369@gmail.com > Subject: Re: [PATCH 2/2] fpga: zynq: Add AFI config driver > > Hi Nava, > > On Wed, Apr 15, 2020 at 03:54:50PM +0530, Nava kishore Manne wrote: > > This patch Adds AFI config driver. This is useful for the PS to PL > > configuration for the fpga manager On zynq platform. > > > > Signed-off-by: Nava kishore Manne > > --- > > drivers/fpga/Kconfig | 8 +++++ > > drivers/fpga/Makefile | 1 + > > drivers/fpga/zynq-afi.c | 81 > > +++++++++++++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 90 insertions(+) > > create mode 100644 drivers/fpga/zynq-afi.c > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index > > 474f304e..60982a0 100644 > > --- a/drivers/fpga/Kconfig > > +++ b/drivers/fpga/Kconfig > > @@ -214,4 +214,12 @@ config FPGA_MGR_ZYNQMP_FPGA > > to configure the programmable logic(PL) through PS > > on ZynqMP SoC. > > > > +config FPGA_MGR_ZYNQ_AFI_FPGA > > + bool "Xilinx AFI FPGA" > > + depends on FPGA_MGR_ZYNQ_FPGA > Curious. How does this dependency play in here? > > + help > > + Zynq AFI driver support for writing to the AFI registers > > + for configuring the PS_PL interface. For some of the bitstream > > + or designs to work the PS to PL interfaces need to be configured > > + like the data bus-width etc. > > endif # FPGA > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index > > 312b937..d115e29 100644 > > --- a/drivers/fpga/Makefile > > +++ b/drivers/fpga/Makefile > > @@ -26,6 +26,7 @@ obj-$(CONFIG_FPGA_BRIDGE) += fpga- > bridge.o > > obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera- > fpga2sdram.o > > obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o > > obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o > > +obj-$(CONFIG_FPGA_MGR_ZYNQ_AFI_FPGA) += zynq-afi.o > > > > # High Level Interfaces > > obj-$(CONFIG_FPGA_REGION) += fpga-region.o > > diff --git a/drivers/fpga/zynq-afi.c b/drivers/fpga/zynq-afi.c new > > file mode 100644 index 0000000..7ce0d08 > > --- /dev/null > > +++ b/drivers/fpga/zynq-afi.c > > @@ -0,0 +1,81 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Xilinx FPGA AFI driver. > > + * Copyright (c) 2018 Xilinx Inc. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* Registers and special values for doing register-based operations */ > > +#define AFI_RDCHAN_CTRL_OFFSET 0x00 > > +#define AFI_WRCHAN_CTRL_OFFSET 0x14 > > + > > +#define AFI_BUSWIDTH_MASK 0x01 > > + > > +/** > > + * struct afi_fpga - AFI register description > > + * @membase: pointer to register struct > > + * @afi_width: AFI bus width to be written > > + */ > > +struct zynq_afi_fpga { > > + void __iomem *membase; > > + u32 afi_width; > > +}; > > + > > +static int zynq_afi_fpga_probe(struct platform_device *pdev) { > > + struct zynq_afi_fpga *afi_fpga; > > + struct resource *res; > > + u32 reg_val; > > + u32 val; > > + > > + afi_fpga = devm_kzalloc(&pdev->dev, sizeof(*afi_fpga), GFP_KERNEL); > > + if (!afi_fpga) > > + return -ENOMEM; > > + > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > + afi_fpga->membase = devm_ioremap_resource(&pdev->dev, res); > > + if (IS_ERR(afi_fpga->membase)) > > + return PTR_ERR(afi_fpga->membase); > > + > > + val = device_property_read_u32(&pdev->dev, "xlnx,afi-width", > > + &afi_fpga->afi_width); > > + if (val) { > > + dev_err(&pdev->dev, "Fail to get the afi bus width\n"); > > + return -EINVAL; > > + } > > + > > + reg_val = readl(afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET); > > + reg_val &= ~AFI_BUSWIDTH_MASK; > > + writel(reg_val | afi_fpga->afi_width, > > + afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET); > > + reg_val = readl(afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET); > > + reg_val &= ~AFI_BUSWIDTH_MASK; > > + writel(reg_val | afi_fpga->afi_width, > > + afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET); > > + > > + return 0; > > +} > > + > > +static const struct of_device_id zynq_afi_fpga_ids[] = { > > + { .compatible = "xlnx,zynq-afi-fpga" }, > > + { }, > > +}; > > +MODULE_DEVICE_TABLE(of, zynq_afi_fpga_ids); > > + > > +static struct platform_driver zynq_afi_fpga_driver = { > > + .driver = { > > + .name = "zynq-afi-fpga", > > + .of_match_table = zynq_afi_fpga_ids, > > + }, > > + .probe = zynq_afi_fpga_probe, > > +}; > > +module_platform_driver(zynq_afi_fpga_driver); > > + > > +MODULE_DESCRIPTION("ZYNQ FPGA AFI module"); > MODULE_AUTHOR("Nava > > +kishore Manne "); MODULE_LICENSE("GPL v2"); > > -- > > 2.7.4 > > > > It looks like all the driver does is writing two registers? How does > that fit into FPGA Manager as a framework. Should this maybe be eithe > for Zynq architecture or a Misc driver instead? > To establish the proper communication channel between PS and PL, The AXI Interface Bus Width should be configured properly. For a design to design this AXI Interface Bus Width settings are vary. So for Zynq just loading the Bitstream into the PL is not sufficient to establish a proper communication channel between PS and PL we have to do AXI Interface Bus Width settings as per the design after loading the Bit file into the PL. I feel this is more relevant to the FPGA settings so I have placed this driver here. Please suggest the best place to put this driver. > Is the idea here to create the device via an overlay? Yes, this driver loading/removal is triggered by the overlay after loading the bit file into the PL. Regards, Navakishore. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel