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Sat, 16 May 2020 13:01:26 +0000 From: Anup Patel To: Marc Zyngier CC: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Jason Cooper , Atish Patra , Alistair Francis , Anup Patel , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH 3/4] irqchip/sifive-plic: Separate irq_chip for muiltiple PLIC instances Thread-Topic: [PATCH 3/4] irqchip/sifive-plic: Separate irq_chip for muiltiple PLIC instances Thread-Index: AQHWK0zIG2SJo4BaZ0+zBbhx696gsKiqpKoAgAAHeAA= Date: Sat, 16 May 2020 13:01:26 +0000 Message-ID: References: <20200516063901.18365-1-anup.patel@wdc.com> <20200516063901.18365-4-anup.patel@wdc.com> <577f9a16b3dddfadb7c5487ffaef31d8@kernel.org> In-Reply-To: <577f9a16b3dddfadb7c5487ffaef31d8@kernel.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=wdc.com; x-originating-ip: [106.51.108.254] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 060a9c3c-d440-4db8-342f-08d7f9993e5d x-ms-traffictypediagnostic: DM6PR04MB6969: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:7691; 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x-ms-exchange-antispam-messagedata: PXtjWr9IILJlChDRoYNDgu649AyIRnesPFVjUjwv47Mj19BZHZHOeRIcanVsAhDjHku9fuuMd6p0Xx+wn2Rade47b09PWo0S6+C8ys0L6HXlai8+AFt6D2gUdOLJXskLHZYTl2PDG6ONVHLhuUBmgabjjSRqGpnqM1rX2/S2Tl7NApFa0GMnDMVT3eU+TQnoxv78ZKa+Kzi/R+P0jShw8PTXAUOYM3t/wAqd2CfpBqtG+vdlYT/Xx5CcUtx0aQTifR4RMpa3zTf8TyDnuqC3jjsSrYr2RDmq8CRNNiLgbfdige2cyqH4PvJfEioPPrlF2sip761JP2Fy+E3bUYtilOi6L5a2+zNMQJmYBJLA31XSbDDAPUQ1jSP6w5TV2dYIfT2eh6LHoOesMiXzO177l9QJ2QrzcNh9JaijNS6paYPfOhXcbh1wG+anpkQC8l0wSD52mvPGTvH/Qgwky5Lf8OCksv6mQpw3ok5MNHFbXBXbhddQzDT5tVnTBywk0ySB Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 060a9c3c-d440-4db8-342f-08d7f9993e5d X-MS-Exchange-CrossTenant-originalarrivaltime: 16 May 2020 13:01:26.7073 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pO7rYZC7yzFrJWHyKrbB2w+O6KM1C5LRVLE0t4Ah4/qIvosz5352N1kDOWu21W7sukvySv1hX0Lv7Pqh9RM+KA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR04MB6969 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Marc Zyngier > Sent: 16 May 2020 17:59 > To: Anup Patel > Cc: Palmer Dabbelt ; Paul Walmsley > ; Thomas Gleixner ; Jason > Cooper ; Atish Patra ; Alistai= r > Francis ; Anup Patel ; lin= ux- > riscv@lists.infradead.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 3/4] irqchip/sifive-plic: Separate irq_chip for muilt= iple PLIC > instances >=20 > On 2020-05-16 07:39, Anup Patel wrote: > > To distinguish interrupts from multiple PLIC instances, we use a > > per-PLIC irq_chip instance with a different name. > > > > Signed-off-by: Anup Patel > > --- > > drivers/irqchip/irq-sifive-plic.c | 28 +++++++++++++++------------- > > 1 file changed, 15 insertions(+), 13 deletions(-) > > > > diff --git a/drivers/irqchip/irq-sifive-plic.c > > b/drivers/irqchip/irq-sifive-plic.c > > index 2d3db927a551..e42fc082ad18 100644 > > --- a/drivers/irqchip/irq-sifive-plic.c > > +++ b/drivers/irqchip/irq-sifive-plic.c > > @@ -60,6 +60,7 @@ > > #define PLIC_ENABLE_THRESHOLD 0 > > > > struct plic_priv { > > + struct irq_chip chip; > > struct cpumask lmask; > > struct irq_domain *irqdomain; > > void __iomem *regs; > > @@ -76,6 +77,7 @@ struct plic_handler { > > void __iomem *enable_base; > > struct plic_priv *priv; > > }; > > +static unsigned int plic_count; > > static bool plic_cpuhp_setup_done; > > static DEFINE_PER_CPU(struct plic_handler, plic_handlers); > > > > @@ -164,20 +166,12 @@ static void plic_irq_eoi(struct irq_data *d) > > writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); } > > > > -static struct irq_chip plic_chip =3D { > > - .name =3D "SiFive PLIC", > > - .irq_mask =3D plic_irq_mask, > > - .irq_unmask =3D plic_irq_unmask, > > - .irq_eoi =3D plic_irq_eoi, > > -#ifdef CONFIG_SMP > > - .irq_set_affinity =3D plic_set_affinity, > > -#endif > > -}; > > - > > static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, > > irq_hw_number_t hwirq) > > { > > - irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, > > + struct plic_priv *priv =3D d->host_data; > > + > > + irq_domain_set_info(d, irq, hwirq, &priv->chip, d->host_data, > > handle_fasteoi_irq, NULL, NULL); > > irq_set_noprobe(irq); > > return 0; > > @@ -294,6 +288,14 @@ static int __init plic_init(struct device_node > > *node, > > if (!priv) > > return -ENOMEM; > > > > + priv->chip.name =3D kasprintf(GFP_KERNEL, "PLIC%d", plic_count++); > > + priv->chip.irq_mask =3D plic_irq_mask, > > + priv->chip.irq_unmask =3D plic_irq_unmask, > > + priv->chip.irq_eoi =3D plic_irq_eoi, > > +#ifdef CONFIG_SMP > > + priv->chip.irq_set_affinity =3D plic_set_affinity, #endif > > + > > priv->regs =3D of_iomap(node, 0); > > if (WARN_ON(!priv->regs)) { > > error =3D -EIO; > > @@ -383,9 +385,9 @@ static int __init plic_init(struct device_node > > *node, > > } > > > > pr_info("interrupt-controller at 0x%llx " > > - "(interrupts=3D%d, contexts=3D%d, handlers=3D%d)\n", > > + "(interrupts=3D%d, contexts=3D%d, handlers=3D%d) (%s)\n", > > (unsigned long long)iores.start, nr_irqs, > > - nr_contexts, nr_handlers); > > + nr_contexts, nr_handlers, priv->chip.name); > > set_handle_irq(plic_handle_irq); > > return 0; >=20 > I really dislike this patch for multiple reasons: >=20 > - Allocating a new struc irq_chip just for a string seems over the top, > specially as all the *useful* stuff stays the same. >=20 > - Even if I hate it, /proc is API. I'm sure something, somewhere is > parsing this. Changing the string is likely to confuse it. AFAIK, we don't have scripts in RISC-V world that depend on /proc/interrupts content. May be in future such scripts will show up. For system with multiple PLICs, we are seeing same "SiFive PLIC" string for all PLIC interrupts in "cat /proc/interrupts". I am trying to assign different string based on PLIC instance. This is similar to what GICv2 driver is doing (e.g. GIC-0, GIC-1, ... in /proc/interrupts). Is there a better way to do this ? >=20 > - If you do this for debug purposes, then CONFIG_GENERIC_IRQ_DEBUGFS > is the right way to look up the information. >=20 > - If, for reasons that are beyond me, you actually *need* this, then > implementing irq_print_chip in your irq_chip structure is the way > to go. >=20 > But frankly, I'd rather you drop this altogether. I just want to differentiate which interrupt belongs to which PLIC Instance in /proc/interrupts. I can take a different approach if you suggest. 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 060a9c3c-d440-4db8-342f-08d7f9993e5d X-MS-Exchange-CrossTenant-originalarrivaltime: 16 May 2020 13:01:26.7073 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pO7rYZC7yzFrJWHyKrbB2w+O6KM1C5LRVLE0t4Ah4/qIvosz5352N1kDOWu21W7sukvySv1hX0Lv7Pqh9RM+KA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR04MB6969 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200516_060130_314175_A39AD79B X-CRM114-Status: GOOD ( 24.82 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Cooper , Anup Patel , "linux-kernel@vger.kernel.org" , Atish Patra , Palmer Dabbelt , Paul Walmsley , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Marc Zyngier > Sent: 16 May 2020 17:59 > To: Anup Patel > Cc: Palmer Dabbelt ; Paul Walmsley > ; Thomas Gleixner ; Jason > Cooper ; Atish Patra ; Alistai= r > Francis ; Anup Patel ; lin= ux- > riscv@lists.infradead.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 3/4] irqchip/sifive-plic: Separate irq_chip for muilt= iple PLIC > instances >=20 > On 2020-05-16 07:39, Anup Patel wrote: > > To distinguish interrupts from multiple PLIC instances, we use a > > per-PLIC irq_chip instance with a different name. > > > > Signed-off-by: Anup Patel > > --- > > drivers/irqchip/irq-sifive-plic.c | 28 +++++++++++++++------------- > > 1 file changed, 15 insertions(+), 13 deletions(-) > > > > diff --git a/drivers/irqchip/irq-sifive-plic.c > > b/drivers/irqchip/irq-sifive-plic.c > > index 2d3db927a551..e42fc082ad18 100644 > > --- a/drivers/irqchip/irq-sifive-plic.c > > +++ b/drivers/irqchip/irq-sifive-plic.c > > @@ -60,6 +60,7 @@ > > #define PLIC_ENABLE_THRESHOLD 0 > > > > struct plic_priv { > > + struct irq_chip chip; > > struct cpumask lmask; > > struct irq_domain *irqdomain; > > void __iomem *regs; > > @@ -76,6 +77,7 @@ struct plic_handler { > > void __iomem *enable_base; > > struct plic_priv *priv; > > }; > > +static unsigned int plic_count; > > static bool plic_cpuhp_setup_done; > > static DEFINE_PER_CPU(struct plic_handler, plic_handlers); > > > > @@ -164,20 +166,12 @@ static void plic_irq_eoi(struct irq_data *d) > > writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); } > > > > -static struct irq_chip plic_chip =3D { > > - .name =3D "SiFive PLIC", > > - .irq_mask =3D plic_irq_mask, > > - .irq_unmask =3D plic_irq_unmask, > > - .irq_eoi =3D plic_irq_eoi, > > -#ifdef CONFIG_SMP > > - .irq_set_affinity =3D plic_set_affinity, > > -#endif > > -}; > > - > > static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, > > irq_hw_number_t hwirq) > > { > > - irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, > > + struct plic_priv *priv =3D d->host_data; > > + > > + irq_domain_set_info(d, irq, hwirq, &priv->chip, d->host_data, > > handle_fasteoi_irq, NULL, NULL); > > irq_set_noprobe(irq); > > return 0; > > @@ -294,6 +288,14 @@ static int __init plic_init(struct device_node > > *node, > > if (!priv) > > return -ENOMEM; > > > > + priv->chip.name =3D kasprintf(GFP_KERNEL, "PLIC%d", plic_count++); > > + priv->chip.irq_mask =3D plic_irq_mask, > > + priv->chip.irq_unmask =3D plic_irq_unmask, > > + priv->chip.irq_eoi =3D plic_irq_eoi, > > +#ifdef CONFIG_SMP > > + priv->chip.irq_set_affinity =3D plic_set_affinity, #endif > > + > > priv->regs =3D of_iomap(node, 0); > > if (WARN_ON(!priv->regs)) { > > error =3D -EIO; > > @@ -383,9 +385,9 @@ static int __init plic_init(struct device_node > > *node, > > } > > > > pr_info("interrupt-controller at 0x%llx " > > - "(interrupts=3D%d, contexts=3D%d, handlers=3D%d)\n", > > + "(interrupts=3D%d, contexts=3D%d, handlers=3D%d) (%s)\n", > > (unsigned long long)iores.start, nr_irqs, > > - nr_contexts, nr_handlers); > > + nr_contexts, nr_handlers, priv->chip.name); > > set_handle_irq(plic_handle_irq); > > return 0; >=20 > I really dislike this patch for multiple reasons: >=20 > - Allocating a new struc irq_chip just for a string seems over the top, > specially as all the *useful* stuff stays the same. >=20 > - Even if I hate it, /proc is API. I'm sure something, somewhere is > parsing this. Changing the string is likely to confuse it. AFAIK, we don't have scripts in RISC-V world that depend on /proc/interrupts content. May be in future such scripts will show up. For system with multiple PLICs, we are seeing same "SiFive PLIC" string for all PLIC interrupts in "cat /proc/interrupts". I am trying to assign different string based on PLIC instance. This is similar to what GICv2 driver is doing (e.g. GIC-0, GIC-1, ... in /proc/interrupts). Is there a better way to do this ? >=20 > - If you do this for debug purposes, then CONFIG_GENERIC_IRQ_DEBUGFS > is the right way to look up the information. >=20 > - If, for reasons that are beyond me, you actually *need* this, then > implementing irq_print_chip in your irq_chip structure is the way > to go. >=20 > But frankly, I'd rather you drop this altogether. I just want to differentiate which interrupt belongs to which PLIC Instance in /proc/interrupts. I can take a different approach if you suggest. Regards, Anup